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diff --git a/sys/amd64/include/pmc_mdep.h b/sys/amd64/include/pmc_mdep.h
--- a/sys/amd64/include/pmc_mdep.h
+++ b/sys/amd64/include/pmc_mdep.h
@@ -45,6 +45,7 @@
#include <dev/hwpmc/hwpmc_rapl.h>
#include <dev/hwpmc/hwpmc_tsc.h>
#include <dev/hwpmc/hwpmc_uncore.h>
+#include <dev/hwpmc/hwpmc_perf.h>
/*
* Intel processors implementing V2 and later of the Intel performance
@@ -66,6 +67,7 @@
* TSC The timestamp counter
* K8 AMD Athlon64 and Opteron PMCs in 64 bit mode.
* IBS AMD IBS
+ * PERF AMD MPERF / APERF
* IAP Intel Core/Core2/Atom CPUs in 64 bits mode.
* IAF Intel fixed-function PMCs in Core2 and later CPUs.
* UCP Intel Uncore programmable PMCs.
diff --git a/sys/conf/files.x86 b/sys/conf/files.x86
--- a/sys/conf/files.x86
+++ b/sys/conf/files.x86
@@ -118,6 +118,7 @@
dev/hptrr/hptrr_config.c optional hptrr
dev/hptrr/$M-elf.hptrr_lib.o optional hptrr
dev/hwpmc/hwpmc_amd.c optional hwpmc
+dev/hwpmc/hwpmc_perf.c optional hwpmc
dev/hwpmc/hwpmc_ibs.c optional hwpmc
dev/hwpmc/hwpmc_intel.c optional hwpmc
dev/hwpmc/hwpmc_core.c optional hwpmc
diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c
--- a/sys/dev/hwpmc/hwpmc_amd.c
+++ b/sys/dev/hwpmc/hwpmc_amd.c
@@ -1090,6 +1090,17 @@
nclasses = 3;
}
+ /*
+ * Detect support for MPERF and APERF MSRs. tsc_perf_stat is set by the
+ * kernel's generic TSC initialization (start_TSC(), called at boot via
+ * cpu_startup() -> startrtclock()), not by hwpmc's TSC PMC class. It is
+ * set only after confirming both MSRs actually increment (some emulators
+ * expose the CPUID bit without real MSR support).
+ */
+ if ((cpu_power_ecx & CPUID_PERF_STAT) && (tsc_perf_stat == 1)) {
+ nclasses++;
+ }
+
pmc_mdep = pmc_mdep_alloc(nclasses);
ncpus = pmc_cpu_max();
@@ -1139,6 +1150,15 @@
goto error;
}
+ if ((cpu_power_ecx & CPUID_PERF_STAT) && (tsc_perf_stat == 1)) {
+ /* The PERF class is the one right after IBS. */
+ int perf_classindex = nclasses - 1;
+ /* Initialize PERF class. */
+ error = pmc_perf_initialize(pmc_mdep, ncpus, perf_classindex);
+ if (error != 0)
+ goto error;
+ }
+
/* RAPL takes the reserved last slot; drop it if the probe fails. */
error = pmc_rapl_initialize(pmc_mdep, ncpus, pmc_mdep->pmd_nclass - 1);
if (error != 0)
@@ -1164,6 +1184,10 @@
pmc_tsc_finalize(md);
+ if ((cpu_power_ecx & CPUID_PERF_STAT) && (tsc_perf_stat == 1)) {
+ pmc_perf_finalize(md);
+ }
+
for (int i = 0; i < pmc_cpu_max(); i++)
KASSERT(amd_pcpu[i] == NULL,
("[amd,%d] non-null pcpu cpu %d", __LINE__, i));
diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h
--- a/sys/dev/hwpmc/pmc_events.h
+++ b/sys/dev/hwpmc/pmc_events.h
@@ -62,6 +62,14 @@
#define PMC_EV_RAPL_FIRST PMC_EV_RAPL_ENERGY_PKG
#define PMC_EV_RAPL_LAST PMC_EV_RAPL_ENERGY_DRAM
+/* MPERF / APERF MSRs */
+#define __PMC_EV_PERF() \
+ __PMC_EV(PERF, MPERF) \
+ __PMC_EV(PERF, APERF) \
+
+#define PMC_EV_PERF_FIRST PMC_EV_PERF_MPERF
+#define PMC_EV_PERF_LAST PMC_EV_PERF_APERF
+
/*
* Software events are dynamically defined.
*/
@@ -2416,6 +2424,7 @@
* START #EVENTS DESCRIPTION
* 0 0x1000 Reserved
* 0x1000 0x0001 TSC
+ * 0x1001 0x0002 PERF MSRs events
* 0x2000 0x0080 AMD IBS (was AMD K7 events)
* 0x2080 0x0100 AMD K8 events
* 0x10000 0x0080 INTEL architectural fixed-function events
@@ -2443,6 +2452,8 @@
#define __PMC_EVENTS() \
__PMC_EV_BLOCK(TSC, 0x01000) \
__PMC_EV_TSC() \
+ __PMC_EV_BLOCK(PERF, 0x01001) \
+ __PMC_EV_PERF() \
__PMC_EV_BLOCK(IBS, 0x02000) \
__PMC_EV_IBS() \
__PMC_EV_BLOCK(K8, 0x02080) \
diff --git a/sys/i386/include/pmc_mdep.h b/sys/i386/include/pmc_mdep.h
--- a/sys/i386/include/pmc_mdep.h
+++ b/sys/i386/include/pmc_mdep.h
@@ -53,6 +53,7 @@
#include <dev/hwpmc/hwpmc_ibs.h>
#include <dev/hwpmc/hwpmc_core.h>
#include <dev/hwpmc/hwpmc_rapl.h>
+#include <dev/hwpmc/hwpmc_perf.h>
#include <dev/hwpmc/hwpmc_tsc.h>
#include <dev/hwpmc/hwpmc_uncore.h>
diff --git a/sys/modules/hwpmc/Makefile b/sys/modules/hwpmc/Makefile
--- a/sys/modules/hwpmc/Makefile
+++ b/sys/modules/hwpmc/Makefile
@@ -25,6 +25,7 @@
hwpmc_ibs.c \
hwpmc_intel.c \
hwpmc_rapl.c \
+ hwpmc_perf.c \
hwpmc_tsc.c \
hwpmc_uncore.c \
hwpmc_x86.c
@@ -38,6 +39,7 @@
hwpmc_core.c \
hwpmc_ibs.c \
hwpmc_intel.c \
+ hwpmc_perf.c \
hwpmc_tsc.c \
hwpmc_uncore.c \
hwpmc_x86.c
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -60,7 +60,7 @@
* The patch version is incremented for every bug fix.
*/
#define PMC_VERSION_MAJOR 0x0A
-#define PMC_VERSION_MINOR 0x02
+#define PMC_VERSION_MINOR 0x03
#define PMC_VERSION_PATCH 0x0000
#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
@@ -141,6 +141,7 @@
*/
#define __PMC_CLASSES() \
__PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
+ __PMC_CLASS(PERF, 0x01, "AMD PERF MSRs") \
__PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
__PMC_CLASS(IBS, 0x03, "AMD IBS performance counters") \
__PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \

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