Page MenuHomeFreeBSD
Files F168049797

D56619.id176330.diff
No OneTemporary
Actions

D56619.id176330.diff
View Options

diff --git a/sys/dev/amdsmu/amdsmu.h b/sys/dev/amdsmu/amdsmu.h
--- a/sys/dev/amdsmu/amdsmu.h
+++ b/sys/dev/amdsmu/amdsmu.h
@@ -27,13 +27,16 @@
uint16_t amdsmu_deviceid;
int16_t idlemask_reg;
size_t ip_block_count;
+ uint32_t amdsmu_msg;
} amdsmu_products[] = {
{ CPU_VENDOR_AMD, PCI_DEVICEID_AMD_CEZANNE_ROOT,
- SMU_REG_IDLEMASK_CEZANNE, 12 },
+ SMU_REG_IDLEMASK_CEZANNE, 12 , 0x538},
{ CPU_VENDOR_AMD, PCI_DEVICEID_AMD_REMBRANDT_ROOT,
- SMU_REG_IDLEMASK_PHOENIX, 12 },
+ SMU_REG_IDLEMASK_PHOENIX, 12 , 0x538},
{ CPU_VENDOR_AMD, PCI_DEVICEID_AMD_PHOENIX_ROOT,
- SMU_REG_IDLEMASK_PHOENIX, 21 },
+ SMU_REG_IDLEMASK_PHOENIX, 21 , 0x538},
+ { CPU_VENDOR_AMD, PCI_DEVICEID_AMD_KRACKAN_POINT_ROOT,
+ SMU_REG_IDLEMASK_KRACKAN, 22, 0x938 },
/*
* XXX Strix Point (PCI_DEVICEID_AMD_STRIX_POINT_ROOT) doesn't support
* S0i3 and thus doesn't have an idlemask. Since our driver doesn't
@@ -96,6 +99,7 @@
bus_space_handle_t metrics_space;
struct amdsmu_metrics metrics;
uint32_t idlemask;
+ uint32_t smu_msg;
};
static inline uint32_t
diff --git a/sys/dev/amdsmu/amdsmu.c b/sys/dev/amdsmu/amdsmu.c
--- a/sys/dev/amdsmu/amdsmu.c
+++ b/sys/dev/amdsmu/amdsmu.c
@@ -105,7 +105,7 @@
amdsmu_write4(sc, SMU_REG_RESPONSE, SMU_RES_WAIT);
/* Write out command to registers. */
- amdsmu_write4(sc, SMU_REG_MESSAGE, msg);
+ amdsmu_write4(sc, sc->product->amdsmu_msg, msg);
amdsmu_write4(sc, SMU_REG_ARGUMENT, arg);
/* Wait for SMU response and handle it. */
diff --git a/sys/dev/amdsmu/amdsmu_reg.h b/sys/dev/amdsmu/amdsmu_reg.h
--- a/sys/dev/amdsmu/amdsmu_reg.h
+++ b/sys/dev/amdsmu/amdsmu_reg.h
@@ -16,6 +16,7 @@
* out? Also, there are way more of these. I couldn't find a centralized place
* which lists them though.
*/
+#define PCI_DEVICEID_AMD_KRACKAN_POINT_ROOT 0x1122
#define PCI_DEVICEID_AMD_CEZANNE_ROOT 0x1630
#define PCI_DEVICEID_AMD_REMBRANDT_ROOT 0x14B5
#define PCI_DEVICEID_AMD_PHOENIX_ROOT 0x14E8
@@ -28,14 +29,15 @@
#define SMU_PHYSBASE_ADDR_HI 0x13B102EC
#define SMU_MEM_SIZE 0x1000
+
#define SMU_REG_SPACE_OFF 0x10000
-#define SMU_REG_MESSAGE 0x538
#define SMU_REG_RESPONSE 0x980
#define SMU_REG_ARGUMENT 0x9BC
#define SMU_REG_IDLEMASK_CEZANNE 0x94
#define SMU_REG_IDLEMASK_PHOENIX 0xD14
+#define SMU_REG_IDLEMASK_KRACKAN 0xF14
enum amdsmu_res {
SMU_RES_WAIT = 0x00,

File Metadata

Mime Type
text/plain
Expires
Thu, Aug 27, 3:33 AM (5 h, 27 m)
Storage Engine
blob
Storage Format
Raw Data
Storage Handle
37347748
Default Alt Text
D56619.id176330.diff (2 KB)

Event Timeline