D15506.id.diff
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D15506.id.diff
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	Index: head/sys/amd64/amd64/pmap.c
	===================================================================
	--- head/sys/amd64/amd64/pmap.c
	+++ head/sys/amd64/amd64/pmap.c
	@@ -1721,6 +1721,18 @@
	if (cpuid != i)
	pmap->pm_pcids[i].pm_gen = 0;
	}
	+
	+ /*
	+ * The fence is between stores to pm_gen and the read of
	+ * the pm_active mask. We need to ensure that it is
	+ * impossible for us to miss the bit update in pm_active
	+ * and simultaneously observe a non-zero pm_gen in
	+ * pmap_activate_sw(), otherwise TLB update is missed.
	+ * Without the fence, IA32 allows such an outcome.
	+ * Note that pm_active is updated by a locked operation,
	+ * which provides the reciprocal fence.
	+ */
	+ atomic_thread_fence_seq_cst();
	}
	mask = &pmap->pm_active;
	}
	@@ -1792,6 +1804,8 @@
	if (cpuid != i)
	pmap->pm_pcids[i].pm_gen = 0;
	}
	+ /* See comment int pmap_invalidate_page(). */
	+ atomic_thread_fence_seq_cst();
	}
	mask = &pmap->pm_active;
	}
	@@ -1863,6 +1877,8 @@
	if (cpuid != i)
	pmap->pm_pcids[i].pm_gen = 0;
	}
	+ /* See comment int pmap_invalidate_page(). */
	+ atomic_thread_fence_seq_cst();
	}
	mask = &pmap->pm_active;
	}