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diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -166,6 +166,188 @@
#define APIBKeyLo_EL1_CRm 1
#define APIBKeyLo_EL1_op2 2
+/* BRBCR_EL1 - Branch Record Buffer Control Register */
+#define BRBCR_EL1_REG MRS_REG_ALT_NAME(BRBCR_EL1)
+#define BRBCR_EL1_op0 2
+#define BRBCR_EL1_op1 1
+#define BRBCR_EL1_CRn 9
+#define BRBCR_EL1_CRm 0
+#define BRBCR_EL1_op2 0
+#define BRBCR_EXCEPTION_SHIFT 23
+#define BRBCR_EXCEPTION_MASK (1 << BRBCR_EXCEPTION_SHIFT)
+#define BRBCR_ERTN_SHIFT 22
+#define BRBCR_ERTN_MASK (1 << BRBCR_ERTN_SHIFT)
+#define BRBCR_FZPSS_SHIFT 9
+#define BRBCR_FZPSS_MASK (1 << BRBCR_FZPSS_SHIFT)
+#define BRBCR_FZP_SHIFT 8
+#define BRBCR_FZP_MASK (1 << BRBCR_FZP_SHIFT)
+#define BRBCR_TS_SHIFT 5
+#define BRBCR_TS_MASK (3 << BRBCR_TS_SHIFT)
+#define BRBCR_TS_VIRTUAL (1 << BRBCR_TS_SHIFT)
+#define BRBCR_TS_GUEST_PHYSICAL (2 << BRBCR_TS_SHIFT)
+#define BRBCR_TS_PHYSICAL (3 << BRBCR_TS_SHIFT)
+#define BRBCR_MPRED_SHIFT 4
+#define BRBCR_MPRED_MASK (1 << BRBCR_MPRED_SHIFT)
+#define BRBCR_CC_SHIFT 3
+#define BRBCR_CC_MASK (1 << BRBCR_CC_SHIFT)
+#define BRBCR_E1BRE_SHIFT 1
+#define BRBCR_E1BRE_MASK (1 << BRBCR_E1BRE_SHIFT)
+#define BRBCR_E0BRE_SHIFT 0
+#define BRBCR_E0BRE_MASK (1 << BRBCR_E0BRE_SHIFT)
+
+/* BRBFCR_EL1 - Branch Record Buffer Function Control Register */
+#define BRBFCR_EL1_REG MRS_REG_ALT_NAME(BRBFCR_EL1)
+#define BRBFCR_EL1_op0 2
+#define BRBFCR_EL1_op1 1
+#define BRBFCR_EL1_CRn 9
+#define BRBFCR_EL1_CRm 0
+#define BRBFCR_EL1_op2 1
+#define BRBFCR_BANK_SHIFT 28
+#define BRBFCR_BANK_MASK (3 << BRBFCR_BANK_SHIFT)
+#define BRBFCR_BANK_0_31 (0 << BRBFCR_BANK_SHIFT)
+#define BRBFCR_BANK_32_63 (1 << BRBFCR_BANK_SHIFT)
+#define BRBFCR_CONDDIR_SHIFT 22
+#define BRBFCR_CONDDIR_MASK (1 << BRBFCR_CONDDIR_SHIFT)
+#define BRBFCR_DIRCALL_SHIFT 21
+#define BRBFCR_DIRCALL_MASK (1 << BRBFCR_DIRCALL_SHIFT)
+#define BRBFCR_INDCALL_SHIFT 20
+#define BRBFCR_INDCALL_MASK (1 << BRBFCR_INDCALL_SHIFT)
+#define BRBFCR_RTN_SHIFT 19
+#define BRBFCR_RTN_MASK (1 << BRBFCR_RTN_SHIFT)
+#define BRBFCR_INDIRECT_SHIFT 18
+#define BRBFCR_INDIRECT_MASK (1 << BRBFCR_INDIRECT_SHIFT)
+#define BRBFCR_DIRECT_SHIFT 17
+#define BRBFCR_DIRECT_MASK (1 << BRBFCR_DIRECT_SHIFT)
+#define BRBFCR_EnI_SHIFT 16
+#define BRBFCR_EnI_MASK (1 << BRBFCR_EnI_SHIFT)
+#define BRBFCR_PAUSED_SHIFT 7
+#define BRBFCR_PAUSED_MASK (1 << BRBFCR_PAUSED_SHIFT)
+
+/* BRBIDR0_EL1 - Branch Record Buffer ID0 Register */
+#define BRBIDR0_EL1_REG MRS_REG_ALT_NAME(BRBIDR0_EL1)
+#define BRBIDR0_EL1_op0 2
+#define BRBIDR0_EL1_op1 1
+#define BRBIDR0_EL1_CRn 9
+#define BRBIDR0_EL1_CRm 2
+#define BRBIDR0_EL1_op2 0
+#define BRBIDR0_CC_SHIFT 12
+#define BRBIDR0_CC_MASK (0xf << BRBIDR0_CC_SHIFT)
+#define BRBIDR0_CC_20BIT (0x5 << BRBIDR0_CC_SHIFT)
+#define BRBIDR0_FORMAT_SHIFT 8
+#define BRBIDR0_FORMAT_MASK (0xf << BRBIDR0_FORMAT_SHIFT)
+#define BRBIDR0_FORMAT_0 (0 << BRBIDR0_FORMAT_SHIFT)
+#define BRBIDR0_NUMREC_SHIFT 0
+#define BRBIDR0_NUMREC_MASK (0xff << BRBIDR0_NUMREC_SHIFT)
+#define BRBIDR0_NUMREC_8 (8 << BRBIDR0_NUMREC_SHIFT)
+#define BRBIDR0_NUMREC_16 (16 << BRBIDR0_NUMREC_SHIFT)
+#define BRBIDR0_NUMREC_32 (32 << BRBIDR0_NUMREC_SHIFT)
+#define BRBIDR0_NUMREC_64 (64 << BRBIDR0_NUMREC_SHIFT)
+
+/*
+ * BRBINFINJ_EL1 - Branch Record Buffer Information Injection Control Register
+ */
+#define BRBINFINJ_EL1_REG MRS_REG_ALT_NAME(BRBINFINJ_EL1)
+#define BRBINFINJ_EL1_op0 2
+#define BRBINFINJ_EL1_op1 1
+#define BRBINFINJ_EL1_CRn 9
+#define BRBINFINJ_EL1_CRm 1
+#define BRBINFINJ_EL1_op2 0
+
+/* BRBINF<n>_EL1 - Branch Record Buffer Information Register <n>, n = 0 - 31 */
+#define BRBINFn_EL1_REG(n) MRS_REG_ALT_NAME_n(BRBINFn_EL1, n)
+#define BRBINFn_EL1_op0 2
+#define BRBINFn_EL1_op1 1
+#define BRBINFn_EL1_CRn 8
+
+#define BRBINF_CCU_SHIFT 46
+#define BRBINF_CCU_MASK (1 << BRBINF_CCU_SHIFT)
+#define BRBINF_CC_SHIFT 32
+#define BRBINF_CC_MASK (0x3fff << BRBINF_CC_SHIFT)
+#define BRBINF_CC_M_SHIFT 40
+#define BRBINF_CC_M_MASK (0x3f << BRBINF_CC_M_SHIFT)
+#define BRBINF_CC_E_SHIFT 32
+#define BRBINF_CC_E_MASK (0xff << BRBINF_CC_E_SHIFT)
+#define BRBINF_TYPE_SHIFT 8
+#define BRBINF_TYPE_MASK (0x3f << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_DIRECT_BRANCH (0x00 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_INDIRECT_BRANCH (0x01 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_DIRECT_BRANCH_LINK (0x02 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_INDIRECT_BRANCH_LINK (0x03 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_RETURN_SUBR (0x05 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_EXCEPTION_RETURN (0x07 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_COND_DIRECT_BRANCH (0x08 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_DEBUG_HALT (0x21 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_CALL (0x22 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_TRAP (0x23 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_SERROR (0x24 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_INSTRUCTION_DEBUG (0x26 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_DATA_DEBUG (0x27 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_ALIGNMENT (0x2a << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_INSTRUCTION_FAULT (0x2b << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_DATA_FAULT (0x2c << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_IRQ (0x2e << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_FIQ (0x2f << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_IMPDEF_EL3 (0x30 << BRBINF_TYPE_SHIFT)
+#define BRBINF_TYPE_DEBUG_STATE_EXIT (0x39 << BRBINF_TYPE_SHIFT)
+#define BRBINF_EL_SHIFT 6
+#define BRBINF_EL_MASK (3 << BRBINF_EL_SHIFT)
+#define BRBINF_EL_EL0 (0 << BRBINF_EL_SHIFT)
+#define BRBINF_EL_EL1 (1 << BRBINF_EL_SHIFT)
+#define BRBINF_EL_EL2 (2 << BRBINF_EL_SHIFT)
+#define BRBINF_EL_EL3 (3 << BRBINF_EL_SHIFT)
+#define BRBINF_MPRED_SHIFT 5
+#define BRBINF_MPRED_MASK (1 << BRBINF_MPRED_SHIFT)
+#define BRBINF_VALID_SHIFT 0
+#define BRBINF_VALID_MASK (3 << BRBINF_VALID_SHIFT)
+#define BRBINF_VALID_NOT_VALID (0 << BRBINF_VALID_SHIFT)
+#define BRBINF_VALID_HALF_TARGET (1 << BRBINF_VALID_SHIFT)
+#define BRBINF_VALID_HALF_SOURCE (2 << BRBINF_VALID_SHIFT)
+#define BRBINF_VALID_FULL_BRANCH (3 << BRBINF_VALID_SHIFT)
+
+/* BRBSRCINJ_EL1 - Branch Record Buffer Source Address Injection Register */
+#define BRBSRCINJ_EL1_REG MRS_REG_ALT_NAME(BRBSRCINJ_EL1)
+#define BRBSRCINJ_EL1_op0 2
+#define BRBSRCINJ_EL1_op1 1
+#define BRBSRCINJ_EL1_CRn 9
+#define BRBSRCINJ_EL1_CRm 1
+#define BRBSRCINJ_EL1_op2 1
+
+/*
+ * BRBSRC<n>_EL1 - Branch Record Buffer Source Address Register <n>, n = 0 - 31
+ */
+#define BRBSRCn_EL1_REG MRS_REG_ALT_NAME(BRBSRCn_EL1)
+#define BRBSRCn_EL1_op0 2
+#define BRBSRCn_EL1_op1 1
+#define BRBSRCn_EL1_CRn 8
+#define BRBSRCn_EL1_CRm(n) ((n) & 0xf)
+#define BRBSRCn_EL1_op2(n) ((((n) & 0x10) >> 1) | 1)
+
+/* BRBTGTINJ_EL1 - Branch Record Buffer Target Address Injection Register */
+#define BRBTGTINJ_EL1_REG MRS_REG_ALT_NAME(BRBTGTINJ_EL1)
+#define BRBTGTINJ_EL1_op0 2
+#define BRBTGTINJ_EL1_op1 1
+#define BRBTGTINJ_EL1_CRn 9
+#define BRBTGTINJ_EL1_CRm 1
+#define BRBTGTINJ_EL1_op2 2
+
+/*
+ * BRBTGT<n>_EL1 - Branch Record Buffer Target Address Register <n>, n = 0 - 31
+ */
+#define BRBTGTn_EL1_REG MRS_REG_ALT_NAME(BRBTGTn_EL1)
+#define BRBTGTn_EL1_op0 2
+#define BRBTGTn_EL1_op1 1
+#define BRBTGTn_EL1_CRn 8
+#define BRBTGTn_EL1_CRm(n) ((n) & 0xf)
+#define BRBTGTn_EL1_op2(n) ((((n) & 0x10) >> 1) | 2)
+
+/* BRBTS_EL1 - Branch Record Buffer Timestamp Register */
+#define BRBTS_EL1_REG MRS_REG_ALT_NAME(BRBTS_EL1)
+#define BRBTS_EL1_op0 2
+#define BRBTS_EL1_op1 1
+#define BRBTS_EL1_CRn 9
+#define BRBTS_EL1_CRm 0
+#define BRBTS_EL1_op2 2
+
/* CCSIDR_EL1 - Cache Size ID Register */
#define CCSIDR_EL1_REG MRS_REG_ALT_NAME(CCSIDR_EL1)
#define CCSIDR_EL1_op0 2

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