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Index: head/sys/arm/mv/armada/wdt.c
===================================================================
--- head/sys/arm/mv/armada/wdt.c
+++ head/sys/arm/mv/armada/wdt.c
@@ -245,9 +245,9 @@
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
- val = read_cpu_misc(RSTOUTn_MASK);
+ val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val &= ~RSTOUTn_MASK_WD;
- write_cpu_misc(RSTOUTn_MASK, val);
+ write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
}
static void
@@ -305,9 +305,9 @@
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
- val = read_cpu_misc(RSTOUTn_MASK);
+ val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val |= RSTOUTn_MASK_WD;
- write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
+ write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
}
static void
Index: head/sys/arm/mv/mv_armv7_machdep.c
===================================================================
--- head/sys/arm/mv/mv_armv7_machdep.c
+++ head/sys/arm/mv/mv_armv7_machdep.c
@@ -439,8 +439,8 @@
mv_cpu_reset(platform_t plat)
{
- write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
- write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
+ write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7);
+ write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7);
}
#if defined(SOC_MV_ARMADA38X)
Index: head/sys/arm/mv/mvreg.h
===================================================================
--- head/sys/arm/mv/mvreg.h
+++ head/sys/arm/mv/mvreg.h
@@ -103,17 +103,15 @@
/*
* System reset
*/
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
-#define RSTOUTn_MASK 0x60
-#define SYSTEM_SOFT_RESET 0x64
-#define SOFT_RST_OUT_EN 0x00000001
-#define SYS_SOFT_RST 0x00000001
-#else
+#define RSTOUTn_MASK_ARMV7 0x60
+#define SYSTEM_SOFT_RESET_ARMV7 0x64
+#define SOFT_RST_OUT_EN_ARMV7 0x00000001
+#define SYS_SOFT_RST_ARMV7 0x00000001
+
#define RSTOUTn_MASK 0x8
#define SOFT_RST_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET 0xc
#define SYS_SOFT_RST 0x00000001
-#endif
#define RSTOUTn_MASK_WD 0x400
#define WD_RSTOUTn_MASK 0x4
#define WD_GLOBAL_MASK 0x00000100
Index: head/sys/arm/mv/timer.c
===================================================================
--- head/sys/arm/mv/timer.c
+++ head/sys/arm/mv/timer.c
@@ -411,9 +411,9 @@
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
- val = read_cpu_misc(RSTOUTn_MASK);
+ val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val &= ~RSTOUTn_MASK_WD;
- write_cpu_misc(RSTOUTn_MASK, val);
+ write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
val = mv_get_timer_control();
val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
@@ -451,9 +451,9 @@
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
- val = read_cpu_misc(RSTOUTn_MASK);
+ val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
val |= RSTOUTn_MASK_WD;
- write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
+ write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER_WD_CLR;

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