D31181.id92196.diff
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	Index: sys/arm64/arm64/pmap.c
	===================================================================
	--- sys/arm64/arm64/pmap.c
	+++ sys/arm64/arm64/pmap.c
	@@ -4035,7 +4035,7 @@
	if (pmap != kernel_pmap)
	new_l2 \|= ATTR_S1_nG;
	return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP \|
	- PMAP_ENTER_NOREPLACE \| PMAP_ENTER_NORECLAIM, NULL, lockp) ==
	+ PMAP_ENTER_NOREPLACE \| PMAP_ENTER_NORECLAIM, m, lockp) ==
	KERN_SUCCESS);
	}

	@@ -4065,8 +4065,6 @@
	* KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
	* page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
	* PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
	- *
	- * The parameter "m" is only used when creating a managed, writeable mapping.
	*/
	static int
	pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
	@@ -4153,6 +4151,16 @@
	pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
	pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;

	+ /*
	+ * Conditionally sync the icache. See pmap_enter() for details.
	+ */
	+ if ((new_l2 & ATTR_S1_XN) == 0 && ((new_l2 & ~ATTR_MASK) !=
	+ (old_l2 & ~ATTR_MASK) \|\| (old_l2 & ATTR_S1_XN) != 0) &&
	+ m->md.pv_memattr == VM_MEMATTR_WRITE_BACK && pmap != kernel_pmap) {
	+ cpu_icache_sync_range(PHYS_TO_DMAP(new_l2 & ~ATTR_MASK),
	+ L2_SIZE);
	+ }
	+
	/*
	* Map the superpage.
	*/