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diff --git a/sys/arm64/arm64/busdma_bounce.c b/sys/arm64/arm64/busdma_bounce.c
--- a/sys/arm64/arm64/busdma_bounce.c
+++ b/sys/arm64/arm64/busdma_bounce.c
@@ -196,7 +196,7 @@
return (false);
if (map != NULL && (map->flags & DMAMAP_CACHELINE_FLAGS) != 0)
return (false);
- return (((paddr | size) & (dcache_line_size - 1)) != 0);
+ return (((paddr | size) & (cache_wb_max - 1)) != 0);
#undef DMAMAP_CACHELINE_FLAGS
}
@@ -301,9 +301,9 @@
* causing the cache to become dirty.
*/
newtag->alloc_alignment = MAX(newtag->common.alignment,
- dcache_line_size);
+ cache_wb_max);
newtag->alloc_size = roundup2(newtag->common.maxsize,
- dcache_line_size);
+ cache_wb_max);
}
if (newtag->common.lowaddr < ptoa((vm_paddr_t)Maxmem) ||
@@ -968,14 +968,19 @@
static void
dma_preread_safe(char *va, vm_size_t size)
{
+ char *va_end;
+
/*
* Write back any partial cachelines immediately before and
* after the DMA region.
*/
- if (!__is_aligned(va, dcache_line_size))
- cpu_dcache_wb_range(va, 1);
- if (!__is_aligned(va + size, dcache_line_size))
- cpu_dcache_wb_range(va + size, 1);
+ if (!__is_aligned(va, cache_wb_max))
+ cpu_dcache_wb_range(va, roundup2(va, cache_wb_max) - va);
+
+ va_end = va + size;
+ if (!__is_aligned(va + size, cache_wb_max))
+ cpu_dcache_wb_range(rounddown2(va_end, cache_wb_max),
+ va_end - rounddown2(va_end, cache_wb_max));
cpu_dcache_inv_range(va, size);
}
@@ -1195,13 +1200,13 @@
{
if (in_realm())
nonsecure_allocator = busdma_bufalloc_create("nonsecure",
- dcache_line_size, /* minimum_alignment */
+ cache_wb_max, /* minimum_alignment */
nonsecure_alloc, /* uma_alloc func */
nonsecure_free, /* uma_free func */
UMA_ZONE_NOTOUCH); /* uma_zcreate_flags */
else
nonsecure_allocator = busdma_bufalloc_create("nonsecure",
- dcache_line_size, /* minimum_alignment */
+ cache_wb_max, /* minimum_alignment */
NULL, /* uma_alloc func */
NULL, /* uma_free func */
UMA_ZONE_NOTOUCH); /* uma_zcreate_flags */
diff --git a/sys/arm64/arm64/cpufunc_asm.S b/sys/arm64/arm64/cpufunc_asm.S
--- a/sys/arm64/arm64/cpufunc_asm.S
+++ b/sys/arm64/arm64/cpufunc_asm.S
@@ -39,7 +39,6 @@
/*
* FIXME:
* Need big.LITTLE awareness at some point.
- * Using arm64_p[id]cache_line_size may not be the best option.
* Need better SMP awareness.
*/
.text
@@ -53,12 +52,11 @@
* in x1. It will corrupt x0, x1, x2, x3, and x4.
*/
.macro cache_handle_range dcop = 0, ic = 0, icop = 0
-.if \ic == 0
- adrp x3, dcache_line_size /* Load the D cache line size */
- ldr x3, [x3, :lo12:dcache_line_size]
-.else
- adrp x3, idcache_line_size /* Load the I & D cache line size */
- ldr x3, [x3, :lo12:idcache_line_size]
+ adrp x3, dcache_line_min /* Load the D cache line size */
+ ldr w3, [x3, :lo12:dcache_line_min]
+.if \ic != 0
+ adrp x5, icache_line_min /* Load the I & D cache line size */
+ ldr w5, [x5, :lo12:icache_line_min]
.endif
sub x4, x3, #1 /* Get the address mask */
and x2, x0, x4 /* Get the low bits of the address */
@@ -77,8 +75,8 @@
.if \ic != 0
2:
ic \icop, x2
- add x2, x2, x3 /* Move to the next line */
- subs x4, x4, x3 /* Reduce the size */
+ add x2, x2, x5 /* Move to the next line */
+ subs x4, x4, x5 /* Reduce the size */
b.hi 2b /* Check if we are done */
dsb ish
isb
diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -2751,9 +2751,11 @@
bool __read_frequently icache_aliasing = false;
bool __read_frequently icache_vmid = false;
-int64_t dcache_line_size; /* The minimum D cache line size */
-int64_t icache_line_size; /* The minimum I cache line size */
-int64_t idcache_line_size; /* The minimum cache line size */
+/* The default writeback cache size when CTR_EL0.CWG == 0 */
+#define CACHE_WB_DEFAULT 128
+uint32_t cache_wb_max; /* The maximum writeback size */
+uint32_t dcache_line_min; /* The minimum D cache line size */
+uint32_t icache_line_min; /* The minimum I cache line size */
/*
* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2.
@@ -3299,6 +3301,7 @@
void
identify_cache(uint64_t ctr)
{
+ uint32_t cwg_size, dline_size, iline_size;
/* Identify the L1 cache type */
switch (CTR_L1IP_VAL(ctr)) {
@@ -3310,27 +3313,37 @@
break;
}
- if (dcache_line_size == 0) {
- KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld",
- __func__, icache_line_size));
+ dline_size = CTR_DLINE_SIZE(ctr);
+ iline_size = CTR_ILINE_SIZE(ctr);
+
+ if (dcache_line_min == 0) {
+ KASSERT(icache_line_min == 0, ("%s: i-cacheline size set: %u",
+ __func__, icache_line_min));
/* Get the D cache line size */
- dcache_line_size = CTR_DLINE_SIZE(ctr);
+ dcache_line_min = dline_size;
/* And the same for the I cache */
- icache_line_size = CTR_ILINE_SIZE(ctr);
-
- idcache_line_size = MIN(dcache_line_size, icache_line_size);
- }
+ icache_line_min = iline_size;
+ } else {
+ if (dcache_line_min != dline_size) {
+ printf("WARNING: D-cacheline size mismatch %u != %u\n",
+ dcache_line_min, dline_size);
+ dcache_line_min = MIN(dcache_line_min, dline_size);
+ }
- if (dcache_line_size != CTR_DLINE_SIZE(ctr)) {
- printf("WARNING: D-cacheline size mismatch %ld != %d\n",
- dcache_line_size, CTR_DLINE_SIZE(ctr));
+ if (icache_line_min != iline_size) {
+ printf("WARNING: I-cacheline size mismatch %u != %u\n",
+ icache_line_min, iline_size);
+ icache_line_min = MIN(icache_line_min, iline_size);
+ }
}
- if (icache_line_size != CTR_ILINE_SIZE(ctr)) {
- printf("WARNING: I-cacheline size mismatch %ld != %d\n",
- icache_line_size, CTR_ILINE_SIZE(ctr));
- }
+ if (CTR_CWG_VAL(ctr) == 0)
+ /* No Cache writeback size, assume a 128 byte alignment */
+ cwg_size = CACHE_WB_DEFAULT;
+ else
+ cwg_size = CTR_CWG_SIZE(ctr);
+ cache_wb_max = MAX(cache_wb_max, cwg_size);
}
void
diff --git a/sys/arm64/include/cpufunc.h b/sys/arm64/include/cpufunc.h
--- a/sys/arm64/include/cpufunc.h
+++ b/sys/arm64/include/cpufunc.h
@@ -188,9 +188,9 @@
extern bool icache_aliasing;
extern bool icache_vmid;
-extern int64_t dcache_line_size;
-extern int64_t icache_line_size;
-extern int64_t idcache_line_size;
+extern uint32_t cache_wb_max;
+extern uint32_t dcache_line_min;
+extern uint32_t icache_line_min;
extern int64_t dczva_line_size;
#define cpu_nullop() arm64_nullop()

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