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diff --git a/diffen b/diffen
new file mode 100644
diff --git a/sys/arm/conf/GENERIC b/sys/arm/conf/GENERIC
--- a/sys/arm/conf/GENERIC
+++ b/sys/arm/conf/GENERIC
@@ -58,7 +58,6 @@
options SOC_MV_ARMADA38X
options SOC_MV_ARMADAXP
options SOC_TI_AM335X
-options SOC_OMAP4
options SCHED_ULE # ULE scheduler
options SMP # Enable multiple cores
@@ -270,7 +269,6 @@
makeoptions MODULES_EXTRA+="dtb/am335x"
makeoptions MODULES_EXTRA+="dtb/imx6"
makeoptions MODULES_EXTRA+="dtb/nvidia"
-makeoptions MODULES_EXTRA+="dtb/omap4"
makeoptions MODULES_EXTRA+="dtb/rockchip"
makeoptions MODULES_EXTRA+="dtb/rpi"
makeoptions MODULES_EXTRA+="dtb/zynq"
diff --git a/sys/arm/conf/NOTES b/sys/arm/conf/NOTES
--- a/sys/arm/conf/NOTES
+++ b/sys/arm/conf/NOTES
@@ -88,6 +88,5 @@
makeoptions MODULES_EXTRA+="dtb/am335x"
makeoptions MODULES_EXTRA+="dtb/imx6"
makeoptions MODULES_EXTRA+="dtb/nvidia"
-makeoptions MODULES_EXTRA+="dtb/omap4"
makeoptions MODULES_EXTRA+="dtb/rpi"
makeoptions MODULES_EXTRA+="dtb/zynq"
diff --git a/sys/arm/ti/clk/ti_clkctrl.c b/sys/arm/ti/clk/ti_clkctrl.c
--- a/sys/arm/ti/clk/ti_clkctrl.c
+++ b/sys/arm/ti/clk/ti_clkctrl.c
@@ -168,12 +168,6 @@
/* Check if this is a clkctrl with special registers like gpio */
switch (ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- /* FIXME: Todo */
- break;
-
-#endif /* SOC_OMAP4 */
#ifdef SOC_TI_AM335X
/* Checkout TRM 8.1.12.1.29 - 8.1.12.31 and 8.1.12.2.3
* and the DTS.
diff --git a/sys/arm/ti/omap4/files.omap4 b/sys/arm/ti/omap4/files.omap4
deleted file mode 100644
--- a/sys/arm/ti/omap4/files.omap4
+++ /dev/null
@@ -1,21 +0,0 @@
-
-arm/ti/ti_smc.S standard
-
-arm/ti/usb/omap_ehci.c optional usb ehci
-arm/ti/usb/omap_host.c optional usb
-arm/ti/usb/omap_tll.c optional usb
-arm/ti/ti_sdma.c optional ti_sdma
-
-arm/ti/omap4/omap4_gpio.c optional gpio
-arm/ti/omap4/omap4_l2cache.c optional pl310
-#arm/ti/omap4/omap4_prcm_clks.c standard
-arm/ti/omap4/omap4_scm_padconf.c standard
-arm/ti/omap4/omap4_mp.c optional smp
-arm/ti/omap4/omap4_wugen.c standard
-
-arm/ti/omap4/pandaboard/pandaboard.c standard
-
-arm/ti/twl/twl.c optional twl
-arm/ti/twl/twl_vreg.c optional twl twl_vreg
-arm/ti/twl/twl_clks.c optional twl twl_clks
-
diff --git a/sys/arm/ti/omap4/omap4_gpio.c b/sys/arm/ti/omap4/omap4_gpio.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_gpio.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*-
- * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
- * Copyright (c) 2014 Andrew Turner <andrew@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/gpio.h>
-
-#include <machine/bus.h>
-#include <machine/intr.h>
-
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <arm/ti/ti_cpuid.h>
-#include <arm/ti/ti_gpio.h>
-#include <arm/ti/ti_pinmux.h>
-
-#include <arm/ti/omap4/omap4_scm_padconf.h>
-
-#include "ti_gpio_if.h"
-
-static struct ofw_compat_data compat_data[] = {
- {"ti,omap4-gpio", 1},
- {"ti,gpio", 1},
- {NULL, 0},
-};
-
-static int
-omap4_gpio_probe(device_t dev)
-{
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
- return (ENXIO);
- if (ti_chip() != CHIP_OMAP_4)
- return (ENXIO);
-
- device_set_desc(dev, "TI OMAP4 General Purpose I/O (GPIO)");
-
- return (0);
-}
-
-static int
-omap4_gpio_set_flags(device_t dev, uint32_t gpio, uint32_t flags)
-{
- unsigned int state = 0;
- struct ti_gpio_softc *sc;
-
- sc = device_get_softc(dev);
- /* First the SCM driver needs to be told to put the pad into GPIO mode */
- if (flags & GPIO_PIN_OUTPUT)
- state = PADCONF_PIN_OUTPUT;
- else if (flags & GPIO_PIN_INPUT) {
- if (flags & GPIO_PIN_PULLUP)
- state = PADCONF_PIN_INPUT_PULLUP;
- else if (flags & GPIO_PIN_PULLDOWN)
- state = PADCONF_PIN_INPUT_PULLDOWN;
- else
- state = PADCONF_PIN_INPUT;
- }
- return ti_pinmux_padconf_set_gpiomode((sc->sc_bank-1)*32 + gpio, state);
-}
-
-static int
-omap4_gpio_get_flags(device_t dev, uint32_t gpio, uint32_t *flags)
-{
- unsigned int state;
- struct ti_gpio_softc *sc;
-
- sc = device_get_softc(dev);
-
- /* Get the current pin state */
- if (ti_pinmux_padconf_get_gpiomode((sc->sc_bank-1)*32 + gpio, &state) != 0) {
- *flags = 0;
- return (EINVAL);
- } else {
- switch (state) {
- case PADCONF_PIN_OUTPUT:
- *flags = GPIO_PIN_OUTPUT;
- break;
- case PADCONF_PIN_INPUT:
- *flags = GPIO_PIN_INPUT;
- break;
- case PADCONF_PIN_INPUT_PULLUP:
- *flags = GPIO_PIN_INPUT | GPIO_PIN_PULLUP;
- break;
- case PADCONF_PIN_INPUT_PULLDOWN:
- *flags = GPIO_PIN_INPUT | GPIO_PIN_PULLDOWN;
- break;
- default:
- *flags = 0;
- break;
- }
- }
-
- return (0);
-}
-
-static device_method_t omap4_gpio_methods[] = {
- /* bus interface */
- DEVMETHOD(device_probe, omap4_gpio_probe),
-
- /* ti_gpio interface */
- DEVMETHOD(ti_gpio_set_flags, omap4_gpio_set_flags),
- DEVMETHOD(ti_gpio_get_flags, omap4_gpio_get_flags),
-
- DEVMETHOD_END
-};
-
-extern driver_t ti_gpio_driver;
-
-DEFINE_CLASS_1(gpio, omap4_gpio_driver, omap4_gpio_methods,
- sizeof(struct ti_gpio_softc), ti_gpio_driver);
-DRIVER_MODULE(omap4_gpio, simplebus, omap4_gpio_driver, 0, 0);
diff --git a/sys/arm/ti/omap4/omap4_l2cache.c b/sys/arm/ti/omap4/omap4_l2cache.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_l2cache.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012 Olivier Houchard. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#include <sys/types.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/rman.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-
-#include <machine/bus.h>
-#include <machine/pl310.h>
-#include <machine/platformvar.h>
-
-#include <arm/ti/ti_smc.h>
-#include <arm/ti/omap4/omap4_machdep.h>
-#include <arm/ti/omap4/omap4_smc.h>
-
-#include "platform_pl310_if.h"
-
-void
-omap4_pl310_init(platform_t plat, struct pl310_softc *sc)
-{
- uint32_t aux, prefetch;
-
- aux = pl310_read4(sc, PL310_AUX_CTRL);
- prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL);
-
- /*
- * Disable instruction prefetch
- */
- prefetch &= ~PREFETCH_CTRL_INSTR_PREFETCH;
- aux &= ~AUX_CTRL_INSTR_PREFETCH;
-
- // prefetch &= ~PREFETCH_CTRL_DATA_PREFETCH;
- // aux &= ~AUX_CTRL_DATA_PREFETCH;
-
- /*
- * Make sure data prefetch is on
- */
- prefetch |= PREFETCH_CTRL_DATA_PREFETCH;
- aux |= AUX_CTRL_DATA_PREFETCH;
-
- /*
- * TODO: add tunable for prefetch offset
- * and experiment with performance
- */
-
- ti_smc0(aux, 0, WRITE_AUXCTRL_REG);
- ti_smc0(prefetch, 0, WRITE_PREFETCH_CTRL_REG);
-}
-
-void
-omap4_pl310_write_ctrl(platform_t plat, struct pl310_softc *sc, uint32_t val)
-{
-
- ti_smc0(val, 0, L2CACHE_WRITE_CTRL_REG);
-}
-
-void
-omap4_pl310_write_debug(platform_t plat, struct pl310_softc *sc, uint32_t val)
-{
-
- ti_smc0(val, 0, L2CACHE_WRITE_DEBUG_REG);
-}
diff --git a/sys/arm/ti/omap4/omap4_machdep.h b/sys/arm/ti/omap4/omap4_machdep.h
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_machdep.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*-
- * Copyright (c) 2016 Olivier Houchard <cognet@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _OMAP4_MACHDEP_H_
-#define _OMAP4_MACHDEP_H_
-
-struct pl310_softc;
-
-void omap4_mp_setmaxid(platform_t plat);
-void omap4_mp_start_ap(platform_t plat);
-
-void omap4_pl310_init(platform_t, struct pl310_softc *);
-void omap4_pl310_write_ctrl(platform_t, struct pl310_softc *, uint32_t);
-void omap4_pl310_write_debug(platform_t, struct pl310_softc *, uint32_t);
-
-#endif /* _OMAP4_MACHDEP_H_ */
diff --git a/sys/arm/ti/omap4/omap4_mp.c b/sys/arm/ti/omap4/omap4_mp.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_mp.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012 Olivier Houchard. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/smp.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-
-#include <machine/cpu.h>
-#include <machine/smp.h>
-#include <machine/fdt.h>
-#include <machine/intr.h>
-#include <machine/platformvar.h>
-
-#include <arm/ti/ti_smc.h>
-#include <arm/ti/omap4/omap4_machdep.h>
-#include <arm/ti/omap4/omap4_smc.h>
-
-void
-omap4_mp_setmaxid(platform_t plat)
-{
-
- if (mp_ncpus != 0)
- return;
- mp_maxid = 1;
- mp_ncpus = 2;
-}
-
-void
-omap4_mp_start_ap(platform_t plat)
-{
- bus_addr_t scu_addr;
-
- if (bus_space_map(fdtbus_bs_tag, 0x48240000, 0x1000, 0, &scu_addr) != 0)
- panic("Couldn't map the SCU\n");
- /* Enable the SCU */
- *(volatile unsigned int *)scu_addr |= 1;
- //*(volatile unsigned int *)(scu_addr + 0x30) |= 1;
- dcache_wbinv_poc_all();
-
- ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0);
- ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1);
- dsb();
- sev();
- bus_space_unmap(fdtbus_bs_tag, scu_addr, 0x1000);
-}
diff --git a/sys/arm/ti/omap4/omap4_prcm_clks.c b/sys/arm/ti/omap4/omap4_prcm_clks.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_prcm_clks.c
+++ /dev/null
@@ -1,1500 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <machine/intr.h>
-
-#include <arm/arm/mpcore_timervar.h>
-#include <arm/ti/tivar.h>
-#include <arm/ti/ti_prcm.h>
-#include <arm/ti/omap4/omap4_reg.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-/*
- * This file defines the clock configuration for the OMAP4xxx series of
- * devices.
- *
- * How This is Suppose to Work
- * ===========================
- * - There is a top level omap_prcm module that defines all OMAP SoC drivers
- * should use to enable/disable the system clocks regardless of the version
- * of OMAP device they are running on. This top level PRCM module is just
- * a thin shim to chip specific functions that perform the donkey work of
- * configuring the clock - this file is the 'donkey' for OMAP44xx devices.
- *
- * - The key bit in this file is the omap_clk_devmap array, it's
- * used by the omap_prcm driver to determine what clocks are valid and which
- * functions to call to manipulate them.
- *
- * - In essence you just need to define some callbacks for each of the
- * clocks and then you're done.
- *
- * - The other thing that is worth noting is that when the omap_prcm device
- * is registered you typically pass in some memory ranges which are the
- * SYS_MEMORY resources. These resources are in turn allocated using
- * bus_allocate_resources(...) and the resource handles are passed to all
- * individual clock callback handlers.
- *
- *
- *
- * OMAP4 devices are different from the previous OMAP3 devices in that there
- * is no longer a separate functional and interface clock for each module,
- * instead there is typically an interface clock that spans many modules.
- */
-
-#define FREQ_96MHZ 96000000
-#define FREQ_64MHZ 64000000
-#define FREQ_48MHZ 48000000
-#define FREQ_32KHZ 32000
-
-#define PRM_INSTANCE 1
-#define CM1_INSTANCE 2
-#define CM2_INSTANCE 3
-
-/**
- * Address offsets from the PRM memory region to the top level clock control
- * registers.
- */
-#define CKGEN_PRM_OFFSET 0x00000100UL
-#define MPU_PRM_OFFSET 0x00000300UL
-#define DSP_PRM_OFFSET 0x00000400UL
-#define ABE_PRM_OFFSET 0x00000500UL
-#define ALWAYS_ON_PRM_OFFSET 0x00000600UL
-#define CORE_PRM_OFFSET 0x00000700UL
-#define IVAHD_PRM_OFFSET 0x00000F00UL
-#define CAM_PRM_OFFSET 0x00001000UL
-#define DSS_PRM_OFFSET 0x00001100UL
-#define SGX_PRM_OFFSET 0x00001200UL
-#define L3INIT_PRM_OFFSET 0x00001300UL
-#define L4PER_PRM_OFFSET 0x00001400UL
-#define WKUP_PRM_OFFSET 0x00001700UL
-#define WKUP_CM_OFFSET 0x00001800UL
-#define EMU_PRM_OFFSET 0x00001900UL
-#define EMU_CM_OFFSET 0x00001A00UL
-#define DEVICE_PRM_OFFSET 0x00001B00UL
-#define INSTR_PRM_OFFSET 0x00001F00UL
-
-#define CM_ABE_DSS_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0000UL)
-#define CM_L4_WKUP_CLKSELL_OFFSET (CKGEN_PRM_OFFSET + 0x0008UL)
-#define CM_ABE_PLL_REF_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x000CUL)
-#define CM_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0010UL)
-
-/**
- * Address offsets from the CM1 memory region to the top level clock control
- * registers.
- */
-#define CKGEN_CM1_OFFSET 0x00000100UL
-#define MPU_CM1_OFFSET 0x00000300UL
-#define DSP_CM1_OFFSET 0x00000400UL
-#define ABE_CM1_OFFSET 0x00000500UL
-#define RESTORE_CM1_OFFSET 0x00000E00UL
-#define INSTR_CM1_OFFSET 0x00000F00UL
-
-#define CM_CLKSEL_DPLL_MPU (CKGEN_CM1_OFFSET + 0x006CUL)
-
-/**
- * Address offsets from the CM2 memory region to the top level clock control
- * registers.
- */
-#define INTRCONN_SOCKET_CM2_OFFSET 0x00000000UL
-#define CKGEN_CM2_OFFSET 0x00000100UL
-#define ALWAYS_ON_CM2_OFFSET 0x00000600UL
-#define CORE_CM2_OFFSET 0x00000700UL
-#define IVAHD_CM2_OFFSET 0x00000F00UL
-#define CAM_CM2_OFFSET 0x00001000UL
-#define DSS_CM2_OFFSET 0x00001100UL
-#define SGX_CM2_OFFSET 0x00001200UL
-#define L3INIT_CM2_OFFSET 0x00001300UL
-#define L4PER_CM2_OFFSET 0x00001400UL
-#define RESTORE_CM2_OFFSET 0x00001E00UL
-#define INSTR_CM2_OFFSET 0x00001F00UL
-
-#define CLKCTRL_MODULEMODE_MASK 0x00000003UL
-#define CLKCTRL_MODULEMODE_DISABLE 0x00000000UL
-#define CLKCTRL_MODULEMODE_AUTO 0x00000001UL
-#define CLKCTRL_MODULEMODE_ENABLE 0x00000001UL
-
-#define CLKCTRL_IDLEST_MASK 0x00030000UL
-#define CLKCTRL_IDLEST_ENABLED 0x00000000UL
-#define CLKCTRL_IDLEST_WAKING 0x00010000UL
-#define CLKCTRL_IDLEST_IDLE 0x00020000UL
-#define CLKCTRL_IDLEST_DISABLED 0x00030000UL
-
-static struct ofw_compat_data compat_data[] = {
- {"ti,omap4-cm1", (uintptr_t)CM1_INSTANCE},
- {"ti,omap4-cm2", (uintptr_t)CM2_INSTANCE},
- {"ti,omap4-prm", (uintptr_t)PRM_INSTANCE},
- {NULL, (uintptr_t)0},
-};
-
-struct omap4_prcm_softc {
- struct resource *sc_res;
- int sc_rid;
- int sc_instance;
- int attach_done;
-};
-
-static int omap4_clk_generic_activate(struct ti_clock_dev *clkdev);
-static int omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev);
-static int omap4_clk_generic_accessible(struct ti_clock_dev *clkdev);
-static int omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
-static int omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
-
-static int omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
-static int omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
-
-static int omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
-static int omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
-
-static int omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc);
-static int omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev);
-static int omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev);
-static int omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev);
-
-static int omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
-static int omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq);
-
-/**
- * omap_clk_devmap - Array of clock devices available on OMAP4xxx devices
- *
- * This map only defines which clocks are valid and the callback functions
- * for clock activate, deactivate, etc. It is used by the top level omap_prcm
- * driver.
- *
- * The actual details of the clocks (config registers, bit fields, sources,
- * etc) are in the private g_omap3_clk_details array below.
- *
- */
-
-#define OMAP4_GENERIC_CLOCK_DEV(i) \
- { .id = (i), \
- .clk_activate = omap4_clk_generic_activate, \
- .clk_deactivate = omap4_clk_generic_deactivate, \
- .clk_set_source = omap4_clk_generic_set_source, \
- .clk_accessible = omap4_clk_generic_accessible, \
- .clk_get_source_freq = omap4_clk_generic_get_source_freq, \
- .clk_set_source_freq = NULL \
- }
-
-#define OMAP4_GPTIMER_CLOCK_DEV(i) \
- { .id = (i), \
- .clk_activate = omap4_clk_generic_activate, \
- .clk_deactivate = omap4_clk_generic_deactivate, \
- .clk_set_source = omap4_clk_gptimer_set_source, \
- .clk_accessible = omap4_clk_generic_accessible, \
- .clk_get_source_freq = omap4_clk_gptimer_get_source_freq, \
- .clk_set_source_freq = NULL \
- }
-
-#define OMAP4_HSMMC_CLOCK_DEV(i) \
- { .id = (i), \
- .clk_activate = omap4_clk_generic_activate, \
- .clk_deactivate = omap4_clk_generic_deactivate, \
- .clk_set_source = omap4_clk_hsmmc_set_source, \
- .clk_accessible = omap4_clk_generic_accessible, \
- .clk_get_source_freq = omap4_clk_hsmmc_get_source_freq, \
- .clk_set_source_freq = NULL \
- }
-
-#define OMAP4_HSUSBHOST_CLOCK_DEV(i) \
- { .id = (i), \
- .clk_activate = omap4_clk_hsusbhost_activate, \
- .clk_deactivate = omap4_clk_hsusbhost_deactivate, \
- .clk_set_source = omap4_clk_hsusbhost_set_source, \
- .clk_accessible = omap4_clk_hsusbhost_accessible, \
- .clk_get_source_freq = NULL, \
- .clk_set_source_freq = NULL \
- }
-
-struct ti_clock_dev ti_omap4_clk_devmap[] = {
- /* System clocks */
- { .id = SYS_CLK,
- .clk_activate = NULL,
- .clk_deactivate = NULL,
- .clk_set_source = NULL,
- .clk_accessible = NULL,
- .clk_get_source_freq = omap4_clk_get_sysclk_freq,
- .clk_set_source_freq = NULL,
- },
- /* MPU (ARM) core clocks */
- { .id = MPU_CLK,
- .clk_activate = NULL,
- .clk_deactivate = NULL,
- .clk_set_source = NULL,
- .clk_accessible = NULL,
- .clk_get_source_freq = omap4_clk_get_arm_fclk_freq,
- .clk_set_source_freq = NULL,
- },
-
- /* UART device clocks */
- OMAP4_GENERIC_CLOCK_DEV(UART1_CLK),
- OMAP4_GENERIC_CLOCK_DEV(UART2_CLK),
- OMAP4_GENERIC_CLOCK_DEV(UART3_CLK),
- OMAP4_GENERIC_CLOCK_DEV(UART4_CLK),
-
- /* Timer device source clocks */
- OMAP4_GPTIMER_CLOCK_DEV(TIMER1_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER2_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER3_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER4_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER5_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER6_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER7_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER8_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER9_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER10_CLK),
- OMAP4_GPTIMER_CLOCK_DEV(TIMER11_CLK),
-
- /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */
- OMAP4_HSMMC_CLOCK_DEV(MMC1_CLK),
- OMAP4_HSMMC_CLOCK_DEV(MMC2_CLK),
- OMAP4_GENERIC_CLOCK_DEV(MMC3_CLK),
- OMAP4_GENERIC_CLOCK_DEV(MMC4_CLK),
- OMAP4_GENERIC_CLOCK_DEV(MMC5_CLK),
-
- /* USB HS (high speed TLL, EHCI and OHCI) */
- OMAP4_HSUSBHOST_CLOCK_DEV(USBTLL_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBFSHOST_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_PHY_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_PHY_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_UTMI_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_UTMI_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_HSIC_CLK),
- OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_HSIC_CLK),
-
- /* GPIO */
- OMAP4_GENERIC_CLOCK_DEV(GPIO1_CLK),
- OMAP4_GENERIC_CLOCK_DEV(GPIO2_CLK),
- OMAP4_GENERIC_CLOCK_DEV(GPIO3_CLK),
- OMAP4_GENERIC_CLOCK_DEV(GPIO4_CLK),
- OMAP4_GENERIC_CLOCK_DEV(GPIO5_CLK),
- OMAP4_GENERIC_CLOCK_DEV(GPIO6_CLK),
-
- /* sDMA */
- OMAP4_GENERIC_CLOCK_DEV(SDMA_CLK),
-
- /* I2C */
- OMAP4_GENERIC_CLOCK_DEV(I2C1_CLK),
- OMAP4_GENERIC_CLOCK_DEV(I2C2_CLK),
- OMAP4_GENERIC_CLOCK_DEV(I2C3_CLK),
- OMAP4_GENERIC_CLOCK_DEV(I2C4_CLK),
- { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL }
-};
-
-/**
- * omap4_clk_details - Stores details for all the different clocks supported
- *
- * Whenever an operation on a clock is being performed (activated, deactivated,
- * etc) this array is looked up to find the correct register and bit(s) we
- * should be modifying.
- *
- */
-struct omap4_clk_details {
- clk_ident_t id;
-
- uint32_t instance;
- uint32_t clksel_reg;
-
- int32_t src_freq;
-
- uint32_t enable_mode;
-};
-
-#define OMAP4_GENERIC_CLOCK_DETAILS(i, f, di, r, e) \
- { .id = (i), \
- .instance = (di), \
- .clksel_reg = (r), \
- .src_freq = (f), \
- .enable_mode = (e), \
- }
-
-static struct omap4_clk_details g_omap4_clk_details[] = {
- /* UART */
- OMAP4_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0150), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(UART4_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0158), CLKCTRL_MODULEMODE_ENABLE),
-
- /* General purpose timers */
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER1_CLK, -1, PRM_INSTANCE,
- (WKUP_CM_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER2_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x038), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER3_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER4_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x048), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER5_CLK, -1, CM1_INSTANCE,
- (ABE_CM1_OFFSET + 0x068), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER6_CLK, -1, CM1_INSTANCE,
- (ABE_CM1_OFFSET + 0x070), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER7_CLK, -1, CM1_INSTANCE,
- (ABE_CM1_OFFSET + 0x078), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER8_CLK, -1, CM1_INSTANCE,
- (ABE_CM1_OFFSET + 0x080), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER9_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x050), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER10_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x028), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(TIMER11_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x030), CLKCTRL_MODULEMODE_ENABLE),
-
- /* HSMMC (MMC1 and MMC2 can have different input clocks) */
- OMAP4_GENERIC_CLOCK_DETAILS(MMC1_CLK, -1, CM2_INSTANCE,
- (L3INIT_CM2_OFFSET + 0x028), /*CLKCTRL_MODULEMODE_ENABLE*/2),
- OMAP4_GENERIC_CLOCK_DETAILS(MMC2_CLK, -1, CM2_INSTANCE,
- (L3INIT_CM2_OFFSET + 0x030), /*CLKCTRL_MODULEMODE_ENABLE*/2),
- OMAP4_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x120), /*CLKCTRL_MODULEMODE_ENABLE*/2),
- OMAP4_GENERIC_CLOCK_DETAILS(MMC4_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x128), /*CLKCTRL_MODULEMODE_ENABLE*/2),
- OMAP4_GENERIC_CLOCK_DETAILS(MMC5_CLK, FREQ_48MHZ, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x160), /*CLKCTRL_MODULEMODE_ENABLE*/1),
-
- /* GPIO modules */
- OMAP4_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, PRM_INSTANCE,
- (WKUP_CM_OFFSET + 0x038), CLKCTRL_MODULEMODE_AUTO),
- OMAP4_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x060), CLKCTRL_MODULEMODE_AUTO),
- OMAP4_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x068), CLKCTRL_MODULEMODE_AUTO),
- OMAP4_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x070), CLKCTRL_MODULEMODE_AUTO),
- OMAP4_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x078), CLKCTRL_MODULEMODE_AUTO),
- OMAP4_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x080), CLKCTRL_MODULEMODE_AUTO),
-
- /* sDMA block */
- OMAP4_GENERIC_CLOCK_DETAILS(SDMA_CLK, -1, CM2_INSTANCE,
- (CORE_CM2_OFFSET + 0x300), CLKCTRL_MODULEMODE_AUTO),
-
- /* I2C modules */
- OMAP4_GENERIC_CLOCK_DETAILS(I2C1_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0A0), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(I2C2_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0A8), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(I2C3_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0B0), CLKCTRL_MODULEMODE_ENABLE),
- OMAP4_GENERIC_CLOCK_DETAILS(I2C4_CLK, -1, CM2_INSTANCE,
- (L4PER_CM2_OFFSET + 0x0B8), CLKCTRL_MODULEMODE_ENABLE),
-
- { INVALID_CLK_IDENT, 0, 0, 0, 0 },
-};
-
-/**
- * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come
- * alive.
- *
- */
-#define MAX_MODULE_ENABLE_WAIT 100
-
-/**
- * ARRAY_SIZE - Macro to return the number of elements in a static const array.
- *
- */
-#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
-
-/**
- * omap4_clk_details - writes a 32-bit value to one of the timer registers
- * @timer: Timer device context
- * @off: The offset of a register from the timer register address range
- * @val: The value to write into the register
- *
- *
- * RETURNS:
- * nothing
- */
-static struct omap4_clk_details*
-omap4_clk_details(clk_ident_t id)
-{
- struct omap4_clk_details *walker;
-
- for (walker = g_omap4_clk_details; walker->id != INVALID_CLK_IDENT; walker++) {
- if (id == walker->id)
- return (walker);
- }
-
- return NULL;
-}
-
-static struct omap4_prcm_softc *
-omap4_prcm_get_instance_softc(int module_instance)
-{
- int i, maxunit;
- devclass_t prcm_devclass;
- device_t dev;
- struct omap4_prcm_softc *sc;
-
- prcm_devclass = devclass_find("omap4_prcm");
- maxunit = devclass_get_maxunit(prcm_devclass);
-
- for (i = 0; i < maxunit; i++) {
- dev = devclass_get_device(prcm_devclass, i);
- sc = device_get_softc(dev);
- if (sc->sc_instance == module_instance)
- return (sc);
- }
-
- return (NULL);
-}
-
-/**
- * omap4_clk_generic_activate - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a positive error code on failure.
- */
-static int
-omap4_clk_generic_activate(struct ti_clock_dev *clkdev)
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
- uint32_t clksel;
- unsigned int i;
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- /* All the 'generic' clocks have a CLKCTRL register which is more or less
- * generic - the have at least two fielda called MODULEMODE and IDLEST.
- */
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
- clksel &= ~CLKCTRL_MODULEMODE_MASK;
- clksel |= clk_details->enable_mode;
- bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel);
-
- /* Now poll on the IDLEST register to tell us if the module has come up.
- * TODO: We need to take into account the parent clocks.
- */
-
- /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */
- for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) {
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
- if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED)
- break;
- DELAY(10);
- }
-
- /* Check the enabled state */
- if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) {
- printf("Error: failed to enable module with clock %d\n", clkdev->id);
- printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel);
- return (ETIMEDOUT);
- }
-
- return (0);
-}
-
-/**
- * omap4_clk_generic_deactivate - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a positive error code on failure.
- */
-static int
-omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev)
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
- uint32_t clksel;
-
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- /* All the 'generic' clocks have a CLKCTRL register which is more or less
- * generic - the have at least two fielda called MODULEMODE and IDLEST.
- */
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
- clksel &= ~CLKCTRL_MODULEMODE_MASK;
- clksel |= CLKCTRL_MODULEMODE_DISABLE;
- bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel);
-
- return (0);
-}
-
-/**
- * omap4_clk_generic_set_source - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a positive error code on failure.
- */
-static int
-omap4_clk_generic_set_source(struct ti_clock_dev *clkdev,
- clk_src_t clksrc)
-{
-
- return (0);
-}
-
-/**
- * omap4_clk_generic_accessible - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a negative error code on failure.
- */
-static int
-omap4_clk_generic_accessible(struct ti_clock_dev *clkdev)
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
- uint32_t clksel;
-
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
-
- /* Check the enabled state */
- if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED)
- return (0);
-
- return (1);
-}
-
-/**
- * omap4_clk_generic_get_source_freq - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a negative error code on failure.
- */
-static int
-omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev,
- unsigned int *freq
- )
-{
- struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- /* Simply return the stored frequency */
- if (freq)
- *freq = (unsigned int)clk_details->src_freq;
-
- return (0);
-}
-
-/**
- * omap4_clk_gptimer_set_source - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a negative error code on failure.
- */
-static int
-omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev,
- clk_src_t clksrc)
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
-
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- /* TODO: Implement */
-
- return (0);
-}
-
-/**
- * omap4_clk_gptimer_get_source_freq - checks if a module is accessible
- * @module: identifier for the module to check, see omap3_prcm.h for a list
- * of possible modules.
- * Example: OMAP3_MODULE_MMC1
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a negative error code on failure.
- */
-static int
-omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev,
- unsigned int *freq
- )
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
- uint32_t clksel;
- unsigned int src_freq;
-
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- /* Need to read the CLKSEL field to determine the clock source */
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
- if (clksel & (0x1UL << 24))
- src_freq = FREQ_32KHZ;
- else
- omap4_clk_get_sysclk_freq(NULL, &src_freq);
-
- /* Return the frequency */
- if (freq)
- *freq = src_freq;
-
- return (0);
-}
-
-/**
- * omap4_clk_hsmmc_set_source - sets the source clock (freq)
- * @clkdev: pointer to the clockdev structure (id field will contain clock id)
- *
- * The MMC 1 and 2 clocks can be source from either a 64MHz or 96MHz clock.
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a negative error code on failure.
- */
-static int
-omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev,
- clk_src_t clksrc)
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
- uint32_t clksel;
-
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- /* For MMC modules 3, 4 & 5 you can't change the freq, it's always 48MHz */
- if ((clkdev->id == MMC3_CLK) || (clkdev->id == MMC4_CLK) ||
- (clkdev->id == MMC5_CLK)) {
- if (clksrc != F48MHZ_CLK)
- return (EINVAL);
- return 0;
- }
-
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
-
- /* Bit 24 is set if 96MHz clock or cleared for 64MHz clock */
- if (clksrc == F64MHZ_CLK)
- clksel &= ~(0x1UL << 24);
- else if (clksrc == F96MHZ_CLK)
- clksel |= (0x1UL << 24);
- else
- return (EINVAL);
-
- bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel);
-
- return (0);
-}
-
-/**
- * omap4_clk_hsmmc_get_source_freq - checks if a module is accessible
- * @clkdev: pointer to the clockdev structure (id field will contain clock id)
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a negative error code on failure.
- */
-static int
-omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev,
- unsigned int *freq
- )
-{
- struct omap4_prcm_softc *sc;
- struct omap4_clk_details* clk_details;
- struct resource* clk_mem_res;
- uint32_t clksel;
- unsigned int src_freq;
-
- clk_details = omap4_clk_details(clkdev->id);
-
- if (clk_details == NULL)
- return (ENXIO);
-
- sc = omap4_prcm_get_instance_softc(clk_details->instance);
- if (sc == NULL)
- return ENXIO;
-
- clk_mem_res = sc->sc_res;
-
- if (clk_mem_res == NULL)
- return (EINVAL);
-
- switch (clkdev->id) {
- case MMC1_CLK:
- case MMC2_CLK:
- /* Need to read the CLKSEL field to determine the clock source */
- clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
- if (clksel & (0x1UL << 24))
- src_freq = FREQ_96MHZ;
- else
- src_freq = FREQ_64MHZ;
- break;
- case MMC3_CLK:
- case MMC4_CLK:
- case MMC5_CLK:
- src_freq = FREQ_48MHZ;
- break;
- default:
- return (EINVAL);
- }
-
- /* Return the frequency */
- if (freq)
- *freq = src_freq;
-
- return (0);
-}
-
-/**
- * omap4_clk_get_sysclk_freq - gets the sysclk frequency
- * @sc: pointer to the clk module/device context
- *
- * Read the clocking information from the power-control/boot-strap registers,
- * and stored in two global variables.
- *
- * RETURNS:
- * nothing, values are saved in global variables
- */
-static int
-omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev,
- unsigned int *freq)
-{
- uint32_t clksel;
- uint32_t sysclk;
- struct omap4_prcm_softc *sc;
-
- sc = omap4_prcm_get_instance_softc(PRM_INSTANCE);
- if (sc == NULL)
- return ENXIO;
-
- /* Read the input clock freq from the configuration register (CM_SYS_CLKSEL) */
- clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET);
- switch (clksel & 0x7) {
- case 0x1:
- /* 12Mhz */
- sysclk = 12000000;
- break;
- case 0x3:
- /* 16.8Mhz */
- sysclk = 16800000;
- break;
- case 0x4:
- /* 19.2Mhz */
- sysclk = 19200000;
- break;
- case 0x5:
- /* 26Mhz */
- sysclk = 26000000;
- break;
- case 0x7:
- /* 38.4Mhz */
- sysclk = 38400000;
- break;
- default:
- panic("%s: Invalid clock freq", __func__);
- }
-
- /* Return the value */
- if (freq)
- *freq = sysclk;
-
- return (0);
-}
-
-/**
- * omap4_clk_get_arm_fclk_freq - gets the MPU clock frequency
- * @clkdev: ignored
- * @freq: pointer which upon return will contain the freq in hz
- * @mem_res: array of allocated memory resources
- *
- * Reads the frequency setting information registers and returns the value
- * in the freq variable.
- *
- * RETURNS:
- * returns 0 on success, a positive error code on failure.
- */
-static int
-omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev,
- unsigned int *freq)
-{
- uint32_t clksel;
- uint32_t pll_mult, pll_div;
- uint32_t mpuclk, sysclk;
- struct omap4_prcm_softc *sc;
-
- sc = omap4_prcm_get_instance_softc(CM1_INSTANCE);
- if (sc == NULL)
- return ENXIO;
-
- /* Read the clksel register which contains the DPLL multiple and divide
- * values. These are applied to the sysclk.
- */
- clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU);
-
- pll_mult = ((clksel >> 8) & 0x7ff);
- pll_div = (clksel & 0x7f) + 1;
-
- /* Get the system clock freq */
- omap4_clk_get_sysclk_freq(NULL, &sysclk);
-
- /* Calculate the MPU freq */
- mpuclk = ((uint64_t)sysclk * pll_mult) / pll_div;
-
- /* Return the value */
- if (freq)
- *freq = mpuclk;
-
- return (0);
-}
-
-/**
- * omap4_clk_hsusbhost_activate - activates the USB clocks for the given module
- * @clkdev: pointer to the clock device structure.
- * @mem_res: array of memory resources allocated by the top level PRCM driver.
- *
- * The USB clocking setup seems to be a bit more tricky than the other modules,
- * to start with the clocking diagram for the HS host module shows 13 different
- * clocks. So to try and make it easier to follow the clocking activation
- * and deactivation is handled in its own set of callbacks.
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a positive error code on failure.
- */
-
-struct dpll_param {
- unsigned int m;
- unsigned int n;
- unsigned int m2;
- unsigned int m3;
- unsigned int m4;
- unsigned int m5;
- unsigned int m6;
- unsigned int m7;
-};
-/* USB parameters */
-struct dpll_param usb_dpll_param[7] = {
- /* 12M values */
- {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
- /* 13M values */
- {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
- /* 16.8M values */
- {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
- /* 19.2M values */
- {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
- /* 26M values */
- {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
- /* 27M values */
- {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
- /* 38.4M values */
-#ifdef CONFIG_OMAP4_SDC
- {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
-#else
- {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
-#endif
-};
-static int
-omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev)
-{
- struct omap4_prcm_softc *sc;
- struct resource* clk_mem_res;
- uint32_t clksel_reg_off;
- uint32_t clksel;
- unsigned int i;
-
- sc = omap4_prcm_get_instance_softc(CM2_INSTANCE);
- if (sc == NULL)
- return ENXIO;
-
- switch (clkdev->id) {
- case USBTLL_CLK:
- /* For the USBTLL module we need to enable the following clocks:
- * - INIT_L4_ICLK (will be enabled by bootloader)
- * - TLL_CH0_FCLK
- * - TLL_CH1_FCLK
- */
-
- /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x68;
-
- /* Enable the module and also enable the optional func clocks for
- * channels 0 & 1 (is this needed ?)
- */
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
- clksel &= ~CLKCTRL_MODULEMODE_MASK;
- clksel |= CLKCTRL_MODULEMODE_ENABLE;
-
- clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */
- clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */
- break;
-
- case USBHSHOST_CLK:
- case USBP1_PHY_CLK:
- case USBP2_PHY_CLK:
- case USBP1_UTMI_CLK:
- case USBP2_UTMI_CLK:
- case USBP1_HSIC_CLK:
- case USBP2_HSIC_CLK:
- /* For the USB HS HOST module we need to enable the following clocks:
- * - INIT_L4_ICLK (will be enabled by bootloader)
- * - INIT_L3_ICLK (will be enabled by bootloader)
- * - INIT_48MC_FCLK
- * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?)
- * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?)
- * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?)
- * - HSIC_P1_60 (HSIC only, create a new clock for that ?)
- * - HSIC_P1_480 (HSIC only, create a new clock for that ?)
- * - HSIC_P2_60 (HSIC only, create a new clock for that ?)
- * - HSIC_P2_480 (HSIC only, create a new clock for that ?)
- */
-
- /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x58;
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
- /* Enable the module and also enable the optional func clocks */
- if (clkdev->id == USBHSHOST_CLK) {
- clksel &= ~CLKCTRL_MODULEMODE_MASK;
- clksel |= /*CLKCTRL_MODULEMODE_ENABLE*/2;
-
- clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */
- }
-
- else if (clkdev->id == USBP1_UTMI_CLK)
- clksel |= (0x1 << 8); /* UTMI_P1_CLK */
- else if (clkdev->id == USBP2_UTMI_CLK)
- clksel |= (0x1 << 9); /* UTMI_P2_CLK */
-
- else if (clkdev->id == USBP1_HSIC_CLK)
- clksel |= (0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */
- else if (clkdev->id == USBP2_HSIC_CLK)
- clksel |= (0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */
-
- break;
-
- default:
- return (EINVAL);
- }
-
- bus_write_4(clk_mem_res, clksel_reg_off, clksel);
-
- /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */
- for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) {
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
- if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED)
- break;
- }
-
- /* Check the enabled state */
- if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) {
- printf("Error: HERE failed to enable module with clock %d\n", clkdev->id);
- printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel);
- return (ETIMEDOUT);
- }
-
- return (0);
-}
-
-/**
- * omap4_clk_generic_deactivate - checks if a module is accessible
- * @clkdev: pointer to the clock device structure.
- * @mem_res: array of memory resources allocated by the top level PRCM driver.
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 on success or a positive error code on failure.
- */
-static int
-omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev)
-{
- struct omap4_prcm_softc *sc;
- struct resource* clk_mem_res;
- uint32_t clksel_reg_off;
- uint32_t clksel;
-
- sc = omap4_prcm_get_instance_softc(CM2_INSTANCE);
- if (sc == NULL)
- return ENXIO;
-
- switch (clkdev->id) {
- case USBTLL_CLK:
- /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x68;
-
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
- clksel &= ~CLKCTRL_MODULEMODE_MASK;
- clksel |= CLKCTRL_MODULEMODE_DISABLE;
- break;
-
- case USBHSHOST_CLK:
- case USBP1_PHY_CLK:
- case USBP2_PHY_CLK:
- case USBP1_UTMI_CLK:
- case USBP2_UTMI_CLK:
- case USBP1_HSIC_CLK:
- case USBP2_HSIC_CLK:
- /* For the USB HS HOST module we need to enable the following clocks:
- * - INIT_L4_ICLK (will be enabled by bootloader)
- * - INIT_L3_ICLK (will be enabled by bootloader)
- * - INIT_48MC_FCLK
- * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?)
- * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?)
- * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?)
- * - HSIC_P1_60 (HSIC only, create a new clock for that ?)
- * - HSIC_P1_480 (HSIC only, create a new clock for that ?)
- * - HSIC_P2_60 (HSIC only, create a new clock for that ?)
- * - HSIC_P2_480 (HSIC only, create a new clock for that ?)
- */
-
- /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x58;
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
-
- /* Enable the module and also enable the optional func clocks */
- if (clkdev->id == USBHSHOST_CLK) {
- clksel &= ~CLKCTRL_MODULEMODE_MASK;
- clksel |= CLKCTRL_MODULEMODE_DISABLE;
-
- clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */
- }
-
- else if (clkdev->id == USBP1_UTMI_CLK)
- clksel &= ~(0x1 << 8); /* UTMI_P1_CLK */
- else if (clkdev->id == USBP2_UTMI_CLK)
- clksel &= ~(0x1 << 9); /* UTMI_P2_CLK */
-
- else if (clkdev->id == USBP1_HSIC_CLK)
- clksel &= ~(0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */
- else if (clkdev->id == USBP2_HSIC_CLK)
- clksel &= ~(0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */
-
- break;
-
- default:
- return (EINVAL);
- }
-
- bus_write_4(clk_mem_res, clksel_reg_off, clksel);
-
- return (0);
-}
-
-/**
- * omap4_clk_hsusbhost_accessible - checks if a module is accessible
- * @clkdev: pointer to the clock device structure.
- * @mem_res: array of memory resources allocated by the top level PRCM driver.
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 if module is not enable, 1 if module is enabled or a negative
- * error code on failure.
- */
-static int
-omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev)
-{
- struct omap4_prcm_softc *sc;
- struct resource* clk_mem_res;
- uint32_t clksel_reg_off;
- uint32_t clksel;
-
- sc = omap4_prcm_get_instance_softc(CM2_INSTANCE);
- if (sc == NULL)
- return ENXIO;
-
- if (clkdev->id == USBTLL_CLK) {
- /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x68;
- }
- else if (clkdev->id == USBHSHOST_CLK) {
- /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x58;
- }
- else {
- return (EINVAL);
- }
-
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
-
- /* Check the enabled state */
- if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED)
- return (0);
-
- return (1);
-}
-
-/**
- * omap4_clk_hsusbhost_set_source - sets the source clocks
- * @clkdev: pointer to the clock device structure.
- * @clksrc: the clock source ID for the given clock.
- * @mem_res: array of memory resources allocated by the top level PRCM driver.
- *
- *
- *
- * LOCKING:
- * Inherits the locks from the omap_prcm driver, no internal locking.
- *
- * RETURNS:
- * Returns 0 if successful otherwise a negative error code on failure.
- */
-static int
-omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev,
- clk_src_t clksrc)
-{
- struct omap4_prcm_softc *sc;
- struct resource* clk_mem_res;
- uint32_t clksel_reg_off;
- uint32_t clksel;
- unsigned int bit;
-
- sc = omap4_prcm_get_instance_softc(CM2_INSTANCE);
- if (sc == NULL)
- return ENXIO;
-
- if (clkdev->id == USBP1_PHY_CLK)
- bit = 24;
- else if (clkdev->id != USBP2_PHY_CLK)
- bit = 25;
- else
- return (EINVAL);
-
- /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */
- clk_mem_res = sc->sc_res;
- clksel_reg_off = L3INIT_CM2_OFFSET + 0x58;
- clksel = bus_read_4(clk_mem_res, clksel_reg_off);
-
- /* Set the clock source to either external or internal */
- if (clksrc == EXT_CLK)
- clksel |= (0x1 << bit);
- else
- clksel &= ~(0x1 << bit);
-
- bus_write_4(clk_mem_res, clksel_reg_off, clksel);
-
- return (0);
-}
-
-#define PRM_RSTCTRL 0x1b00
-#define PRM_RSTCTRL_RESET 0x2
-
-static void
-omap4_prcm_reset(void)
-{
- struct omap4_prcm_softc *sc;
-
- sc = omap4_prcm_get_instance_softc(PRM_INSTANCE);
- if (sc == NULL)
- return;
-
- bus_write_4(sc->sc_res, PRM_RSTCTRL,
- bus_read_4(sc->sc_res, PRM_RSTCTRL) | PRM_RSTCTRL_RESET);
- bus_read_4(sc->sc_res, PRM_RSTCTRL);
-}
-
-/**
- * omap4_prcm_probe - probe function for the driver
- * @dev: prcm device handle
- *
- * Simply sets the name of the driver module.
- *
- * LOCKING:
- * None
- *
- * RETURNS:
- * Always returns 0
- */
-static int
-omap4_prcm_probe(device_t dev)
-{
- const struct ofw_compat_data *ocd;
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- ocd = ofw_bus_search_compatible(dev, compat_data);
- if ((int)ocd->ocd_data == 0)
- return (ENXIO);
-
- switch ((int)ocd->ocd_data) {
- case PRM_INSTANCE:
- device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (PRM)");
- break;
- case CM1_INSTANCE:
- device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C1)");
- break;
- case CM2_INSTANCE:
- device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C2)");
- break;
- default:
- device_printf(dev, "unknown instance type: %d\n", (int)ocd->ocd_data);
- return (ENXIO);
- }
-
- return (BUS_PROBE_DEFAULT);
-}
-
-/**
- * omap_prcm_attach - attach function for the driver
- * @dev: prcm device handle
- *
- * Allocates and sets up the driver context, this simply entails creating a
- * bus mappings for the PRCM register set.
- *
- * LOCKING:
- * None
- *
- * RETURNS:
- * Always returns 0
- */
-
-extern uint32_t platform_arm_tmr_freq;
-
-static int
-omap4_prcm_attach(device_t dev)
-{
- struct omap4_prcm_softc *sc;
- const struct ofw_compat_data *ocd;
-
- sc = device_get_softc(dev);
- ocd = ofw_bus_search_compatible(dev, compat_data);
- sc->sc_instance = (int)ocd->ocd_data;
-
- sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
- RF_ACTIVE);
- if (sc->sc_res == NULL) {
- device_printf(dev, "could not allocate resources\n");
- return (ENXIO);
- }
-
- ti_cpu_reset = omap4_prcm_reset;
-
- return (0);
-}
-
-static void
-omap4_prcm_new_pass(device_t dev)
-{
- struct omap4_prcm_softc *sc = device_get_softc(dev);
- unsigned int freq;
-
- if (sc->attach_done ||
- bus_current_pass < (BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY)) {
- bus_generic_new_pass(dev);
- return;
- }
- sc->attach_done = 1;
-
- /*
- * In order to determine ARM frequency we need both RPM and CM1
- * instances up and running. So wait until all CRM devices are
- * initialized. Should be replaced with proper clock framework
- */
- if (device_get_unit(dev) == 2) {
- omap4_clk_get_arm_fclk_freq(NULL, &freq);
- arm_tmr_change_frequency(freq / 2);
- }
-
- return;
-}
-
-static device_method_t omap4_prcm_methods[] = {
- DEVMETHOD(device_probe, omap4_prcm_probe),
- DEVMETHOD(device_attach, omap4_prcm_attach),
-
- /* Bus interface */
- DEVMETHOD(bus_new_pass, omap4_prcm_new_pass),
-
- {0, 0},
-};
-
-static driver_t omap4_prcm_driver = {
- "omap4_prcm",
- omap4_prcm_methods,
- sizeof(struct omap4_prcm_softc),
-};
-
-EARLY_DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver, 0, 0,
- BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
-MODULE_VERSION(omap4_prcm, 1);
diff --git a/sys/arm/ti/omap4/omap4_reg.h b/sys/arm/ti/omap4/omap4_reg.h
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_reg.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Texas Instruments - OMAP44xx series processors
- *
- * Reference:
- * OMAP44xx Applications Processor
- * Technical Reference Manual
- * (omap44xx_techref.pdf)
- *
- *
- * Note:
- * The devices are mapped into address above 0xD000_0000 as the kernel space
- * memory is at 0xC000_0000 and above. The first 256MB after this is reserved
- * for the size of the kernel, everything above that is reserved for SoC
- * devices.
- *
- */
-#ifndef _OMAP44XX_REG_H_
-#define _OMAP44XX_REG_H_
-
-#ifndef _LOCORE
-#include <sys/types.h> /* for uint32_t */
-#endif
-
-/* Physical/Virtual address for SDRAM controller */
-
-#define OMAP44XX_SMS_VBASE 0x6C000000UL
-#define OMAP44XX_SMS_HWBASE 0x6C000000UL
-#define OMAP44XX_SMS_SIZE 0x01000000UL
-
-#define OMAP44XX_SDRC_VBASE 0x6D000000UL
-#define OMAP44XX_SDRC_HWBASE 0x6D000000UL
-#define OMAP44XX_SDRC_SIZE 0x01000000UL
-
-/* Physical/Virtual address for I/O space */
-
-#define OMAP44XX_L3_EMU_VBASE 0xD4000000UL
-#define OMAP44XX_L3_EMU_HWBASE 0x54000000UL
-#define OMAP44XX_L3_EMU_SIZE 0x00200000UL
-
-#define OMAP44XX_L3_EMIF1_VBASE 0xEC000000UL
-#define OMAP44XX_L3_EMIF1_HWBASE 0x4C000000UL
-#define OMAP44XX_L3_EMIF1_SIZE 0x01000000UL
-
-#define OMAP44XX_L3_EMIF2_VBASE 0xED000000UL
-#define OMAP44XX_L3_EMIF2_HWBASE 0x4D000000UL
-#define OMAP44XX_L3_EMIF2_SIZE 0x01000000UL
-
-#define OMAP44XX_L4_CORE_VBASE 0xEA000000UL
-#define OMAP44XX_L4_CORE_HWBASE 0x4A000000UL
-#define OMAP44XX_L4_CORE_SIZE 0x01000000UL
-
-#define OMAP44XX_L4_WAKEUP_VBASE 0xEA300000UL
-#define OMAP44XX_L4_WAKEUP_HWBASE 0x4A300000UL
-#define OMAP44XX_L4_WAKEUP_SIZE 0x00040000UL
-
-#define OMAP44XX_L4_PERIPH_VBASE 0xE8000000UL
-#define OMAP44XX_L4_PERIPH_HWBASE 0x48000000UL
-#define OMAP44XX_L4_PERIPH_SIZE 0x01000000UL
-
-#define OMAP44XX_L4_ABE_VBASE 0xE9000000UL
-#define OMAP44XX_L4_ABE_HWBASE 0x49000000UL
-#define OMAP44XX_L4_ABE_SIZE 0x00100000UL
-
-/* Physical/Virtual address for MPU Subsystem space */
-
-#define OMAP44XX_MPU_SUBSYS_VBASE (OMAP44XX_L4_PERIPH_VBASE + 0x00240000UL)
-#define OMAP44XX_MPU_SUBSYS_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + 0x00240000UL)
-#define OMAP44XX_MPU_SUBSYS_SIZE 0x00004000UL
-
-/*
- * MPU Subsystem address offsets
- */
-#define OMAP44XX_SCU_OFFSET 0x00000000UL
-#define OMAP44XX_GIC_CPU_OFFSET 0x00000100UL
-#define OMAP44XX_GBL_TIMER_OFFSET 0x00000200UL
-#define OMAP44XX_PRV_TIMER_OFFSET 0x00000600UL
-#define OMAP44XX_GIC_DIST_OFFSET 0x00001000UL
-#define OMAP44XX_PL310_OFFSET 0x00002000UL
-#define OMAP44XX_CORTEXA9_SOCKET_PRCM_OFFSET 0x00003000UL
-#define OMAP44XX_CORTEXA9_PRM_OFFSET 0x00003200UL
-#define OMAP44XX_CORTEXA9_CPU0_OFFSET 0x00003400UL
-#define OMAP44XX_CORTEXA9_CPU1_OFFSET 0x00003800UL
-
-#define OMAP44XX_SCU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_SCU_OFFSET)
-#define OMAP44XX_SCU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_SCU_OFFSET)
-#define OMAP44XX_SCU_SIZE 0x00000080UL
-#define OMAP44XX_GIC_CPU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_CPU_OFFSET)
-#define OMAP44XX_GIC_CPU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_CPU_OFFSET)
-#define OMAP44XX_GIC_CPU_SIZE 0x00000100UL
-#define OMAP44XX_GBL_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GBL_TIMER_OFFSET)
-#define OMAP44XX_GBL_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GBL_TIMER_OFFSET)
-#define OMAP44XX_GBL_TIMER_SIZE 0x00000100UL
-#define OMAP44XX_PRV_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PRV_TIMER_OFFSET)
-#define OMAP44XX_PRV_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PRV_TIMER_OFFSET)
-#define OMAP44XX_PRV_TIMER_SIZE 0x00000100UL
-#define OMAP44XX_GIC_DIST_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_DIST_OFFSET)
-#define OMAP44XX_GIC_DIST_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_DIST_OFFSET)
-#define OMAP44XX_GIC_DIST_SIZE 0x00000100UL
-#define OMAP44XX_PL310_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PL310_OFFSET)
-#define OMAP44XX_PL310_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PL310_OFFSET)
-#define OMAP44XX_PL310_SIZE 0x00001000UL
-
-/*
- * L4-CORE Physical/Virtual address offsets
- */
-#define OMAP44XX_SCM_OFFSET 0x00002000UL
-#define OMAP44XX_CM_OFFSET 0x00004000UL
-#define OMAP44XX_SDMA_OFFSET 0x00056000UL
-#define OMAP44XX_USB_TLL_OFFSET 0x00062000UL
-#define OMAP44XX_USB_UHH_OFFSET 0x00064000UL
-#define OMAP44XX_USB_OHCI_OFFSET 0x00064800UL
-#define OMAP44XX_USB_EHCI_OFFSET 0x00064C00UL
-#define OMAP44XX_MCBSP1_OFFSET 0x00074000UL
-#define OMAP44XX_MCBSP5_OFFSET 0x00096000UL
-#define OMAP44XX_SCM_PADCONF_OFFSET 0x00100000UL
-
-/*
- * L4-WAKEUP Physical/Virtual address offsets
- */
-#define OMAP44XX_PRM_OFFSET 0x00006000UL
-#define OMAP44XX_SCRM_OFFSET 0x0000A000UL
-#define OMAP44XX_GPIO1_OFFSET 0x00010000UL
-#define OMAP44XX_GPTIMER1_OFFSET 0x00018000UL
-
-/*
- * L4-PERIPH Physical/Virtual address offsets
- */
-#define OMAP44XX_UART3_OFFSET 0x00020000UL
-#define OMAP44XX_GPTIMER2_OFFSET 0x00032000UL
-#define OMAP44XX_GPTIMER3_OFFSET 0x00034000UL
-#define OMAP44XX_GPTIMER4_OFFSET 0x00036000UL
-#define OMAP44XX_GPTIMER9_OFFSET 0x0003E000UL
-#define OMAP44XX_GPIO2_OFFSET 0x00055000UL
-#define OMAP44XX_GPIO3_OFFSET 0x00057000UL
-#define OMAP44XX_GPIO4_OFFSET 0x00059000UL
-#define OMAP44XX_GPIO5_OFFSET 0x0005B000UL
-#define OMAP44XX_GPIO6_OFFSET 0x0005D000UL
-#define OMAP44XX_I2C3_OFFSET 0x00060000UL
-#define OMAP44XX_UART1_OFFSET 0x0006A000UL
-#define OMAP44XX_UART2_OFFSET 0x0006C000UL
-#define OMAP44XX_UART4_OFFSET 0x0006E000UL
-#define OMAP44XX_I2C1_OFFSET 0x00070000UL
-#define OMAP44XX_I2C2_OFFSET 0x00072000UL
-#define OMAP44XX_SLIMBUS2_OFFSET 0x00076000UL
-#define OMAP44XX_ELM_OFFSET 0x00078000UL
-#define OMAP44XX_GPTIMER10_OFFSET 0x00086000UL
-#define OMAP44XX_GPTIMER11_OFFSET 0x00088000UL
-#define OMAP44XX_MCBSP4_OFFSET 0x00096000UL
-#define OMAP44XX_MCSPI1_OFFSET 0x00098000UL
-#define OMAP44XX_MCSPI2_OFFSET 0x0009A000UL
-#define OMAP44XX_MMCHS1_OFFSET 0x0009C000UL
-#define OMAP44XX_MMCSD3_OFFSET 0x000AD000UL
-#define OMAP44XX_MMCHS2_OFFSET 0x000B4000UL
-#define OMAP44XX_MMCSD4_OFFSET 0x000D1000UL
-#define OMAP44XX_MMCSD5_OFFSET 0x000D5000UL
-#define OMAP44XX_I2C4_OFFSET 0x00350000UL
-
-/* The following are registers defined as part of the ARM MPCORE system,
- * they are not SoC components rather registers that control the MPCORE core.
- */
-// #define OMAP44XX_SCU_OFFSET 0x48240000 /* Snoop control unit */
-// #define OMAP44XX_GIC_PROC_OFFSET 0x48240100 /* Interrupt controller unit */
-// #define OMAP44XX_MPU_TIMER_OFFSET 0x48240600
-// #define OMAP44XX_GIC_INTR_OFFSET 0x48241000
-// #define OMAP44XX_PL310_OFFSET 0x48242000 /* L2 Cache controller */
-
-/*
- * L4-ABE Physical/Virtual address offsets
- */
-#define OMAP44XX_GPTIMER5_OFFSET 0x00038000UL
-#define OMAP44XX_GPTIMER6_OFFSET 0x0003A000UL
-#define OMAP44XX_GPTIMER7_OFFSET 0x0003C000UL
-#define OMAP44XX_GPTIMER8_OFFSET 0x0003E000UL
-
-/*
- * System Control Module
- */
-#define OMAP44XX_SCM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_OFFSET)
-#define OMAP44XX_SCM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_OFFSET)
-#define OMAP44XX_SCM_SIZE 0x00001000UL
-
-/*
- *
- */
-#define OMAP44XX_CM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_CM_OFFSET)
-#define OMAP44XX_CM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_CM_OFFSET)
-#define OMAP44XX_CM_SIZE 0x00001500UL
-
-/*
- *
- */
-#define OMAP44XX_PRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_PRM_OFFSET)
-#define OMAP44XX_PRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_PRM_OFFSET)
-#define OMAP44XX_PRM_SIZE 0x00001600UL
-
-/*
- *
- */
-#define OMAP44XX_SCRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_SCRM_OFFSET)
-#define OMAP44XX_SCRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_SCRM_OFFSET)
-#define OMAP44XX_SCRM_SIZE 0x00000800UL
-
-/*
- * Uarts
- */
-#define OMAP44XX_UART1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART1_OFFSET)
-#define OMAP44XX_UART1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART1_OFFSET)
-#define OMAP44XX_UART1_SIZE 0x00001000UL
-#define OMAP44XX_UART2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART2_OFFSET)
-#define OMAP44XX_UART2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART2_OFFSET)
-#define OMAP44XX_UART2_SIZE 0x00001000UL
-#define OMAP44XX_UART3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART3_OFFSET)
-#define OMAP44XX_UART3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART3_OFFSET)
-#define OMAP44XX_UART3_SIZE 0x00001000UL
-#define OMAP44XX_UART4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART4_OFFSET)
-#define OMAP44XX_UART4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART4_OFFSET)
-#define OMAP44XX_UART4_SIZE 0x00001000UL
-
-/*
- * I2C Modules
- */
-#define OMAP44XX_I2C1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C1_OFFSET)
-#define OMAP44XX_I2C1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C1_OFFSET)
-#define OMAP44XX_I2C1_SIZE 0x00000080UL
-#define OMAP44XX_I2C2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C2_OFFSET)
-#define OMAP44XX_I2C2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C2_OFFSET)
-#define OMAP44XX_I2C2_SIZE 0x00000080UL
-#define OMAP44XX_I2C3_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C3_OFFSET)
-#define OMAP44XX_I2C3_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C3_OFFSET)
-#define OMAP44XX_I2C3_SIZE 0x00000080UL
-
-/*
- * McBSP Modules
- */
-#define OMAP44XX_MCBSP1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP1_OFFSET)
-#define OMAP44XX_MCBSP1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP1_OFFSET)
-#define OMAP44XX_MCBSP1_SIZE 0x00001000UL
-#define OMAP44XX_MCBSP2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP2_OFFSET)
-#define OMAP44XX_MCBSP2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP2_OFFSET)
-#define OMAP44XX_MCBSP2_SIZE 0x00001000UL
-#define OMAP44XX_MCBSP3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP3_OFFSET)
-#define OMAP44XX_MCBSP3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP3_OFFSET)
-#define OMAP44XX_MCBSP3_SIZE 0x00001000UL
-#define OMAP44XX_MCBSP4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP4_OFFSET)
-#define OMAP44XX_MCBSP4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP4_OFFSET)
-#define OMAP44XX_MCBSP4_SIZE 0x00001000UL
-#define OMAP44XX_MCBSP5_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP5_OFFSET)
-#define OMAP44XX_MCBSP5_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP5_OFFSET)
-#define OMAP44XX_MCBSP5_SIZE 0x00001000UL
-
-/*
- * USB TTL Module
- */
-#define OMAP44XX_USB_TLL_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_TLL_OFFSET)
-#define OMAP44XX_USB_TLL_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_TLL_OFFSET)
-#define OMAP44XX_USB_TLL_SIZE 0x00001000UL
-
-/*
- * USB Host Module
- */
-#define OMAP44XX_USB_UHH_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_UHH_OFFSET)
-#define OMAP44XX_USB_UHH_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_UHH_OFFSET)
-#define OMAP44XX_USB_UHH_SIZE 0x00000700UL
-
-/*
- * USB OHCI Module
- */
-#define OMAP44XX_USB_OHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_OHCI_OFFSET)
-#define OMAP44XX_USB_OHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_OHCI_OFFSET)
-#define OMAP44XX_USB_OHCI_SIZE 0x00000400UL
-
-/*
- * USB EHCI Module
- */
-#define OMAP44XX_USB_EHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_EHCI_OFFSET)
-#define OMAP44XX_USB_EHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_EHCI_OFFSET)
-#define OMAP44XX_USB_EHCI_SIZE 0x0000400UL
-
-/*
- * SDMA Offset
- * PA 0x4805 6000
- */
-
-#define OMAP44XX_SDMA_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SDMA_OFFSET)
-#define OMAP44XX_SDMA_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SDMA_OFFSET)
-#define OMAP44XX_SDMA_SIZE 0x00001000UL
-
-/*
- * Interrupt Controller Unit.
- *
- * Refer to the omap4_intr.c file for interrupt controller (GIC)
- * implementation.
- *
- * Note:
- * - 16 Interprocessor interrupts (IPI): ID[15:0]
- * - 2 private Timer/Watchdog interrupts: ID[30:29]
- * - 2 legacy nFIQ & nIRQ: one per CPU, bypasses the interrupt distributor
- * logic and directly drives interrupt requests into CPU if used in
- * legacy mode (else treated like other interrupts lines with ID28
- * and ID31 respectively)
- * - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive).
- */
-#define OMAP44XX_HARDIRQ(x) (32 + (x))
-
-#define OMAP44XX_IRQ_L2CACHE OMAP44XX_HARDIRQ(0) /* L2 cache controller interrupt */
-#define OMAP44XX_IRQ_CTI_0 OMAP44XX_HARDIRQ(1) /* Cross-trigger module 0 (CTI0) interrupt */
-#define OMAP44XX_IRQ_CTI_1 OMAP44XX_HARDIRQ(2) /* Cross-trigger module 1 (CTI1) interrupt */
-#define OMAP44XX_IRQ_RESERVED3 OMAP44XX_HARDIRQ(3) /* RESERVED */
-#define OMAP44XX_IRQ_ELM OMAP44XX_HARDIRQ(4) /* Error location process completion */
-#define OMAP44XX_IRQ_RESERVED5 OMAP44XX_HARDIRQ(5) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED6 OMAP44XX_HARDIRQ(6) /* RESERVED */
-#define OMAP44XX_IRQ_SYS_NIRQ OMAP44XX_HARDIRQ(7) /* External source (active low) */
-#define OMAP44XX_IRQ_RESERVED8 OMAP44XX_HARDIRQ(8) /* RESERVED */
-#define OMAP44XX_IRQ_L3_DBG OMAP44XX_HARDIRQ(9) /* L3 interconnect debug error */
-#define OMAP44XX_IRQ_L3_APP OMAP44XX_HARDIRQ(10) /* L3 interconnect application error */
-#define OMAP44XX_IRQ_PRCM_MPU OMAP44XX_HARDIRQ(11) /* PRCM module IRQ */
-#define OMAP44XX_IRQ_SDMA0 OMAP44XX_HARDIRQ(12) /* System DMA request 0(3) */
-#define OMAP44XX_IRQ_SDMA1 OMAP44XX_HARDIRQ(13) /* System DMA request 1(3) */
-#define OMAP44XX_IRQ_SDMA2 OMAP44XX_HARDIRQ(14) /* System DMA request 2 */
-#define OMAP44XX_IRQ_SDMA3 OMAP44XX_HARDIRQ(15) /* System DMA request 3 */
-#define OMAP44XX_IRQ_MCBSP4 OMAP44XX_HARDIRQ(16) /* McBSP module 4 IRQ */
-#define OMAP44XX_IRQ_MCBSP1 OMAP44XX_HARDIRQ(17) /* McBSP module 1 IRQ */
-#define OMAP44XX_IRQ_SR1 OMAP44XX_HARDIRQ(18) /* SmartReflex™ 1 */
-#define OMAP44XX_IRQ_SR2 OMAP44XX_HARDIRQ(19) /* SmartReflex™ 2 */
-#define OMAP44XX_IRQ_GPMC OMAP44XX_HARDIRQ(20) /* General-purpose memory controller module */
-#define OMAP44XX_IRQ_SGX OMAP44XX_HARDIRQ(21) /* 2D/3D graphics module */
-#define OMAP44XX_IRQ_MCBSP2 OMAP44XX_HARDIRQ(22) /* McBSP module 2 */
-#define OMAP44XX_IRQ_MCBSP3 OMAP44XX_HARDIRQ(23) /* McBSP module 3 */
-#define OMAP44XX_IRQ_ISS5 OMAP44XX_HARDIRQ(24) /* Imaging subsystem interrupt 5 */
-#define OMAP44XX_IRQ_DSS OMAP44XX_HARDIRQ(25) /* Display subsystem module(3) */
-#define OMAP44XX_IRQ_MAIL_U0 OMAP44XX_HARDIRQ(26) /* Mailbox user 0 request */
-#define OMAP44XX_IRQ_C2C_SSCM OMAP44XX_HARDIRQ(27) /* C2C status interrupt */
-#define OMAP44XX_IRQ_DSP_MMU OMAP44XX_HARDIRQ(28) /* DSP MMU */
-#define OMAP44XX_IRQ_GPIO1_MPU OMAP44XX_HARDIRQ(29) /* GPIO module 1(3) */
-#define OMAP44XX_IRQ_GPIO2_MPU OMAP44XX_HARDIRQ(30) /* GPIO module 2(3) */
-#define OMAP44XX_IRQ_GPIO3_MPU OMAP44XX_HARDIRQ(31) /* GPIO module 3(3) */
-#define OMAP44XX_IRQ_GPIO4_MPU OMAP44XX_HARDIRQ(32) /* GPIO module 4(3) */
-#define OMAP44XX_IRQ_GPIO5_MPU OMAP44XX_HARDIRQ(33) /* GPIO module 5(3) */
-#define OMAP44XX_IRQ_GPIO6_MPU OMAP44XX_HARDIRQ(34) /* GPIO module 6(3) */
-#define OMAP44XX_IRQ_RESERVED35 OMAP44XX_HARDIRQ(35) /* RESERVED */
-#define OMAP44XX_IRQ_WDT3 OMAP44XX_HARDIRQ(36) /* Watchdog timer module 3 overflow */
-#define OMAP44XX_IRQ_GPT1 OMAP44XX_HARDIRQ(37) /* General-purpose timer module 1 */
-#define OMAP44XX_IRQ_GPT2 OMAP44XX_HARDIRQ(38) /* General-purpose timer module 2 */
-#define OMAP44XX_IRQ_GPT3 OMAP44XX_HARDIRQ(39) /* General-purpose timer module 3 */
-#define OMAP44XX_IRQ_GPT4 OMAP44XX_HARDIRQ(40) /* General-purpose timer module 4 */
-#define OMAP44XX_IRQ_GPT5 OMAP44XX_HARDIRQ(41) /* General-purpose timer module 5 */
-#define OMAP44XX_IRQ_GPT6 OMAP44XX_HARDIRQ(42) /* General-purpose timer module 6 */
-#define OMAP44XX_IRQ_GPT7 OMAP44XX_HARDIRQ(43) /* General-purpose timer module 7 */
-#define OMAP44XX_IRQ_GPT8 OMAP44XX_HARDIRQ(44) /* General-purpose timer module 8 */
-#define OMAP44XX_IRQ_GPT9 OMAP44XX_HARDIRQ(45) /* General-purpose timer module 9 */
-#define OMAP44XX_IRQ_GPT10 OMAP44XX_HARDIRQ(46) /* General-purpose timer module 10 */
-#define OMAP44XX_IRQ_GPT11 OMAP44XX_HARDIRQ(47) /* General-purpose timer module 11 */
-#define OMAP44XX_IRQ_MCSPI4 OMAP44XX_HARDIRQ(48) /* McSPI module 4 */
-#define OMAP44XX_IRQ_RESERVED49 OMAP44XX_HARDIRQ(49) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED50 OMAP44XX_HARDIRQ(50) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED51 OMAP44XX_HARDIRQ(51) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED52 OMAP44XX_HARDIRQ(52) /* RESERVED */
-#define OMAP44XX_IRQ_DSS_DSI1 OMAP44XX_HARDIRQ(53) /* Display Subsystem DSI1 interrupt */
-#define OMAP44XX_IRQ_RESERVED54 OMAP44XX_HARDIRQ(54) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED55 OMAP44XX_HARDIRQ(55) /* RESERVED */
-#define OMAP44XX_IRQ_I2C1 OMAP44XX_HARDIRQ(56) /* I2C module 1 */
-#define OMAP44XX_IRQ_I2C2 OMAP44XX_HARDIRQ(57) /* I2C module 2 */
-#define OMAP44XX_IRQ_HDQ OMAP44XX_HARDIRQ(58) /* HDQ / One-wire */
-#define OMAP44XX_IRQ_MMC5 OMAP44XX_HARDIRQ(59) /* MMC5 interrupt */
-#define OMAP44XX_IRQ_RESERVED60 OMAP44XX_HARDIRQ(60) /* RESERVED */
-#define OMAP44XX_IRQ_I2C3 OMAP44XX_HARDIRQ(61) /* I2C module 3 */
-#define OMAP44XX_IRQ_I2C4 OMAP44XX_HARDIRQ(62) /* I2C module 4 */
-#define OMAP44XX_IRQ_RESERVED63 OMAP44XX_HARDIRQ(63) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED64 OMAP44XX_HARDIRQ(64) /* RESERVED */
-#define OMAP44XX_IRQ_MCSPI1 OMAP44XX_HARDIRQ(65) /* McSPI module 1 */
-#define OMAP44XX_IRQ_MCSPI2 OMAP44XX_HARDIRQ(66) /* McSPI module 2 */
-#define OMAP44XX_IRQ_HSI_P1 OMAP44XX_HARDIRQ(67) /* HSI Port 1 interrupt */
-#define OMAP44XX_IRQ_HSI_P2 OMAP44XX_HARDIRQ(68) /* HSI Port 2 interrupt */
-#define OMAP44XX_IRQ_FDIF_3 OMAP44XX_HARDIRQ(69) /* Face detect interrupt 3 */
-#define OMAP44XX_IRQ_UART4 OMAP44XX_HARDIRQ(70) /* UART module 4 interrupt */
-#define OMAP44XX_IRQ_HSI_DMA OMAP44XX_HARDIRQ(71) /* HSI DMA engine MPU request */
-#define OMAP44XX_IRQ_UART1 OMAP44XX_HARDIRQ(72) /* UART module 1 */
-#define OMAP44XX_IRQ_UART2 OMAP44XX_HARDIRQ(73) /* UART module 2 */
-#define OMAP44XX_IRQ_UART3 OMAP44XX_HARDIRQ(74) /* UART module 3 (also infrared)(3) */
-#define OMAP44XX_IRQ_PBIAS OMAP44XX_HARDIRQ(75) /* Merged interrupt for PBIASlite1 and 2 */
-#define OMAP44XX_IRQ_OHCI OMAP44XX_HARDIRQ(76) /* OHCI controller HSUSB MP Host Interrupt */
-#define OMAP44XX_IRQ_EHCI OMAP44XX_HARDIRQ(77) /* EHCI controller HSUSB MP Host Interrupt */
-#define OMAP44XX_IRQ_TLL OMAP44XX_HARDIRQ(78) /* HSUSB MP TLL Interrupt */
-#define OMAP44XX_IRQ_RESERVED79 OMAP44XX_HARDIRQ(79) /* RESERVED */
-#define OMAP44XX_IRQ_WDT2 OMAP44XX_HARDIRQ(80) /* WDTIMER2 interrupt */
-#define OMAP44XX_IRQ_RESERVED81 OMAP44XX_HARDIRQ(81) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED82 OMAP44XX_HARDIRQ(82) /* RESERVED */
-#define OMAP44XX_IRQ_MMC1 OMAP44XX_HARDIRQ(83) /* MMC/SD module 1 */
-#define OMAP44XX_IRQ_DSS_DSI2 OMAP44XX_HARDIRQ(84) /* Display subsystem DSI2 interrupt */
-#define OMAP44XX_IRQ_RESERVED85 OMAP44XX_HARDIRQ(85) /* Reserved */
-#define OMAP44XX_IRQ_MMC2 OMAP44XX_HARDIRQ(86) /* MMC/SD module 2 */
-#define OMAP44XX_IRQ_MPU_ICR OMAP44XX_HARDIRQ(87) /* MPU ICR */
-#define OMAP44XX_IRQ_C2C_GPI OMAP44XX_HARDIRQ(88) /* C2C GPI interrupt */
-#define OMAP44XX_IRQ_FSUSB OMAP44XX_HARDIRQ(89) /* FS-USB - host controller Interrupt */
-#define OMAP44XX_IRQ_FSUSB_SMI OMAP44XX_HARDIRQ(90) /* FS-USB - host controller SMI Interrupt */
-#define OMAP44XX_IRQ_MCSPI3 OMAP44XX_HARDIRQ(91) /* McSPI module 3 */
-#define OMAP44XX_IRQ_HSUSB_OTG OMAP44XX_HARDIRQ(92) /* High-Speed USB OTG controller */
-#define OMAP44XX_IRQ_HSUSB_OTG_DMA OMAP44XX_HARDIRQ(93) /* High-Speed USB OTG DMA controller */
-#define OMAP44XX_IRQ_MMC3 OMAP44XX_HARDIRQ(94) /* MMC/SD module 3 */
-#define OMAP44XX_IRQ_RESERVED95 OMAP44XX_HARDIRQ(95) /* RESERVED */
-#define OMAP44XX_IRQ_MMC4 OMAP44XX_HARDIRQ(96) /* MMC4 interrupt */
-#define OMAP44XX_IRQ_SLIMBUS1 OMAP44XX_HARDIRQ(97) /* SLIMBUS1 interrupt */
-#define OMAP44XX_IRQ_SLIMBUS2 OMAP44XX_HARDIRQ(98) /* SLIMBUS2 interrupt */
-#define OMAP44XX_IRQ_ABE OMAP44XX_HARDIRQ(99) /* Audio back-end interrupt */
-#define OMAP44XX_IRQ_CORTEXM3_MMU OMAP44XX_HARDIRQ(100) /* Cortex-M3 MMU interrupt */
-#define OMAP44XX_IRQ_DSS_HDMI OMAP44XX_HARDIRQ(101) /* Display subsystem HDMI interrupt */
-#define OMAP44XX_IRQ_SR_IVA OMAP44XX_HARDIRQ(102) /* SmartReflex IVA interrupt */
-#define OMAP44XX_IRQ_IVAHD1 OMAP44XX_HARDIRQ(103) /* Sync interrupt from iCONT2 (vDMA) */
-#define OMAP44XX_IRQ_IVAHD2 OMAP44XX_HARDIRQ(104) /* Sync interrupt from iCONT1 */
-#define OMAP44XX_IRQ_RESERVED105 OMAP44XX_HARDIRQ(105) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED106 OMAP44XX_HARDIRQ(106) /* RESERVED */
-#define OMAP44XX_IRQ_IVAHD_MAILBOX0 OMAP44XX_HARDIRQ(107) /* IVAHD mailbox interrupt */
-#define OMAP44XX_IRQ_RESERVED108 OMAP44XX_HARDIRQ(108) /* RESERVED */
-#define OMAP44XX_IRQ_MCASP1 OMAP44XX_HARDIRQ(109) /* McASP1 transmit interrupt */
-#define OMAP44XX_IRQ_EMIF1 OMAP44XX_HARDIRQ(110) /* EMIF1 interrupt */
-#define OMAP44XX_IRQ_EMIF2 OMAP44XX_HARDIRQ(111) /* EMIF2 interrupt */
-#define OMAP44XX_IRQ_MCPDM OMAP44XX_HARDIRQ(112) /* MCPDM interrupt */
-#define OMAP44XX_IRQ_DMM OMAP44XX_HARDIRQ(113) /* DMM interrupt */
-#define OMAP44XX_IRQ_DMIC OMAP44XX_HARDIRQ(114) /* DMIC interrupt */
-#define OMAP44XX_IRQ_RESERVED115 OMAP44XX_HARDIRQ(115) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED116 OMAP44XX_HARDIRQ(116) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED117 OMAP44XX_HARDIRQ(117) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED118 OMAP44XX_HARDIRQ(118) /* RESERVED */
-#define OMAP44XX_IRQ_SYS_NIRQ2 OMAP44XX_HARDIRQ(119) /* External source 2 (active low) */
-#define OMAP44XX_IRQ_KBD OMAP44XX_HARDIRQ(120) /* Keyboard controller interrupt */
-#define OMAP44XX_IRQ_RESERVED121 OMAP44XX_HARDIRQ(121) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED122 OMAP44XX_HARDIRQ(122) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED123 OMAP44XX_HARDIRQ(123) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED124 OMAP44XX_HARDIRQ(124) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED125 OMAP44XX_HARDIRQ(125) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED126 OMAP44XX_HARDIRQ(126) /* RESERVED */
-#define OMAP44XX_IRQ_RESERVED127 OMAP44XX_HARDIRQ(127) /* RESERVED */
-
-/*
- * General Purpose Timers
- */
-#define OMAP44XX_GPTIMER1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPTIMER1_OFFSET)
-#define OMAP44XX_GPTIMER1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPTIMER1_OFFSET)
-#define OMAP44XX_GPTIMER2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER2_OFFSET)
-#define OMAP44XX_GPTIMER2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER2_OFFSET)
-#define OMAP44XX_GPTIMER3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER3_OFFSET)
-#define OMAP44XX_GPTIMER3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER3_OFFSET)
-#define OMAP44XX_GPTIMER4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER4_OFFSET)
-#define OMAP44XX_GPTIMER4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER4_OFFSET)
-#define OMAP44XX_GPTIMER5_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER5_OFFSET)
-#define OMAP44XX_GPTIMER5_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER5_OFFSET)
-#define OMAP44XX_GPTIMER6_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER6_OFFSET)
-#define OMAP44XX_GPTIMER6_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER6_OFFSET)
-#define OMAP44XX_GPTIMER7_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER7_OFFSET)
-#define OMAP44XX_GPTIMER7_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER7_OFFSET)
-#define OMAP44XX_GPTIMER8_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER8_OFFSET)
-#define OMAP44XX_GPTIMER8_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER8_OFFSET)
-#define OMAP44XX_GPTIMER9_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER9_OFFSET)
-#define OMAP44XX_GPTIMER9_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER9_OFFSET)
-#define OMAP44XX_GPTIMER10_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER10_OFFSET)
-#define OMAP44XX_GPTIMER10_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER10_OFFSET)
-#define OMAP44XX_GPTIMER11_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER11_OFFSET)
-#define OMAP44XX_GPTIMER11_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER11_OFFSET)
-#define OMAP44XX_GPTIMER_SIZE 0x00001000UL
-
-/*
- * GPIO - General Purpose IO
- */
-
-/* Base addresses for the GPIO modules */
-#define OMAP44XX_GPIO1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPIO1_OFFSET)
-#define OMAP44XX_GPIO1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPIO1_OFFSET)
-#define OMAP44XX_GPIO1_SIZE 0x00001000UL
-#define OMAP44XX_GPIO2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO2_OFFSET)
-#define OMAP44XX_GPIO2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO2_OFFSET)
-#define OMAP44XX_GPIO2_SIZE 0x00001000UL
-#define OMAP44XX_GPIO3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO3_OFFSET)
-#define OMAP44XX_GPIO3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO3_OFFSET)
-#define OMAP44XX_GPIO3_SIZE 0x00001000UL
-#define OMAP44XX_GPIO4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO4_OFFSET)
-#define OMAP44XX_GPIO4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO4_OFFSET)
-#define OMAP44XX_GPIO4_SIZE 0x00001000UL
-#define OMAP44XX_GPIO5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO5_OFFSET)
-#define OMAP44XX_GPIO5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO5_OFFSET)
-#define OMAP44XX_GPIO5_SIZE 0x00001000UL
-#define OMAP44XX_GPIO6_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO6_OFFSET)
-#define OMAP44XX_GPIO6_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO6_OFFSET)
-#define OMAP44XX_GPIO6_SIZE 0x00001000UL
-
-/*
- * MMC/SD/SDIO
- */
-
-/* Base addresses for the MMC/SD/SDIO modules */
-#define OMAP44XX_MMCHS1_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS1_OFFSET)
-#define OMAP44XX_MMCHS1_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS1_OFFSET)
-#define OMAP44XX_MMCHS2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS2_OFFSET)
-#define OMAP44XX_MMCHS2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS2_OFFSET)
-#define OMAP44XX_MMCHS3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD3_OFFSET)
-#define OMAP44XX_MMCHS3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD3_OFFSET)
-#define OMAP44XX_MMCHS4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD4_OFFSET)
-#define OMAP44XX_MMCHS4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD4_OFFSET)
-#define OMAP44XX_MMCHS5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD5_OFFSET)
-#define OMAP44XX_MMCHS5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD5_OFFSET)
-#define OMAP44XX_MMCHS_SIZE 0x00001000UL
-
-/*
- * SCM - System Control Module
- */
-
-/* Base addresses for the SC modules */
-#define OMAP44XX_SCM_PADCONF_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_PADCONF_OFFSET)
-#define OMAP44XX_SCM_PADCONF_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_PADCONF_OFFSET)
-#define OMAP44XX_SCM_PADCONF_SIZE 0x00001000UL
-
-#endif /* _OMAP44XX_REG_H_ */
diff --git a/sys/arm/ti/omap4/omap4_scm_padconf.h b/sys/arm/ti/omap4/omap4_scm_padconf.h
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_scm_padconf.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*-
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef OMAP4_SCM_PADCONF_H
-#define OMAP4_SCM_PADCONF_H
-
-#define CONTROL_PADCONF_WAKEUP_EVENT (1UL << 15)
-#define CONTROL_PADCONF_WAKEUP_ENABLE (1UL << 14)
-#define CONTROL_PADCONF_OFF_PULL_UP (1UL << 13)
-#define CONTROL_PADCONF_OFF_PULL_ENABLE (1UL << 12)
-#define CONTROL_PADCONF_OFF_OUT_HIGH (1UL << 11)
-#define CONTROL_PADCONF_OFF_OUT_ENABLE (1UL << 10)
-#define CONTROL_PADCONF_OFF_ENABLE (1UL << 9)
-#define CONTROL_PADCONF_INPUT_ENABLE (1UL << 8)
-#define CONTROL_PADCONF_PULL_UP (1UL << 4)
-#define CONTROL_PADCONF_PULL_ENABLE (1UL << 3)
-#define CONTROL_PADCONF_MUXMODE_MASK (0x7)
-
-#define CONTROL_PADCONF_SATE_MASK ( CONTROL_PADCONF_WAKEUP_EVENT \
- | CONTROL_PADCONF_WAKEUP_ENABLE \
- | CONTROL_PADCONF_OFF_PULL_UP \
- | CONTROL_PADCONF_OFF_PULL_ENABLE \
- | CONTROL_PADCONF_OFF_OUT_HIGH \
- | CONTROL_PADCONF_OFF_OUT_ENABLE \
- | CONTROL_PADCONF_OFF_ENABLE \
- | CONTROL_PADCONF_INPUT_ENABLE \
- | CONTROL_PADCONF_PULL_UP \
- | CONTROL_PADCONF_PULL_ENABLE )
-
-/* Active pin states */
-#define PADCONF_PIN_OUTPUT 0
-#define PADCONF_PIN_INPUT CONTROL_PADCONF_INPUT_ENABLE
-#define PADCONF_PIN_INPUT_PULLUP ( CONTROL_PADCONF_INPUT_ENABLE \
- | CONTROL_PADCONF_PULL_ENABLE \
- | CONTROL_PADCONF_PULL_UP)
-#define PADCONF_PIN_INPUT_PULLDOWN ( CONTROL_PADCONF_INPUT_ENABLE \
- | CONTROL_PADCONF_PULL_ENABLE )
-
-/* Off mode states */
-#define PADCONF_PIN_OFF_NONE 0
-#define PADCONF_PIN_OFF_OUTPUT_HIGH ( CONTROL_PADCONF_OFF_ENABLE \
- | CONTROL_PADCONF_OFF_OUT_ENABLE \
- | CONTROL_PADCONF_OFF_OUT_HIGH)
-#define PADCONF_PIN_OFF_OUTPUT_LOW ( CONTROL_PADCONF_OFF_ENABLE \
- | CONTROL_PADCONF_OFF_OUT_ENABLE)
-#define PADCONF_PIN_OFF_INPUT_PULLUP ( CONTROL_PADCONF_OFF_ENABLE \
- | CONTROL_PADCONF_OFF_PULL_ENABLE \
- | CONTROL_PADCONF_OFF_PULL_UP)
-#define PADCONF_PIN_OFF_INPUT_PULLDOWN ( CONTROL_PADCONF_OFF_ENABLE \
- | CONTROL_PADCONF_OFF_PULL_ENABLE)
-#define PADCONF_PIN_OFF_WAKEUPENABLE CONTROL_PADCONF_WAKEUP_ENABLE
-
-extern const struct ti_pinmux_device omap4_pinmux_dev;
-
-#endif /* OMAP4_SCM_PADCONF_H */
diff --git a/sys/arm/ti/omap4/omap4_scm_padconf.c b/sys/arm/ti/omap4/omap4_scm_padconf.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_scm_padconf.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-
-#include <arm/ti/ti_pinmux.h>
-#include <arm/ti/omap4/omap4_scm_padconf.h>
-
-/*
- * This file defines the pin mux configuration for the OMAP4xxx series of
- * devices.
- *
- * How This is Suppose to Work
- * ===========================
- * - There is a top level ti_scm module (System Control Module) that is
- * the interface for all omap drivers, which can use it to change the mux
- * settings for individual pins. (That said, typically the pin mux settings
- * are set to defaults by the 'hints' and then not altered by the driver).
- *
- * - For this to work the top level driver needs all the pin info, and hence
- * this is where this file comes in. Here we define all the pin information
- * that is supplied to the top level driver.
- *
- */
-
-#define _PINDEF(r, b, gp, gm, m0, m1, m2, m3, m4, m5, m6, m7) \
- { .reg_off = r, \
- .gpio_pin = gp, \
- .gpio_mode = gm, \
- .ballname = b, \
- .muxmodes[0] = m0, \
- .muxmodes[1] = m1, \
- .muxmodes[2] = m2, \
- .muxmodes[3] = m3, \
- .muxmodes[4] = m4, \
- .muxmodes[5] = m5, \
- .muxmodes[6] = m6, \
- .muxmodes[7] = m7, \
- }
-
-const static struct ti_pinmux_padstate ti_padstate_devmap[] = {
- {"output", PADCONF_PIN_OUTPUT},
- {"input", PADCONF_PIN_INPUT},
- {"input_pullup", PADCONF_PIN_INPUT_PULLUP},
- {"input_pulldown", PADCONF_PIN_INPUT_PULLDOWN},
- { .state = NULL }
-};
-
-/*
- * Table 18-10, p. 3470
- */
-const static struct ti_pinmux_padconf ti_padconf_devmap[] = {
- _PINDEF(0x0000, "c12", 0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0002, "d12", 0, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0004, "c13", 0, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0006, "d13", 0, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0008, "c15", 0, 0, "gpmc_ad4", "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x000a, "d15", 0, 0, "gpmc_ad5", "sdmmc2_dat5", "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x000c, "a16", 0, 0, "gpmc_ad6", "sdmmc2_dat6", "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x000e, "b16", 0, 0, "gpmc_ad7", "sdmmc2_dat7", "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0010, "c16", 32, 3, "gpmc_ad8", "kpd_row0", "c2c_data15", "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
- _PINDEF(0x0012, "d16", 33, 3, "gpmc_ad9", "kpd_row1", "c2c_data14", "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
- _PINDEF(0x0014, "c17", 34, 3, "gpmc_ad10", "kpd_row2", "c2c_data13", "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
- _PINDEF(0x0016, "d17", 35, 3, "gpmc_ad11", "kpd_row3", "c2c_data12", "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
- _PINDEF(0x0018, "c18", 36, 3, "gpmc_ad12", "kpd_col0", "c2c_data11", "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
- _PINDEF(0x001a, "d18", 37, 3, "gpmc_ad13", "kpd_col1", "c2c_data10", "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
- _PINDEF(0x001c, "c19", 38, 3, "gpmc_ad14", "kpd_col2", "c2c_data9", "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
- _PINDEF(0x001e, "d19", 39, 3, "gpmc_ad15", "kpd_col3", "c2c_data8", "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
- _PINDEF(0x0020, "b17", 40, 3, "gpmc_a16", "kpd_row4", "c2c_datain0", "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
- _PINDEF(0x0022, "a18", 41, 3, "gpmc_a17", "kpd_row5", "c2c_datain1", "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
- _PINDEF(0x0024, "b18", 42, 3, "gpmc_a18", "kpd_row6", "c2c_datain2", "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
- _PINDEF(0x0026, "a19", 43, 3, "gpmc_a19", "kpd_row7", "c2c_datain3", "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
- _PINDEF(0x0028, "b19", 44, 3, "gpmc_a20", "kpd_col4", "c2c_datain4", "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
- _PINDEF(0x002a, "b20", 45, 3, "gpmc_a21", "kpd_col5", "c2c_datain5", "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
- _PINDEF(0x002c, "a21", 46, 3, "gpmc_a22", "kpd_col6", "c2c_datain6", "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
- _PINDEF(0x002e, "b21", 47, 3, "gpmc_a23", "kpd_col7", "c2c_datain7", "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
- _PINDEF(0x0030, "c20", 48, 3, "gpmc_a24", "kpd_col8", "c2c_clkout0", "gpio_48", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0032, "d20", 49, 3, "gpmc_a25", NULL, "c2c_clkout1", "gpio_49", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0034, "b25", 50, 3, "gpmc_ncs0", NULL, NULL, "gpio_50", "sys_ndmareq0", NULL, NULL, NULL),
- _PINDEF(0x0036, "c21", 51, 3, "gpmc_ncs1", NULL, "c2c_dataout6", "gpio_51", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0038, "d21", 52, 3, "gpmc_ncs2", "kpd_row8", "c2c_dataout7", "gpio_52", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x003a, "c22", 53, 3, "gpmc_ncs3", "gpmc_dir", "c2c_dataout4", "gpio_53", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x003c, "c25", 54, 3, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", "sys_ndmareq1", NULL, NULL, NULL),
- _PINDEF(0x003e, "b22", 55, 3, "gpmc_clk", NULL, NULL, "gpio_55", "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
- _PINDEF(0x0040, "d25", 56, 3, "gpmc_nadv_ale", "dsi1_te1", NULL, "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
- _PINDEF(0x0042, "b11", 0, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0044, "b12", 0, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0046, "c23", 59, 3, "gpmc_nbe0_cle", "dsi2_te0", NULL, "gpio_59", NULL, NULL, NULL, NULL),
- _PINDEF(0x0048, "d22", 60, 3, "gpmc_nbe1", NULL, "c2c_dataout5", "gpio_60", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x004a, "b26", 61, 3, "gpmc_wait0", "dsi2_te1", NULL, "gpio_61", NULL, NULL, NULL, NULL),
- _PINDEF(0x004c, "b23", 62, 3, "gpmc_wait1", NULL, "c2c_dataout2", "gpio_62", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x004e, "d23", 100, 3, "gpmc_wait2", "usbc1_icusb_txen", "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, NULL, "safe_mode"),
- _PINDEF(0x0050, "a24", 101, 3, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
- _PINDEF(0x0052, "b24", 102, 3, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
- _PINDEF(0x0054, "c24", 103, 3, "gpmc_ncs6", "dsi2_te0", "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, NULL, "safe_mode"),
- _PINDEF(0x0056, "d24", 104, 3, "gpmc_ncs7", "dsi2_te1", "c2c_dataout1", "gpio_104", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0058, "b9", 63, 3, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x005a, "b10", 64, 3, "hdmi_cec", NULL, NULL, "gpio_64", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x005c, "a8", 65, 3, "hdmi_ddc_scl", NULL, NULL, "gpio_65", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x005e, "b8", 66, 3, "hdmi_ddc_sda", NULL, NULL, "gpio_66", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0060, "r26", 0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0062, "r25", 0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0064, "t26", 0, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0066, "t25", 0, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0068, "u26", 0, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x006a, "u25", 0, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x006c, "v26", 0, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x006e, "v25", 0, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0070, "w26", 0, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0072, "w25", 0, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0074, "m26", 0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0076, "m25", 0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0078, "n26", 0, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x007a, "n25", 0, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x007c, "t27", 81, 3, "cam_shutter", NULL, NULL, "gpio_81", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x007e, "u27", 82, 3, "cam_strobe", NULL, NULL, "gpio_82", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0080, "v27", 83, 3, "cam_globalreset", NULL, NULL, "gpio_83", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0082, "ae18", 84, 3, "usbb1_ulpitll_clk", "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", NULL, "hw_dbg20", "safe_mode"),
- _PINDEF(0x0084, "ag19", 85, 3, "usbb1_ulpitll_stp", "hsi1_cadata", "mcbsp4_clkr", "gpio_85", "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", "safe_mode"),
- _PINDEF(0x0086, "af19", 86, 3, "usbb1_ulpitll_dir", "hsi1_caflag", "mcbsp4_fsr", "gpio_86", "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
- _PINDEF(0x0088, "ae19", 87, 3, "usbb1_ulpitll_nxt", "hsi1_acready", "mcbsp4_fsx", "gpio_87", "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", "safe_mode"),
- _PINDEF(0x008a, "af18", 88, 3, "usbb1_ulpitll_dat0", "hsi1_acwake", "mcbsp4_clkx", "gpio_88", "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", "safe_mode"),
- _PINDEF(0x008c, "ag18", 89, 3, "usbb1_ulpitll_dat1", "hsi1_acdata", "mcbsp4_dx", "gpio_89", "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", "safe_mode"),
- _PINDEF(0x008e, "ae17", 90, 3, "usbb1_ulpitll_dat2", "hsi1_acflag", "mcbsp4_dr", "gpio_90", "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", "safe_mode"),
- _PINDEF(0x0090, "af17", 91, 3, "usbb1_ulpitll_dat3", "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
- _PINDEF(0x0092, "ah17", 92, 3, "usbb1_ulpitll_dat4", "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
- _PINDEF(0x0094, "ae16", 93, 3, "usbb1_ulpitll_dat5", "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
- _PINDEF(0x0096, "af16", 94, 3, "usbb1_ulpitll_dat6", "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", "safe_mode"),
- _PINDEF(0x0098, "ag16", 95, 3, "usbb1_ulpitll_dat7", "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", "safe_mode"),
- _PINDEF(0x009a, "af14", 96, 3, "usbb1_hsic_data", NULL, NULL, "gpio_96", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x009c, "ae14", 97, 3, "usbb1_hsic_strobe", NULL, NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x009e, "h2", 98, 3, "usbc1_icusb_dp", NULL, NULL, "gpio_98", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00a0, "h3", 99, 3, "usbc1_icusb_dm", NULL, NULL, "gpio_99", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00a2, "d2", 100, 3, "sdmmc1_clk", NULL, "dpm_emu19", "gpio_100", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00a4, "e3", 101, 3, "sdmmc1_cmd", NULL, "uart1_rx", "gpio_101", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00a6, "e4", 102, 3, "sdmmc1_dat0", NULL, "dpm_emu18", "gpio_102", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00a8, "e2", 103, 3, "sdmmc1_dat1", NULL, "dpm_emu17", "gpio_103", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00aa, "e1", 104, 3, "sdmmc1_dat2", NULL, "dpm_emu16", "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
- _PINDEF(0x00ac, "f4", 105, 3, "sdmmc1_dat3", NULL, "dpm_emu15", "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
- _PINDEF(0x00ae, "f3", 106, 3, "sdmmc1_dat4", NULL, NULL, "gpio_106", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00b0, "f1", 107, 3, "sdmmc1_dat5", NULL, NULL, "gpio_107", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00b2, "g4", 108, 3, "sdmmc1_dat6", NULL, NULL, "gpio_108", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00b4, "g3", 109, 3, "sdmmc1_dat7", NULL, NULL, "gpio_109", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00b6, "ad27", 110, 3, "abe_mcbsp2_clkx", "mcspi2_clk", "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", NULL, NULL, "safe_mode"),
- _PINDEF(0x00b8, "ad26", 111, 3, "abe_mcbsp2_dr", "mcspi2_somi", "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, NULL, "safe_mode"),
- _PINDEF(0x00ba, "ad25", 112, 3, "abe_mcbsp2_dx", "mcspi2_simo", "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, NULL, "safe_mode"),
- _PINDEF(0x00bc, "ac28", 113, 3, "abe_mcbsp2_fsx", "mcspi2_cs0", "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, NULL, "safe_mode"),
- _PINDEF(0x00be, "ac26", 114, 3, "abe_mcbsp1_clkx", "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00c0, "ac25", 115, 3, "abe_mcbsp1_dr", "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00c2, "ab25", 116, 3, "abe_mcbsp1_dx", "sdmmc3_dat2", "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00c4, "ac27", 117, 3, "abe_mcbsp1_fsx", "sdmmc3_dat3", "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00c6, "ag25", 0, 0, "abe_pdm_ul_data", "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00c8, "af25", 0, 0, "abe_pdm_dl_data", "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00ca, "ae25", 0, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", NULL, NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00cc, "af26", 0, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", NULL, NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00ce, "ah26", 118, 3, "abe_clks", NULL, NULL, "gpio_118", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00d0, "ae24", 119, 3, "abe_dmic_clk1", NULL, NULL, "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, "safe_mode"),
- _PINDEF(0x00d2, "af24", 120, 3, "abe_dmic_din1", NULL, NULL, "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, "safe_mode"),
- _PINDEF(0x00d4, "ag24", 121, 3, "abe_dmic_din2", "slimbus2_clock", "abe_mcasp_axr", "gpio_121", NULL, "dmtimer11_pwm_evt", NULL, "safe_mode"),
- _PINDEF(0x00d6, "ah24", 122, 3, "abe_dmic_din3", "slimbus2_data", "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", NULL, "safe_mode"),
- _PINDEF(0x00d8, "ab26", 123, 3, "uart2_cts", "sdmmc3_clk", NULL, "gpio_123", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00da, "ab27", 124, 3, "uart2_rts", "sdmmc3_cmd", NULL, "gpio_124", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00dc, "aa25", 125, 3, "uart2_rx", "sdmmc3_dat0", NULL, "gpio_125", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00de, "aa26", 126, 3, "uart2_tx", "sdmmc3_dat1", NULL, "gpio_126", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00e0, "aa27", 127, 3, "hdq_sio", "i2c3_sccb", "i2c2_sccb", "gpio_127", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00e2, "ae28", 0, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x00e4, "ae26", 0, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x00e6, "c26", 128, 3, "i2c2_scl", "uart1_rx", NULL, "gpio_128", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00e8, "d26", 129, 3, "i2c2_sda", "uart1_tx", NULL, "gpio_129", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00ea, "w27", 130, 3, "i2c3_scl", NULL, NULL, "gpio_130", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00ec, "y27", 131, 3, "i2c3_sda", NULL, NULL, "gpio_131", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00ee, "ag21", 132, 3, "i2c4_scl", NULL, NULL, "gpio_132", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00f0, "ah22", 133, 3, "i2c4_sda", NULL, NULL, "gpio_133", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00f2, "af22", 134, 3, "mcspi1_clk", NULL, NULL, "gpio_134", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00f4, "ae22", 135, 3, "mcspi1_somi", NULL, NULL, "gpio_135", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00f6, "ag22", 136, 3, "mcspi1_simo", NULL, NULL, "gpio_136", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00f8, "ae23", 137, 3, "mcspi1_cs0", NULL, NULL, "gpio_137", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00fa, "af23", 138, 3, "mcspi1_cs1", "uart1_rx", NULL, "gpio_138", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00fc, "ag23", 139, 3, "mcspi1_cs2", "uart1_cts", "slimbus2_clock", "gpio_139", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x00fe, "ah23", 140, 3, "mcspi1_cs3", "uart1_rts", "slimbus2_data", "gpio_140", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0100, "f27", 141, 3, "uart3_cts_rctx", "uart1_tx", NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0102, "f28", 142, 3, "uart3_rts_sd", NULL, NULL, "gpio_142", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0104, "g27", 143, 3, "uart3_rx_irrx", "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0106, "g28", 144, 3, "uart3_tx_irtx", "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0108, "ae5", 145, 3, "sdmmc5_clk", "mcspi2_clk", "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", NULL, "safe_mode"),
- _PINDEF(0x010a, "af5", 146, 3, "sdmmc5_cmd", "mcspi2_simo", "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", NULL, "safe_mode"),
- _PINDEF(0x010c, "ae4", 147, 3, "sdmmc5_dat0", "mcspi2_somi", "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", NULL, "safe_mode"),
- _PINDEF(0x010e, "af4", 148, 3, "sdmmc5_dat1", NULL, "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", NULL, "safe_mode"),
- _PINDEF(0x0110, "ag3", 149, 3, "sdmmc5_dat2", "mcspi2_cs1", NULL, "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
- _PINDEF(0x0112, "af3", 150, 3, "sdmmc5_dat3", "mcspi2_cs0", NULL, "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
- _PINDEF(0x0114, "ae21", 151, 3, "mcspi4_clk", "sdmmc4_clk", "kpd_col6", "gpio_151", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0116, "af20", 152, 3, "mcspi4_simo", "sdmmc4_cmd", "kpd_col7", "gpio_152", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0118, "af21", 153, 3, "mcspi4_somi", "sdmmc4_dat0", "kpd_row6", "gpio_153", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x011a, "ae20", 154, 3, "mcspi4_cs0", "sdmmc4_dat3", "kpd_row7", "gpio_154", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x011c, "ag20", 155, 3, "uart4_rx", "sdmmc4_dat2", "kpd_row8", "gpio_155", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x011e, "ah19", 156, 3, "uart4_tx", "sdmmc4_dat1", "kpd_col8", "gpio_156", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0120, "ag12", 157, 3, "usbb2_ulpitll_clk", "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", "hsi2_cawake", NULL, NULL, "safe_mode"),
- _PINDEF(0x0122, "af12", 158, 3, "usbb2_ulpitll_stp", "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
- _PINDEF(0x0124, "ae12", 159, 3, "usbb2_ulpitll_dir", "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
- _PINDEF(0x0126, "ag13", 160, 3, "usbb2_ulpitll_nxt", "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
- _PINDEF(0x0128, "ae11", 161, 3, "usbb2_ulpitll_dat0", "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", "safe_mode"),
- _PINDEF(0x012a, "af11", 162, 3, "usbb2_ulpitll_dat1", "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", "safe_mode"),
- _PINDEF(0x012c, "ag11", 163, 3, "usbb2_ulpitll_dat2", "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", "safe_mode"),
- _PINDEF(0x012e, "ah11", 164, 3, "usbb2_ulpitll_dat3", "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", "hsi2_caready", "dispc2_data15", "rfbi_data15", "safe_mode"),
- _PINDEF(0x0130, "ae10", 165, 3, "usbb2_ulpitll_dat4", "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", "mcspi3_somi", "dispc2_data14", "rfbi_data14", "safe_mode"),
- _PINDEF(0x0132, "af10", 166, 3, "usbb2_ulpitll_dat5", "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", "mcspi3_cs0", "dispc2_data13", "rfbi_data13", "safe_mode"),
- _PINDEF(0x0134, "ag10", 167, 3, "usbb2_ulpitll_dat6", "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", "mcspi3_simo", "dispc2_data12", "rfbi_data12", "safe_mode"),
- _PINDEF(0x0136, "ae9", 168, 3, "usbb2_ulpitll_dat7", "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", "mcspi3_clk", "dispc2_data11", "rfbi_data11", "safe_mode"),
- _PINDEF(0x0138, "af13", 169, 3, "usbb2_hsic_data", NULL, NULL, "gpio_169", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x013a, "ae13", 170, 3, "usbb2_hsic_strobe", NULL, NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x013c, "g26", 171, 3, "kpd_col3", "kpd_col0", NULL, "gpio_171", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x013e, "g25", 172, 3, "kpd_col4", "kpd_col1", NULL, "gpio_172", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0140, "h26", 173, 3, "kpd_col5", "kpd_col2", NULL, "gpio_173", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0142, "h25", 174, 3, "kpd_col0", "kpd_col3", NULL, "gpio_174", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0144, "j27", 0, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0146, "h27", 1, 3, "kpd_col2", "kpd_col5", NULL, "gpio_1", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0148, "j26", 175, 3, "kpd_row3", "kpd_row0", NULL, "gpio_175", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x014a, "j25", 176, 3, "kpd_row4", "kpd_row1", NULL, "gpio_176", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x014c, "k26", 177, 3, "kpd_row5", "kpd_row2", NULL, "gpio_177", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x014e, "k25", 178, 3, "kpd_row0", "kpd_row3", NULL, "gpio_178", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0150, "l27", 2, 3, "kpd_row1", "kpd_row4", NULL, "gpio_2", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0152, "k27", 3, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0154, "c3", 0, 0, "usba0_otg_ce", NULL, NULL, NULL, NULL, NULL, NULL, NULL),
- _PINDEF(0x0156, "b5", 0, 0, "usba0_otg_dp", "uart3_rx_irrx", "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0158, "b4", 0, 0, "usba0_otg_dm", "uart3_tx_irtx", "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x015a, "aa28", 181, 3, "fref_clk1_out", NULL, NULL, "gpio_181", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x015c, "y28", 182, 3, "fref_clk2_out", NULL, NULL, "gpio_182", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x015e, "ae6", 0, 0, "sys_nirq1", NULL, NULL, NULL, NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0160, "af6", 183, 3, "sys_nirq2", NULL, NULL, "gpio_183", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0162, "f26", 184, 3, "sys_boot0", NULL, NULL, "gpio_184", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0164, "e27", 185, 3, "sys_boot1", NULL, NULL, "gpio_185", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0166, "e26", 186, 3, "sys_boot2", NULL, NULL, "gpio_186", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x0168, "e25", 187, 3, "sys_boot3", NULL, NULL, "gpio_187", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x016a, "d28", 188, 3, "sys_boot4", NULL, NULL, "gpio_188", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x016c, "d27", 189, 3, "sys_boot5", NULL, NULL, "gpio_189", NULL, NULL, NULL, "safe_mode"),
- _PINDEF(0x016e, "m2", 11, 3, "dpm_emu0", NULL, NULL, "gpio_11", NULL, NULL, "hw_dbg0", "safe_mode"),
- _PINDEF(0x0170, "n2", 12, 3, "dpm_emu1", NULL, NULL, "gpio_12", NULL, NULL, "hw_dbg1", "safe_mode"),
- _PINDEF(0x0172, "p2", 13, 3, "dpm_emu2", "usba0_ulpiphy_clk", NULL, "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "safe_mode"),
- _PINDEF(0x0174, "v1", 14, 3, "dpm_emu3", "usba0_ulpiphy_stp", NULL, "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", "safe_mode"),
- _PINDEF(0x0176, "v2", 15, 3, "dpm_emu4", "usba0_ulpiphy_dir", NULL, "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", "safe_mode"),
- _PINDEF(0x0178, "w1", 16, 3, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, "gpio_16", "rfbi_te_vsync0", "dispc2_data16", "hw_dbg5", "safe_mode"),
- _PINDEF(0x017a, "w2", 17, 3, "dpm_emu6", "usba0_ulpiphy_dat0", "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", "dispc2_data17", "hw_dbg6", "safe_mode"),
- _PINDEF(0x017c, "w3", 18, 3, "dpm_emu7", "usba0_ulpiphy_dat1", "uart3_rx_irrx", "gpio_18", "rfbi_cs0", "dispc2_hsync", "hw_dbg7", "safe_mode"),
- _PINDEF(0x017e, "w4", 19, 3, "dpm_emu8", "usba0_ulpiphy_dat2", "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", "hw_dbg8", "safe_mode"),
- _PINDEF(0x0180, "y2", 20, 3, "dpm_emu9", "usba0_ulpiphy_dat3", "uart3_cts_rctx", "gpio_20", "rfbi_we", "dispc2_vsync", "hw_dbg9", "safe_mode"),
- _PINDEF(0x0182, "y3", 21, 3, "dpm_emu10", "usba0_ulpiphy_dat4", NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", "safe_mode"),
- _PINDEF(0x0184, "y4", 22, 3, "dpm_emu11", "usba0_ulpiphy_dat5", NULL, "gpio_22", "rfbi_data8", "dispc2_data8", "hw_dbg11", "safe_mode"),
- _PINDEF(0x0186, "aa1", 23, 3, "dpm_emu12", "usba0_ulpiphy_dat6", NULL, "gpio_23", "rfbi_data7", "dispc2_data7", "hw_dbg12", "safe_mode"),
- _PINDEF(0x0188, "aa2", 24, 3, "dpm_emu13", "usba0_ulpiphy_dat7", NULL, "gpio_24", "rfbi_data6", "dispc2_data6", "hw_dbg13", "safe_mode"),
- _PINDEF(0x018a, "aa3", 25, 3, "dpm_emu14", "sys_drm_msecure", "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", "hw_dbg14", "safe_mode"),
- _PINDEF(0x018c, "aa4", 26, 3, "dpm_emu15", "sys_secure_indicator", NULL, "gpio_26", "rfbi_data4", "dispc2_data4", "hw_dbg15", "safe_mode"),
- _PINDEF(0x018e, "ab2", 27, 3, "dpm_emu16", "dmtimer8_pwm_evt", "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", "hw_dbg16", "safe_mode"),
- _PINDEF(0x0190, "ab3", 28, 3, "dpm_emu17", "dmtimer9_pwm_evt", "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", "hw_dbg17", "safe_mode"),
- _PINDEF(0x0192, "ab4", 190, 3, "dpm_emu18", "dmtimer10_pwm_evt", "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", "hw_dbg18", "safe_mode"),
- _PINDEF(0x0194, "ac4", 191, 3, "dpm_emu19", "dmtimer11_pwm_evt", "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", "hw_dbg19", "safe_mode"),
- { .ballname = NULL },
-};
-
-const struct ti_pinmux_device omap4_pinmux_dev = {
- .padconf_muxmode_mask = CONTROL_PADCONF_MUXMODE_MASK,
- .padconf_sate_mask = CONTROL_PADCONF_SATE_MASK,
- .padstate = ti_padstate_devmap,
- .padconf = ti_padconf_devmap,
-};
diff --git a/sys/arm/ti/omap4/omap4_smc.h b/sys/arm/ti/omap4/omap4_smc.h
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_smc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012 Olivier Houchard. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- */
-
-#ifndef OMAP4_SMC_H_
-#define OMAP4_SMC_H_
-/* Define the various function IDs used by the OMAP4 */
-#define L2CACHE_WRITE_DEBUG_REG 0x100
-#define L2CACHE_CLEAN_INV_RANG 0x101
-#define L2CACHE_WRITE_CTRL_REG 0x102
-#define READ_AUX_CORE_REGS 0x103
-#define MODIFY_AUX_CORE_0 0x104
-#define WRITE_AUX_CORE_1 0x105
-#define READ_WKG_CTRL_REG 0x106
-#define CLEAR_WKG_CTRL_REG 0x107
-#define SET_POWER_STATUS_REG 0x108
-#define WRITE_AUXCTRL_REG 0x109
-#define LOCKDOWN_TLB 0x10a
-#define SELECT_TLB_ENTRY_FOR_WRITE 0x10b
-#define READ_TLB_VA_ENTRY 0x10c
-#define WRITE_TLB_VA_ENTRY 0x10d
-#define READ_TLB_PA_ENTRY 0x10e
-#define WRITE_TLB_PA_ENTRY 0x10f
-#define READ_TLB_ATTR_ENTRY 0x110
-#define WRITE_TLB_ATTR_ENTRY 0x111
-#define WRITE_LATENCY_CTRL_REG 0x112
-#define WRITE_PREFETCH_CTRL_REG 0x113
-#endif /* OMAP4_SMC_H_ */
diff --git a/sys/arm/ti/omap4/omap4_wugen.c b/sys/arm/ti/omap4/omap4_wugen.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/omap4_wugen.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*-
- * Copyright (c) 2016 Svatopluk Kraus
- * Copyright (c) 2016 Michal Meloun
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/conf.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/rman.h>
-#include <sys/systm.h>
-
-#include <machine/fdt.h>
-#include <machine/intr.h>
-#include <machine/resource.h>
-
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include "pic_if.h"
-
-static struct ofw_compat_data compat_data[] = {
- {"ti,omap4-wugen-mpu", 1},
- {NULL, 0}
-};
-
-struct omap4_wugen_sc {
- device_t sc_dev;
- struct resource *sc_mem_res;
- device_t sc_parent;
-};
-
-static int
-omap4_wugen_activate_intr(device_t dev, struct intr_irqsrc *isrc,
- struct resource *res, struct intr_map_data *data)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- return (PIC_ACTIVATE_INTR(sc->sc_parent, isrc, res, data));
-}
-
-static void
-omap4_wugen_disable_intr(device_t dev, struct intr_irqsrc *isrc)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- PIC_DISABLE_INTR(sc->sc_parent, isrc);
-}
-
-static void
-omap4_wugen_enable_intr(device_t dev, struct intr_irqsrc *isrc)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- PIC_ENABLE_INTR(sc->sc_parent, isrc);
-}
-
-static int
-omap4_wugen_map_intr(device_t dev, struct intr_map_data *data,
- struct intr_irqsrc **isrcp)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- return (PIC_MAP_INTR(sc->sc_parent, data, isrcp));
-}
-
-static int
-omap4_wugen_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
- struct resource *res, struct intr_map_data *data)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- return (PIC_DEACTIVATE_INTR(sc->sc_parent, isrc, res, data));
-}
-
-static int
-omap4_wugen_setup_intr(device_t dev, struct intr_irqsrc *isrc,
- struct resource *res, struct intr_map_data *data)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- return (PIC_SETUP_INTR(sc->sc_parent, isrc, res, data));
-}
-
-static int
-omap4_wugen_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
- struct resource *res, struct intr_map_data *data)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- return (PIC_TEARDOWN_INTR(sc->sc_parent, isrc, res, data));
-}
-
-static void
-omap4_wugen_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- PIC_PRE_ITHREAD(sc->sc_parent, isrc);
-}
-
-static void
-omap4_wugen_post_ithread(device_t dev, struct intr_irqsrc *isrc)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- PIC_POST_ITHREAD(sc->sc_parent, isrc);
-}
-
-static void
-omap4_wugen_post_filter(device_t dev, struct intr_irqsrc *isrc)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- PIC_POST_FILTER(sc->sc_parent, isrc);
-}
-
-#ifdef SMP
-static int
-omap4_wugen_bind_intr(device_t dev, struct intr_irqsrc *isrc)
-{
- struct omap4_wugen_sc *sc = device_get_softc(dev);
-
- return (PIC_BIND_INTR(sc->sc_parent, isrc));
-}
-#endif
-
-static int
-omap4_wugen_probe(device_t dev)
-{
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
- return (ENXIO);
-
- return (BUS_PROBE_DEFAULT);
-}
-
-static int
-omap4_wugen_detach(device_t dev)
-{
- struct omap4_wugen_sc *sc;
-
- sc = device_get_softc(dev);
- if (sc->sc_mem_res != NULL) {
- bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
- sc->sc_mem_res = NULL;
- }
- return (0);
-}
-
-static int
-omap4_wugen_attach(device_t dev)
-{
- struct omap4_wugen_sc *sc;
- phandle_t node;
- phandle_t parent_xref;
- int rid, rv;
-
- sc = device_get_softc(dev);
- sc->sc_dev = dev;
- node = ofw_bus_get_node(dev);
-
- rv = OF_getencprop(node, "interrupt-parent", &parent_xref,
- sizeof(parent_xref));
- if (rv <= 0) {
- device_printf(dev, "can't read parent node property\n");
- goto fail;
- }
- sc->sc_parent = OF_device_from_xref(parent_xref);
- if (sc->sc_parent == NULL) {
- device_printf(dev, "can't find parent controller\n");
- goto fail;
- }
-
- rid = 0;
- sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
- RF_ACTIVE);
- if (sc->sc_mem_res == NULL) {
- device_printf(dev, "can't allocate resources\n");
- return (ENXIO);
- }
-
- if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
- device_printf(dev, "can't register PIC\n");
- goto fail;
- }
- return (0);
-
-fail:
- omap4_wugen_detach(dev);
- return (ENXIO);
-}
-
-static device_method_t omap4_wugen_methods[] = {
- DEVMETHOD(device_probe, omap4_wugen_probe),
- DEVMETHOD(device_attach, omap4_wugen_attach),
- DEVMETHOD(device_detach, omap4_wugen_detach),
-
- /* Interrupt controller interface */
- DEVMETHOD(pic_activate_intr, omap4_wugen_activate_intr),
- DEVMETHOD(pic_disable_intr, omap4_wugen_disable_intr),
- DEVMETHOD(pic_enable_intr, omap4_wugen_enable_intr),
- DEVMETHOD(pic_map_intr, omap4_wugen_map_intr),
- DEVMETHOD(pic_deactivate_intr, omap4_wugen_deactivate_intr),
- DEVMETHOD(pic_setup_intr, omap4_wugen_setup_intr),
- DEVMETHOD(pic_teardown_intr, omap4_wugen_teardown_intr),
- DEVMETHOD(pic_pre_ithread, omap4_wugen_pre_ithread),
- DEVMETHOD(pic_post_ithread, omap4_wugen_post_ithread),
- DEVMETHOD(pic_post_filter, omap4_wugen_post_filter),
-#ifdef SMP
- DEVMETHOD(pic_bind_intr, omap4_wugen_bind_intr),
-#endif
- DEVMETHOD_END
-};
-
-DEFINE_CLASS_0(omap4_wugen, omap4_wugen_driver, omap4_wugen_methods,
- sizeof(struct omap4_wugen_sc));
-EARLY_DRIVER_MODULE(omap4_wugen, simplebus, omap4_wugen_driver, NULL, NULL,
- BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1);
diff --git a/sys/arm/ti/omap4/pandaboard/pandaboard.h b/sys/arm/ti/omap4/pandaboard/pandaboard.h
deleted file mode 100644
--- a/sys/arm/ti/omap4/pandaboard/pandaboard.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2016 Olivier Houchard <cognet@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _PANDABOARD_H_
-#define _PANDABOARD_H_
-void pandaboard_usb_hub_init(void);
-#endif /* _OMAP4_MP_H_ */
diff --git a/sys/arm/ti/omap4/pandaboard/pandaboard.c b/sys/arm/ti/omap4/pandaboard/pandaboard.c
deleted file mode 100644
--- a/sys/arm/ti/omap4/pandaboard/pandaboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-
-#include <machine/bus.h>
-#include <machine/vmparam.h>
-#include <machine/fdt.h>
-
-#include <arm/ti/omap4/omap4_reg.h>
-#include <arm/ti/omap4/pandaboard/pandaboard.h>
-
-/* Registers in the SCRM that control the AUX clocks */
-#define SCRM_ALTCLKSRC (0x110)
-#define SCRM_AUXCLK0 (0x0310)
-#define SCRM_AUXCLK1 (0x0314)
-#define SCRM_AUXCLK2 (0x0318)
-#define SCRM_AUXCLK3 (0x031C)
-
-/* Some of the GPIO register set */
-#define GPIO1_OE (0x0134)
-#define GPIO1_CLEARDATAOUT (0x0190)
-#define GPIO1_SETDATAOUT (0x0194)
-#define GPIO2_OE (0x0134)
-#define GPIO2_CLEARDATAOUT (0x0190)
-#define GPIO2_SETDATAOUT (0x0194)
-
-/* Some of the PADCONF register set */
-#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT (0x058)
-#define CONTROL_CORE_PAD1_KPD_COL2 (0x186)
-#define CONTROL_CORE_PAD0_GPMC_WAIT1 (0x08C)
-
-#define REG_WRITE32(r, x) *((volatile uint32_t*)(r)) = (uint32_t)(x)
-#define REG_READ32(r) *((volatile uint32_t*)(r))
-
-#define REG_WRITE16(r, x) *((volatile uint16_t*)(r)) = (uint16_t)(x)
-#define REG_READ16(r) *((volatile uint16_t*)(r))
-
-/**
- * usb_hub_init - initialises and resets the external USB hub
- *
- * The USB hub needs to be held in reset while the power is being applied
- * and the reference clock is enabled at 19.2MHz. The following is the
- * layout of the USB hub taken from the Pandaboard reference manual.
- *
- *
- * .-------------. .--------------. .----------------.
- * | OMAP4430 | | USB3320C | | LAN9514 |
- * | | | | | USB Hub / Eth |
- * | CLK | <------ | CLKOUT | | |
- * | STP | ------> | STP | | |
- * | DIR | <------ | DIR | | |
- * | NXT | <------ | NXT | | |
- * | DAT0 | <-----> | DAT0 | | |
- * | DAT1 | <-----> | DAT1 DP | <-----> | DP |
- * | DAT2 | <-----> | DAT2 DM | <-----> | DM |
- * | DAT3 | <-----> | DAT3 | | |
- * | DAT4 | <-----> | DAT4 | | |
- * | DAT5 | <-----> | DAT5 | +----> | N_RESET |
- * | DAT6 | <-----> | DAT6 | | | |
- * | DAT7 | <-----> | DAT7 | | | |
- * | | | | | +-> | VDD33IO |
- * | AUX_CLK3 | ------> | REFCLK | | +-> | VDD33A |
- * | | | | | | | |
- * | GPIO_62 | --+---> | RESET | | | | |
- * | | | | | | | | |
- * | | | '--------------' | | '----------------'
- * | | | .--------------. | |
- * | | '---->| VOLT CONVERT |--' |
- * | | '--------------' |
- * | | |
- * | | .--------------. |
- * | GPIO_1 | ------> | TPS73633 |-----'
- * | | '--------------'
- * '-------------'
- *
- *
- * RETURNS:
- * nothing.
- */
-void
-pandaboard_usb_hub_init(void)
-{
- bus_space_handle_t scrm_addr, gpio1_addr, gpio2_addr, scm_addr;
-
- if (bus_space_map(fdtbus_bs_tag, OMAP44XX_SCRM_HWBASE,
- OMAP44XX_SCRM_SIZE, 0, &scrm_addr) != 0)
- panic("Couldn't map SCRM registers");
- if (bus_space_map(fdtbus_bs_tag, OMAP44XX_GPIO1_HWBASE,
- OMAP44XX_GPIO1_SIZE, 0, &gpio1_addr) != 0)
- panic("Couldn't map GPIO1 registers");
- if (bus_space_map(fdtbus_bs_tag, OMAP44XX_GPIO2_HWBASE,
- OMAP44XX_GPIO2_SIZE, 0, &gpio2_addr) != 0)
- panic("Couldn't map GPIO2 registers");
- if (bus_space_map(fdtbus_bs_tag, OMAP44XX_SCM_PADCONF_HWBASE,
- OMAP44XX_SCM_PADCONF_SIZE, 0, &scm_addr) != 0)
- panic("Couldn't map SCM Padconf registers");
-
- /* Need to set FREF_CLK3_OUT to 19.2 MHz and pump it out on pin GPIO_WK31.
- * We know the SYS_CLK is 38.4Mhz and therefore to get the needed 19.2Mhz,
- * just use a 2x divider and ensure the SYS_CLK is used as the source.
- */
- REG_WRITE32(scrm_addr + SCRM_AUXCLK3, (1 << 16) | /* Divider of 2 */
- (0 << 1) | /* Use the SYS_CLK as the source */
- (1 << 8)); /* Enable the clock */
-
- /* Enable the clock out to the pin (GPIO_WK31).
- * muxmode=fref_clk3_out, pullup/down=disabled, input buffer=disabled,
- * wakeup=disabled.
- */
- REG_WRITE16(scm_addr + CONTROL_WKUP_PAD0_FREF_CLK3_OUT, 0x0000);
-
- /* Disable the power to the USB hub, drive GPIO1 low */
- REG_WRITE32(gpio1_addr + GPIO1_OE, REG_READ32(gpio1_addr +
- GPIO1_OE) & ~(1UL << 1));
- REG_WRITE32(gpio1_addr + GPIO1_CLEARDATAOUT, (1UL << 1));
- REG_WRITE16(scm_addr + CONTROL_CORE_PAD1_KPD_COL2, 0x0003);
-
- /* Reset the USB PHY and Hub using GPIO_62 */
- REG_WRITE32(gpio2_addr + GPIO2_OE,
- REG_READ32(gpio2_addr + GPIO2_OE) & ~(1UL << 30));
- REG_WRITE32(gpio2_addr + GPIO2_CLEARDATAOUT, (1UL << 30));
- REG_WRITE16(scm_addr + CONTROL_CORE_PAD0_GPMC_WAIT1, 0x0003);
- DELAY(10);
- REG_WRITE32(gpio2_addr + GPIO2_SETDATAOUT, (1UL << 30));
-
- /* Enable power to the hub (GPIO_1) */
- REG_WRITE32(gpio1_addr + GPIO1_SETDATAOUT, (1UL << 1));
- bus_space_unmap(fdtbus_bs_tag, scrm_addr, OMAP44XX_SCRM_SIZE);
- bus_space_unmap(fdtbus_bs_tag, gpio1_addr, OMAP44XX_GPIO1_SIZE);
- bus_space_unmap(fdtbus_bs_tag, gpio2_addr, OMAP44XX_GPIO2_SIZE);
- bus_space_unmap(fdtbus_bs_tag, scm_addr, OMAP44XX_SCM_PADCONF_SIZE);
-}
diff --git a/sys/arm/ti/omap4/std.omap4 b/sys/arm/ti/omap4/std.omap4
deleted file mode 100644
--- a/sys/arm/ti/omap4/std.omap4
+++ /dev/null
@@ -1,7 +0,0 @@
-# Omap4430 generic configuration
-files "../ti/omap4/files.omap4"
-include "../ti/std.ti"
-
-cpu CPU_CORTEXA
-
-options SOC_OMAP4
diff --git a/sys/arm/ti/ti_cpuid.h b/sys/arm/ti/ti_cpuid.h
--- a/sys/arm/ti/ti_cpuid.h
+++ b/sys/arm/ti/ti_cpuid.h
@@ -30,44 +30,8 @@
#ifndef _TI_CPUID_H_
#define _TI_CPUID_H_
-#define OMAP_MAKEREV(d, a, b, c) \
- (uint32_t)(((d) << 16) | (((a) & 0xf) << 8) | (((b) & 0xf) << 4) | ((c) & 0xf))
-
-#define OMAP_REV_DEVICE(x) (((x) >> 16) & 0xffff)
-#define OMAP_REV_MAJOR(x) (((x) >> 8) & 0xf)
-#define OMAP_REV_MINOR(x) (((x) >> 4) & 0xf)
-#define OMAP_REV_MINOR_MINOR(x) (((x) >> 0) & 0xf)
-
-#define OMAP3350_DEV 0x3530
-#define OMAP3350_REV_ES1_0 OMAP_MAKEREV(OMAP3350_DEV, 1, 0, 0)
-#define OMAP3530_REV_ES2_0 OMAP_MAKEREV(OMAP3350_DEV, 2, 0, 0)
-#define OMAP3530_REV_ES2_1 OMAP_MAKEREV(OMAP3350_DEV, 2, 1, 0)
-#define OMAP3530_REV_ES3_0 OMAP_MAKEREV(OMAP3350_DEV, 3, 0, 0)
-#define OMAP3530_REV_ES3_1 OMAP_MAKEREV(OMAP3350_DEV, 3, 1, 0)
-#define OMAP3530_REV_ES3_1_2 OMAP_MAKEREV(OMAP3350_DEV, 3, 1, 2)
-
-#define OMAP4430_DEV 0x4430
-#define OMAP4430_REV_ES1_0 OMAP_MAKEREV(OMAP4430_DEV, 1, 0, 0)
-#define OMAP4430_REV_ES2_0 OMAP_MAKEREV(OMAP4430_DEV, 2, 0, 0)
-#define OMAP4430_REV_ES2_1 OMAP_MAKEREV(OMAP4430_DEV, 2, 1, 0)
-#define OMAP4430_REV_ES2_2 OMAP_MAKEREV(OMAP4430_DEV, 2, 2, 0)
-#define OMAP4430_REV_ES2_3 OMAP_MAKEREV(OMAP4430_DEV, 2, 3, 0)
-#define OMAP4430_REV_UNKNOWN OMAP_MAKEREV(OMAP4430_DEV, 9, 9, 9)
-
-#define OMAP4460_DEV 0x4460
-#define OMAP4460_REV_ES1_0 OMAP_MAKEREV(OMAP4460_DEV, 1, 0, 0)
-#define OMAP4460_REV_ES1_1 OMAP_MAKEREV(OMAP4460_DEV, 1, 1, 0)
-#define OMAP4460_REV_UNKNOWN OMAP_MAKEREV(OMAP4460_DEV, 9, 9, 9)
-
-#define OMAP4470_DEV 0x4470
-#define OMAP4470_REV_ES1_0 OMAP_MAKEREV(OMAP4470_DEV, 1, 0, 0)
-#define OMAP4470_REV_UNKNOWN OMAP_MAKEREV(OMAP4470_DEV, 9, 9, 9)
-
-#define OMAP_UNKNOWN_DEV OMAP_MAKEREV(0x9999, 9, 9, 9)
-
#define AM335X_DEVREV(x) ((x) >> 28)
-#define CHIP_OMAP_4 0
#define CHIP_AM335X 1
extern int _ti_chip;
diff --git a/sys/arm/ti/ti_cpuid.c b/sys/arm/ti/ti_cpuid.c
--- a/sys/arm/ti/ti_cpuid.c
+++ b/sys/arm/ti/ti_cpuid.c
@@ -51,19 +51,8 @@
#include <arm/ti/tivar.h>
#include <arm/ti/ti_cpuid.h>
-#include <arm/ti/omap4/omap4_reg.h>
#include <arm/ti/am335x/am335x_reg.h>
-#define OMAP4_STD_FUSE_DIE_ID_0 0x2200
-#define OMAP4_ID_CODE 0x2204
-#define OMAP4_STD_FUSE_DIE_ID_1 0x2208
-#define OMAP4_STD_FUSE_DIE_ID_2 0x220C
-#define OMAP4_STD_FUSE_DIE_ID_3 0x2210
-#define OMAP4_STD_FUSE_PROD_ID_0 0x2214
-#define OMAP4_STD_FUSE_PROD_ID_1 0x2218
-
-#define OMAP3_ID_CODE 0xA204
-
static uint32_t chip_revision = 0xffffffff;
/**
@@ -81,125 +70,6 @@
return chip_revision;
}
-/**
- * omap4_get_revision - determines omap4 revision
- *
- * Reads the registers to determine the revision of the chip we are currently
- * running on. Stores the information in global variables.
- *
- *
- */
-static void
-omap4_get_revision(void)
-{
- uint32_t id_code;
- uint32_t revision;
- uint32_t hawkeye;
- bus_space_handle_t bsh;
-
- /* The chip revsion is read from the device identification registers and
- * the JTAG (?) tap registers, which are located in address 0x4A00_2200 to
- * 0x4A00_2218. This is part of the L4_CORE memory range and should have
- * been mapped in by the machdep.c code.
- *
- * STD_FUSE_DIE_ID_0 0x4A00 2200
- * ID_CODE 0x4A00 2204 (this is the only one we need)
- * STD_FUSE_DIE_ID_1 0x4A00 2208
- * STD_FUSE_DIE_ID_2 0x4A00 220C
- * STD_FUSE_DIE_ID_3 0x4A00 2210
- * STD_FUSE_PROD_ID_0 0x4A00 2214
- * STD_FUSE_PROD_ID_1 0x4A00 2218
- */
- /* FIXME Should we map somewhere else? */
- bus_space_map(fdtbus_bs_tag,OMAP44XX_L4_CORE_HWBASE, 0x4000, 0, &bsh);
- id_code = bus_space_read_4(fdtbus_bs_tag, bsh, OMAP4_ID_CODE);
- bus_space_unmap(fdtbus_bs_tag, bsh, 0x4000);
-
- hawkeye = ((id_code >> 12) & 0xffff);
- revision = ((id_code >> 28) & 0xf);
-
- /* Apparently according to the linux code there were some ES2.0 samples that
- * have the wrong id code and report themselves as ES1.0 silicon. So used
- * the ARM cpuid to get the correct revision.
- */
- if (revision == 0) {
- id_code = cp15_midr_get();
- revision = (id_code & 0xf) - 1;
- }
-
- switch (hawkeye) {
- case 0xB852:
- switch (revision) {
- case 0:
- chip_revision = OMAP4430_REV_ES1_0;
- break;
- case 1:
- chip_revision = OMAP4430_REV_ES2_1;
- break;
- default:
- chip_revision = OMAP4430_REV_UNKNOWN;
- break;
- }
- break;
-
- case 0xB95C:
- switch (revision) {
- case 3:
- chip_revision = OMAP4430_REV_ES2_1;
- break;
- case 4:
- chip_revision = OMAP4430_REV_ES2_2;
- break;
- case 6:
- chip_revision = OMAP4430_REV_ES2_3;
- break;
- default:
- chip_revision = OMAP4430_REV_UNKNOWN;
- break;
- }
- break;
-
- case 0xB94E:
- switch (revision) {
- case 0:
- chip_revision = OMAP4460_REV_ES1_0;
- break;
- case 2:
- chip_revision = OMAP4460_REV_ES1_1;
- break;
- default:
- chip_revision = OMAP4460_REV_UNKNOWN;
- break;
- }
- break;
-
- case 0xB975:
- switch (revision) {
- case 0:
- chip_revision = OMAP4470_REV_ES1_0;
- break;
- default:
- chip_revision = OMAP4470_REV_UNKNOWN;
- break;
- }
- break;
-
- default:
- /* Default to the latest revision if we can't determine type */
- chip_revision = OMAP_UNKNOWN_DEV;
- break;
- }
- if (chip_revision != OMAP_UNKNOWN_DEV) {
- printf("Texas Instruments OMAP%04x Processor, Revision ES%u.%u\n",
- OMAP_REV_DEVICE(chip_revision), OMAP_REV_MAJOR(chip_revision),
- OMAP_REV_MINOR(chip_revision));
- }
- else {
- printf("Texas Instruments unknown OMAP chip: %04x, rev %d\n",
- hawkeye, revision);
- }
-}
-
static void
am335x_get_revision(void)
{
@@ -276,9 +146,6 @@
if (!ti_soc_is_supported())
return;
switch(ti_chip()) {
- case CHIP_OMAP_4:
- omap4_get_revision();
- break;
case CHIP_AM335X:
am335x_get_revision();
break;
diff --git a/sys/arm/ti/ti_gpio.c b/sys/arm/ti/ti_gpio.c
--- a/sys/arm/ti/ti_gpio.c
+++ b/sys/arm/ti/ti_gpio.c
@@ -66,7 +66,7 @@
#include "ti_gpio_if.h"
#include "pic_if.h"
-#if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
+#if !defined(SOC_TI_AM335X)
#error "Unknown SoC"
#endif
@@ -136,10 +136,6 @@
ti_gpio_rev(void)
{
switch(ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- return (OMAP4_GPIO_REV);
-#endif
#ifdef SOC_TI_AM335X
case CHIP_AM335X:
return (AM335X_GPIO_REV);
@@ -558,29 +554,6 @@
/* AM335x
* sc->sc_bank used in am335x/am335x_gpio.c and omap4/omap4_gpio.c */
switch(ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- switch (rev_address) {
- case OMAP4_GPIO1_REV:
- sc->sc_bank = 0;
- break;
- case OMAP4_GPIO2_REV:
- sc->sc_bank = 1;
- break;
- case OMAP4_GPIO3_REV:
- sc->sc_bank = 2;
- break;
- case OMAP4_GPIO4_REV:
- sc->sc_bank = 3;
- break;
- case OMAP4_GPIO5_REV:
- sc->sc_bank = 4;
- break;
- case OMAP4_GPIO6_REV:
- sc->sc_bank = 5;
- break;
- }
-#endif
#ifdef SOC_TI_AM335X
case CHIP_AM335X:
switch (rev_address) {
diff --git a/sys/arm/ti/ti_i2c.c b/sys/arm/ti/ti_i2c.c
--- a/sys/arm/ti/ti_i2c.c
+++ b/sys/arm/ti/ti_i2c.c
@@ -105,21 +105,6 @@
uint8_t hssclh; /* High Speed mode SCL high time */
};
-#if defined(SOC_OMAP4)
-/*
- * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
- * The prescaler values for 100KHz and 400KHz modes come from the table in the
- * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
- */
-static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
- { 100000, 23, 13, 15, 0, 0},
- { 400000, 9, 5, 7, 0, 0},
- { 1000000, 3, 5, 7, 0, 0},
-/* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
- { 0 /* Table terminator */ }
-};
-#endif
-
#if defined(SOC_TI_AM335X)
/*
* AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
@@ -476,11 +461,6 @@
uint16_t fifo_trsh, reg, scll, sclh;
switch (ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- clkcfg = ti_omap4_i2c_clock_configs;
- break;
-#endif
#ifdef SOC_TI_AM335X
case CHIP_AM335X:
clkcfg = ti_am335x_i2c_clock_configs;
@@ -576,17 +556,6 @@
* capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
* Multiplexing and Configuration).
*/
- switch (ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
- scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
- sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
- sc->sc_con_reg |= I2C_CON_OPMODE_HS;
- }
- break;
-#endif
- }
/* Write the selected bit rate. */
ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
diff --git a/sys/arm/ti/ti_machdep.c b/sys/arm/ti/ti_machdep.c
--- a/sys/arm/ti/ti_machdep.c
+++ b/sys/arm/ti/ti_machdep.c
@@ -58,12 +58,6 @@
#include "platform_if.h"
-#if defined(SOC_OMAP4)
-#include "platform_pl310_if.h"
-
-static platform_attach_t omap4_attach;
-static platform_devmap_init_t ti_omap4_devmap_init;
-#endif
#if defined(SOC_TI_AM335X)
static platform_attach_t ti_am335x_attach;
static platform_devmap_init_t ti_am335x_devmap_init;
@@ -74,15 +68,6 @@
int _ti_chip = -1;
-#if defined(SOC_OMAP4)
-static int
-omap4_attach(platform_t plat)
-{
- _ti_chip = CHIP_OMAP_4;
- return (0);
-}
-#endif
-
#if defined(SOC_TI_AM335X)
static int
ti_am335x_attach(platform_t plat)
@@ -96,16 +81,6 @@
* Construct static devmap entries to map out the most frequently used
* peripherals using 1mb section mappings.
*/
-#if defined(SOC_OMAP4)
-static int
-ti_omap4_devmap_init(platform_t plat)
-{
- devmap_add_entry(0x48000000, 0x01000000); /*16mb L4_PER devices */
- devmap_add_entry(0x4A000000, 0x01000000); /*16mb L4_CFG devices */
- return (0);
-}
-#endif
-
#if defined(SOC_TI_AM335X)
static int
ti_am335x_devmap_init(platform_t plat)
@@ -131,26 +106,6 @@
printf("no cpu_reset implementation\n");
}
-#if defined(SOC_OMAP4)
-static platform_method_t omap4_methods[] = {
- PLATFORMMETHOD(platform_attach, omap4_attach),
- PLATFORMMETHOD(platform_devmap_init, ti_omap4_devmap_init),
- PLATFORMMETHOD(platform_cpu_reset, ti_plat_cpu_reset),
-
-#ifdef SMP
- PLATFORMMETHOD(platform_mp_start_ap, omap4_mp_start_ap),
- PLATFORMMETHOD(platform_mp_setmaxid, omap4_mp_setmaxid),
-#endif
-
- PLATFORMMETHOD(platform_pl310_init, omap4_pl310_init),
- PLATFORMMETHOD(platform_pl310_write_ctrl, omap4_pl310_write_ctrl),
- PLATFORMMETHOD(platform_pl310_write_debug, omap4_pl310_write_debug),
-
- PLATFORMMETHOD_END,
-};
-FDT_PLATFORM_DEF(omap4, "omap4", 0, "ti,omap4430", 200);
-#endif
-
#if defined(SOC_TI_AM335X)
static platform_method_t am335x_methods[] = {
PLATFORMMETHOD(platform_attach, ti_am335x_attach),
diff --git a/sys/arm/ti/ti_pinmux.c b/sys/arm/ti/ti_pinmux.c
--- a/sys/arm/ti/ti_pinmux.c
+++ b/sys/arm/ti/ti_pinmux.c
@@ -381,11 +381,6 @@
return (EEXIST);
}
switch (ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- ti_pinmux_dev = &omap4_pinmux_dev;
- break;
-#endif
#ifdef SOC_TI_AM335X
case CHIP_AM335X:
ti_pinmux_dev = &ti_am335x_pinmux_dev;
diff --git a/sys/arm/ti/ti_prcm.c b/sys/arm/ti/ti_prcm.c
--- a/sys/arm/ti/ti_prcm.c
+++ b/sys/arm/ti/ti_prcm.c
@@ -177,11 +177,6 @@
ti_prcm_sc = sc;
switch(ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- ti_cpu_reset = omap4_prcm_reset;
- break;
-#endif
#ifdef SOC_TI_AM335X
case CHIP_AM335X:
ti_cpu_reset = am335x_prcm_reset;
@@ -288,50 +283,3 @@
{
ti_prcm_write_4(ti_prcm_sc->dev, AM335x_PRM_RSTCTRL, (1<<1));
}
-
-/* FIXME: Is this correct - or should the license part be ontop? */
-
-/* From sys/arm/ti/omap4/omap4_prcm_clks.c */
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#define PRM_RSTCTRL 0x1b00
-#define PRM_RSTCTRL_RESET 0x2
-
-static void
-omap4_prcm_reset(void)
-{
- uint32_t reg;
-
- ti_prcm_read_4(ti_prcm_sc->dev, PRM_RSTCTRL, &reg);
- reg = reg | PRM_RSTCTRL_RESET;
- ti_prcm_write_4(ti_prcm_sc->dev, PRM_RSTCTRL, reg);
- ti_prcm_read_4(ti_prcm_sc->dev, PRM_RSTCTRL, &reg);
-}
diff --git a/sys/arm/ti/ti_sdhci.c b/sys/arm/ti/ti_sdhci.c
--- a/sys/arm/ti/ti_sdhci.c
+++ b/sys/arm/ti/ti_sdhci.c
@@ -542,12 +542,6 @@
* Also for OMAP4 disable high speed mode due to erratum ID i626.
*/
switch (ti_chip()) {
-#ifdef SOC_OMAP4
- case CHIP_OMAP_4:
- sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
- sc->disable_highspeed = true;
- break;
-#endif
#ifdef SOC_TI_AM335X
case CHIP_AM335X:
sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
diff --git a/sys/arm/ti/twl/twl.h b/sys/arm/ti/twl/twl.h
deleted file mode 100644
--- a/sys/arm/ti/twl/twl.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#ifndef _TWL_H_
-#define _TWL_H_
-
-int twl_read(device_t dev, uint8_t nsub, uint8_t reg, uint8_t *buf, uint16_t cnt);
-int twl_write(device_t dev, uint8_t nsub, uint8_t reg, uint8_t *buf, uint16_t cnt);
-
-int twl_is_4030(device_t dev);
-int twl_is_6025(device_t dev);
-int twl_is_6030(device_t dev);
-
-#endif /* _TWL_H_ */
diff --git a/sys/arm/ti/twl/twl.c b/sys/arm/ti/twl/twl.c
deleted file mode 100644
--- a/sys/arm/ti/twl/twl.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-/*
- * Texas Instruments TWL4030/TWL5030/TWL60x0/TPS659x0 Power Management and
- * Audio CODEC devices.
- *
- * This code is based on the Linux TWL multifunctional device driver, which is
- * copyright (C) 2005-2006 Texas Instruments, Inc.
- *
- * These chips are typically used as support ICs for the OMAP range of embedded
- * ARM processes/SOC from Texas Instruments. They are typically used to control
- * on board voltages, however some variants have other features like audio
- * codecs, USB OTG transceivers, RTC, PWM, etc.
- *
- * This driver acts as a bus for more specific companion devices.
- *
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/sysctl.h>
-#include <sys/mutex.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <machine/intr.h>
-
-#include <dev/iicbus/iicbus.h>
-#include <dev/iicbus/iiconf.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include "arm/ti/twl/twl.h"
-
-/* TWL device IDs */
-#define TWL_DEVICE_UNKNOWN 0xffff
-#define TWL_DEVICE_4030 0x4030
-#define TWL_DEVICE_6025 0x6025
-#define TWL_DEVICE_6030 0x6030
-
-/* Each TWL device typically has more than one I2C address */
-#define TWL_MAX_SUBADDRS 4
-
-/* The maximum number of bytes that can be written in one call */
-#define TWL_MAX_IIC_DATA_SIZE 63
-
-/* The TWL devices typically use 4 I2C address for the different internal
- * register sets, plus one SmartReflex I2C address.
- */
-#define TWL_CHIP_ID0 0x48
-#define TWL_CHIP_ID1 0x49
-#define TWL_CHIP_ID2 0x4A
-#define TWL_CHIP_ID3 0x4B
-
-#define TWL_SMARTREFLEX_CHIP_ID 0x12
-
-#define TWL_INVALID_CHIP_ID 0xff
-
-struct twl_softc {
- device_t sc_dev;
- struct mtx sc_mtx;
- unsigned int sc_type;
-
- uint8_t sc_subaddr_map[TWL_MAX_SUBADDRS];
-
- struct intr_config_hook sc_scan_hook;
-
- device_t sc_vreg;
- device_t sc_clks;
-};
-
-/**
- * Macros for driver mutex locking
- */
-#define TWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
-#define TWL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
-#define TWL_LOCK_INIT(_sc) \
- mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
- "twl", MTX_DEF)
-#define TWL_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
-#define TWL_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
-#define TWL_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
-
-/**
- * twl_is_4030 - returns true if the device is TWL4030
- * twl_is_6025 - returns true if the device is TWL6025
- * twl_is_6030 - returns true if the device is TWL6030
- * @sc: device soft context
- *
- * Returns a non-zero value if the device matches.
- *
- * RETURNS:
- * Returns a non-zero value if the device matches, otherwise zero.
- */
-int
-twl_is_4030(device_t dev)
-{
- struct twl_softc *sc = device_get_softc(dev);
- return (sc->sc_type == TWL_DEVICE_4030);
-}
-
-int
-twl_is_6025(device_t dev)
-{
- struct twl_softc *sc = device_get_softc(dev);
- return (sc->sc_type == TWL_DEVICE_6025);
-}
-
-int
-twl_is_6030(device_t dev)
-{
- struct twl_softc *sc = device_get_softc(dev);
- return (sc->sc_type == TWL_DEVICE_6030);
-}
-
-/**
- * twl_read - read one or more registers from the TWL device
- * @sc: device soft context
- * @nsub: the sub-module to read from
- * @reg: the register offset within the module to read
- * @buf: buffer to store the bytes in
- * @cnt: the number of bytes to read
- *
- * Reads one or more registers and stores the result in the suppled buffer.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-int
-twl_read(device_t dev, uint8_t nsub, uint8_t reg, uint8_t *buf, uint16_t cnt)
-{
- struct twl_softc *sc;
- struct iic_msg msg[2];
- uint8_t addr;
- int rc;
-
- sc = device_get_softc(dev);
-
- TWL_LOCK(sc);
- addr = sc->sc_subaddr_map[nsub];
- TWL_UNLOCK(sc);
-
- if (addr == TWL_INVALID_CHIP_ID)
- return (EIO);
-
- /* Set the address to read from */
- msg[0].slave = addr;
- msg[0].flags = IIC_M_WR | IIC_M_NOSTOP;
- msg[0].len = 1;
- msg[0].buf = &reg;
- /* Read the data back */
- msg[1].slave = addr;
- msg[1].flags = IIC_M_RD;
- msg[1].len = cnt;
- msg[1].buf = buf;
-
- rc = iicbus_transfer(dev, msg, 2);
- if (rc != 0) {
- device_printf(dev, "iicbus read failed (adr:0x%02x, reg:0x%02x)\n",
- addr, reg);
- return (EIO);
- }
-
- return (0);
-}
-
-/**
- * twl_write - writes one or more registers to the TWL device
- * @sc: device soft context
- * @nsub: the sub-module to read from
- * @reg: the register offset within the module to read
- * @buf: data to write
- * @cnt: the number of bytes to write
- *
- * Writes one or more registers.
- *
- * RETURNS:
- * Zero on success or a negative error code on failure.
- */
-int
-twl_write(device_t dev, uint8_t nsub, uint8_t reg, uint8_t *buf, uint16_t cnt)
-{
- struct twl_softc *sc;
- struct iic_msg msg;
- uint8_t addr;
- uint8_t tmp_buf[TWL_MAX_IIC_DATA_SIZE + 1];
- int rc;
-
- if (cnt > TWL_MAX_IIC_DATA_SIZE)
- return (ENOMEM);
-
- /* Set the register address as the first byte */
- tmp_buf[0] = reg;
- memcpy(&tmp_buf[1], buf, cnt);
-
- sc = device_get_softc(dev);
-
- TWL_LOCK(sc);
- addr = sc->sc_subaddr_map[nsub];
- TWL_UNLOCK(sc);
-
- if (addr == TWL_INVALID_CHIP_ID)
- return (EIO);
-
- /* Setup the transfer and execute it */
- msg.slave = addr;
- msg.flags = IIC_M_WR;
- msg.len = cnt + 1;
- msg.buf = tmp_buf;
-
- rc = iicbus_transfer(dev, &msg, 1);
- if (rc != 0) {
- device_printf(sc->sc_dev, "iicbus write failed (adr:0x%02x, reg:0x%02x)\n",
- addr, reg);
- return (EIO);
- }
-
- return (0);
-}
-
-/**
- * twl_test_present - checks if a device with given address is present
- * @sc: device soft context
- * @addr: the address of the device to scan for
- *
- * Sends just the address byte and checks for an ACK. If no ACK then device
- * is assumed to not be present.
- *
- * RETURNS:
- * EIO if device is not present, otherwise 0 is returned.
- */
-static int
-twl_test_present(struct twl_softc *sc, uint8_t addr)
-{
- struct iic_msg msg;
- uint8_t tmp;
-
- /* Set the address to read from */
- msg.slave = addr;
- msg.flags = IIC_M_RD;
- msg.len = 1;
- msg.buf = &tmp;
-
- if (iicbus_transfer(sc->sc_dev, &msg, 1) != 0)
- return (EIO);
-
- return (0);
-}
-
-/**
- * twl_scan - scans the i2c bus for sub modules
- * @dev: the twl device
- *
- * TWL devices don't just have one i2c slave address, rather they have up to
- * 5 other addresses, each is for separate modules within the device. This
- * function scans the bus for 4 possible sub-devices and stores the info
- * internally.
- *
- */
-static void
-twl_scan(void *dev)
-{
- struct twl_softc *sc;
- unsigned i;
- uint8_t devs[TWL_MAX_SUBADDRS];
- uint8_t base = TWL_CHIP_ID0;
-
- sc = device_get_softc((device_t)dev);
-
- memset(devs, TWL_INVALID_CHIP_ID, TWL_MAX_SUBADDRS);
-
- /* Try each of the addresses (0x48, 0x49, 0x4a & 0x4b) to determine which
- * sub modules we have.
- */
- for (i = 0; i < TWL_MAX_SUBADDRS; i++) {
- if (twl_test_present(sc, (base + i)) == 0) {
- devs[i] = (base + i);
- device_printf(sc->sc_dev, "Found (sub)device at 0x%02x\n", (base + i));
- }
- }
-
- TWL_LOCK(sc);
- memcpy(sc->sc_subaddr_map, devs, TWL_MAX_SUBADDRS);
- TWL_UNLOCK(sc);
-
- /* Finished with the interrupt hook */
- config_intrhook_disestablish(&sc->sc_scan_hook);
-}
-
-/**
- * twl_probe -
- * @dev: the twl device
- *
- * Scans the FDT for a match for the device, possible compatible device
- * strings are; "ti,twl6030", "ti,twl6025", "ti,twl4030".
- *
- * The FDT compat string also determines the type of device (it is currently
- * not possible to dynamically determine the device type).
- *
- */
-static int
-twl_probe(device_t dev)
-{
- phandle_t node;
- const char *compat;
- int len, l;
- struct twl_softc *sc;
-
- if ((compat = ofw_bus_get_compat(dev)) == NULL)
- return (ENXIO);
-
- if ((node = ofw_bus_get_node(dev)) == 0)
- return (ENXIO);
-
- /* Get total 'compatible' prop len */
- if ((len = OF_getproplen(node, "compatible")) <= 0)
- return (ENXIO);
-
- sc = device_get_softc(dev);
- sc->sc_dev = dev;
- sc->sc_type = TWL_DEVICE_UNKNOWN;
-
- while (len > 0) {
- if (strncasecmp(compat, "ti,twl6030", 10) == 0)
- sc->sc_type = TWL_DEVICE_6030;
- else if (strncasecmp(compat, "ti,twl6025", 10) == 0)
- sc->sc_type = TWL_DEVICE_6025;
- else if (strncasecmp(compat, "ti,twl4030", 10) == 0)
- sc->sc_type = TWL_DEVICE_4030;
-
- if (sc->sc_type != TWL_DEVICE_UNKNOWN)
- break;
-
- /* Slide to the next sub-string. */
- l = strlen(compat) + 1;
- compat += l;
- len -= l;
- }
-
- switch (sc->sc_type) {
- case TWL_DEVICE_4030:
- device_set_desc(dev, "TI TWL4030/TPS659x0 Companion IC");
- break;
- case TWL_DEVICE_6025:
- device_set_desc(dev, "TI TWL6025 Companion IC");
- break;
- case TWL_DEVICE_6030:
- device_set_desc(dev, "TI TWL6030 Companion IC");
- break;
- case TWL_DEVICE_UNKNOWN:
- default:
- return (ENXIO);
- }
-
- return (0);
-}
-
-static int
-twl_attach(device_t dev)
-{
- struct twl_softc *sc;
-
- sc = device_get_softc(dev);
- sc->sc_dev = dev;
-
- TWL_LOCK_INIT(sc);
-
- /* We have to wait until interrupts are enabled. I2C read and write
- * only works if the interrupts are available.
- */
- sc->sc_scan_hook.ich_func = twl_scan;
- sc->sc_scan_hook.ich_arg = dev;
-
- if (config_intrhook_establish(&sc->sc_scan_hook) != 0)
- return (ENOMEM);
-
- /* FIXME: should be in DTS file */
- if ((sc->sc_vreg = device_add_child(dev, "twl_vreg", -1)) == NULL)
- device_printf(dev, "could not allocate twl_vreg instance\n");
- if ((sc->sc_clks = device_add_child(dev, "twl_clks", -1)) == NULL)
- device_printf(dev, "could not allocate twl_clks instance\n");
-
- return (bus_generic_attach(dev));
-}
-
-static int
-twl_detach(device_t dev)
-{
- struct twl_softc *sc;
-
- sc = device_get_softc(dev);
-
- if (sc->sc_vreg)
- device_delete_child(dev, sc->sc_vreg);
- if (sc->sc_clks)
- device_delete_child(dev, sc->sc_clks);
-
- TWL_LOCK_DESTROY(sc);
-
- return (0);
-}
-
-static device_method_t twl_methods[] = {
- DEVMETHOD(device_probe, twl_probe),
- DEVMETHOD(device_attach, twl_attach),
- DEVMETHOD(device_detach, twl_detach),
-
- {0, 0},
-};
-
-static driver_t twl_driver = {
- "twl",
- twl_methods,
- sizeof(struct twl_softc),
-};
-
-DRIVER_MODULE(twl, iicbus, twl_driver, 0, 0);
-MODULE_VERSION(twl, 1);
diff --git a/sys/arm/ti/twl/twl_clks.h b/sys/arm/ti/twl/twl_clks.h
deleted file mode 100644
--- a/sys/arm/ti/twl/twl_clks.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012
- * Ben Gray <bgray@freebsd.org>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#ifndef _TWL_CLKS_H_
-#define _TWL_CLKS_H_
-
-int twl_clks_enable(device_t dev, const char *name);
-int twl_clks_disable(device_t dev, const char *name);
-int twl_clks_is_enabled(device_t dev, const char *name, int *enabled);
-
-#endif /* _TWL_CLKS_H_ */
diff --git a/sys/arm/ti/twl/twl_clks.c b/sys/arm/ti/twl/twl_clks.c
deleted file mode 100644
--- a/sys/arm/ti/twl/twl_clks.c
+++ /dev/null
@@ -1,647 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012
- * Ben Gray <bgray@freebsd.org>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-/*
- * Texas Instruments TWL4030/TWL5030/TWL60x0/TPS659x0 Power Management.
- *
- * This driver covers the external clocks, allows for enabling &
- * disabling their output.
- *
- *
- *
- * FLATTENED DEVICE TREE (FDT)
- * Startup override settings can be specified in the FDT, if they are they
- * should be under the twl parent device and take the following form:
- *
- * external-clocks = "name1", "state1",
- * "name2", "state2",
- * etc;
- *
- * Each override should be a pair, the first entry is the name of the clock
- * the second is the state to set, possible strings are either "on" or "off".
- *
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/sysctl.h>
-#include <sys/sx.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <machine/intr.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-
-#include "twl.h"
-#include "twl_clks.h"
-
-static int twl_clks_debug = 1;
-
-/*
- * Power Groups bits for the 4030 and 6030 devices
- */
-#define TWL4030_P3_GRP 0x80 /* Peripherals, power group */
-#define TWL4030_P2_GRP 0x40 /* Modem power group */
-#define TWL4030_P1_GRP 0x20 /* Application power group (FreeBSD control) */
-
-#define TWL6030_P3_GRP 0x04 /* Modem power group */
-#define TWL6030_P2_GRP 0x02 /* Connectivity power group */
-#define TWL6030_P1_GRP 0x01 /* Application power group (FreeBSD control) */
-
-/*
- * Register offsets within a clk regulator register set
- */
-#define TWL_CLKS_GRP 0x00 /* Regulator GRP register */
-#define TWL_CLKS_STATE 0x02 /* TWL6030 only */
-
-/**
- * Support voltage regulators for the different IC's
- */
-struct twl_clock {
- const char *name;
- uint8_t subdev;
- uint8_t regbase;
-};
-
-static const struct twl_clock twl4030_clocks[] = {
- { "32kclkout", 0, 0x8e },
- { NULL, 0, 0x00 }
-};
-
-static const struct twl_clock twl6030_clocks[] = {
- { "clk32kg", 0, 0xbc },
- { "clk32kao", 0, 0xb9 },
- { "clk32kaudio", 0, 0xbf },
- { NULL, 0, 0x00 }
-};
-
-#define TWL_CLKS_MAX_NAMELEN 32
-
-struct twl_clk_entry {
- LIST_ENTRY(twl_clk_entry) link;
- struct sysctl_oid *oid;
- char name[TWL_CLKS_MAX_NAMELEN];
- uint8_t sub_dev; /* the sub-device number for the clock */
- uint8_t reg_off; /* register base address of the clock */
-};
-
-struct twl_clks_softc {
- device_t sc_dev; /* twl_clk device */
- device_t sc_pdev; /* parent device (twl) */
- struct sx sc_sx; /* internal locking */
- struct intr_config_hook sc_init_hook;
- LIST_HEAD(twl_clk_list, twl_clk_entry) sc_clks_list;
-};
-
-/**
- * Macros for driver shared locking
- */
-#define TWL_CLKS_XLOCK(_sc) sx_xlock(&(_sc)->sc_sx)
-#define TWL_CLKS_XUNLOCK(_sc) sx_xunlock(&(_sc)->sc_sx)
-#define TWL_CLKS_SLOCK(_sc) sx_slock(&(_sc)->sc_sx)
-#define TWL_CLKS_SUNLOCK(_sc) sx_sunlock(&(_sc)->sc_sx)
-#define TWL_CLKS_LOCK_INIT(_sc) sx_init(&(_sc)->sc_sx, "twl_clks")
-#define TWL_CLKS_LOCK_DESTROY(_sc) sx_destroy(&(_sc)->sc_sx);
-
-#define TWL_CLKS_ASSERT_LOCKED(_sc) sx_assert(&(_sc)->sc_sx, SA_LOCKED);
-
-#define TWL_CLKS_LOCK_UPGRADE(_sc) \
- do { \
- while (!sx_try_upgrade(&(_sc)->sc_sx)) \
- pause("twl_clks_ex", (hz / 100)); \
- } while(0)
-#define TWL_CLKS_LOCK_DOWNGRADE(_sc) sx_downgrade(&(_sc)->sc_sx);
-
-/**
- * twl_clks_read_1 - read single register from the TWL device
- * twl_clks_write_1 - writes a single register in the TWL device
- * @sc: device context
- * @clk: the clock device we're reading from / writing to
- * @off: offset within the clock's register set
- * @val: the value to write or a pointer to a variable to store the result
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static inline int
-twl_clks_read_1(struct twl_clks_softc *sc, struct twl_clk_entry *clk,
- uint8_t off, uint8_t *val)
-{
- return (twl_read(sc->sc_pdev, clk->sub_dev, clk->reg_off + off, val, 1));
-}
-
-static inline int
-twl_clks_write_1(struct twl_clks_softc *sc, struct twl_clk_entry *clk,
- uint8_t off, uint8_t val)
-{
- return (twl_write(sc->sc_pdev, clk->sub_dev, clk->reg_off + off, &val, 1));
-}
-
-/**
- * twl_clks_is_enabled - determines if a clock is enabled
- * @dev: TWL CLK device
- * @name: the name of the clock
- * @enabled: upon return will contain the 'enabled' state
- *
- * LOCKING:
- * Internally the function takes and releases the TWL lock.
- *
- * RETURNS:
- * Zero on success or a negative error code on failure.
- */
-int
-twl_clks_is_enabled(device_t dev, const char *name, int *enabled)
-{
- struct twl_clks_softc *sc = device_get_softc(dev);
- struct twl_clk_entry *clk;
- int found = 0;
- int err;
- uint8_t grp, state;
-
- TWL_CLKS_SLOCK(sc);
-
- LIST_FOREACH(clk, &sc->sc_clks_list, link) {
- if (strcmp(clk->name, name) == 0) {
- found = 1;
- break;
- }
- }
-
- if (!found) {
- TWL_CLKS_SUNLOCK(sc);
- return (EINVAL);
- }
-
- if (twl_is_4030(sc->sc_pdev)) {
- err = twl_clks_read_1(sc, clk, TWL_CLKS_GRP, &grp);
- if (!err)
- *enabled = (grp & TWL4030_P1_GRP);
-
- } else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev)) {
- TWL_CLKS_LOCK_UPGRADE(sc);
-
- /* Check the clock is in the application group */
- if (twl_is_6030(sc->sc_pdev)) {
- err = twl_clks_read_1(sc, clk, TWL_CLKS_GRP, &grp);
- if (err) {
- TWL_CLKS_LOCK_DOWNGRADE(sc);
- goto done;
- }
-
- if (!(grp & TWL6030_P1_GRP)) {
- TWL_CLKS_LOCK_DOWNGRADE(sc);
- *enabled = 0; /* disabled */
- goto done;
- }
- }
-
- /* Read the application mode state and verify it's ON */
- err = twl_clks_read_1(sc, clk, TWL_CLKS_STATE, &state);
- if (!err)
- *enabled = ((state & 0x0C) == 0x04);
-
- TWL_CLKS_LOCK_DOWNGRADE(sc);
-
- } else {
- err = EINVAL;
- }
-
-done:
- TWL_CLKS_SUNLOCK(sc);
- return (err);
-}
-
-/**
- * twl_clks_set_state - enables/disables a clock output
- * @sc: device context
- * @clk: the clock entry to enable/disable
- * @enable: non-zero the clock is enabled, zero the clock is disabled
- *
- * LOCKING:
- * The TWL CLK lock must be held before this function is called.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static int
-twl_clks_set_state(struct twl_clks_softc *sc, struct twl_clk_entry *clk,
- int enable)
-{
- int xlocked;
- int err;
- uint8_t grp;
-
- TWL_CLKS_ASSERT_LOCKED(sc);
-
- /* Upgrade the lock to exclusive because about to perform read-mod-write */
- xlocked = sx_xlocked(&sc->sc_sx);
- if (!xlocked)
- TWL_CLKS_LOCK_UPGRADE(sc);
-
- err = twl_clks_read_1(sc, clk, TWL_CLKS_GRP, &grp);
- if (err)
- goto done;
-
- if (twl_is_4030(sc->sc_pdev)) {
- /* On the TWL4030 we just need to ensure the clock is in the right
- * power domain, don't need to turn on explicitly like TWL6030.
- */
- if (enable)
- grp |= TWL4030_P1_GRP;
- else
- grp &= ~(TWL4030_P1_GRP | TWL4030_P2_GRP | TWL4030_P3_GRP);
-
- err = twl_clks_write_1(sc, clk, TWL_CLKS_GRP, grp);
-
- } else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev)) {
- /* Make sure the clock belongs to at least the APP power group */
- if (twl_is_6030(sc->sc_pdev) && !(grp & TWL6030_P1_GRP)) {
- grp |= TWL6030_P1_GRP;
- err = twl_clks_write_1(sc, clk, TWL_CLKS_GRP, grp);
- if (err)
- goto done;
- }
-
- /* On TWL6030 we need to make sure we disable power for all groups */
- if (twl_is_6030(sc->sc_pdev))
- grp = TWL6030_P1_GRP | TWL6030_P2_GRP | TWL6030_P3_GRP;
- else
- grp = 0x00;
-
- /* Set the state of the clock */
- if (enable)
- err = twl_clks_write_1(sc, clk, TWL_CLKS_STATE, (grp << 5) | 0x01);
- else
- err = twl_clks_write_1(sc, clk, TWL_CLKS_STATE, (grp << 5));
-
- } else {
-
- err = EINVAL;
- }
-
-done:
- if (!xlocked)
- TWL_CLKS_LOCK_DOWNGRADE(sc);
-
- if ((twl_clks_debug > 1) && !err)
- device_printf(sc->sc_dev, "%s : %sabled\n", clk->name,
- enable ? "en" : "dis");
-
- return (err);
-}
-
-/**
- * twl_clks_disable - disables a clock output
- * @dev: TWL clk device
-* @name: the name of the clock
- *
- * LOCKING:
- * Internally the function takes and releases the TWL lock.
- *
- * RETURNS:
-* Zero on success or an error code on failure.
- */
-int
-twl_clks_disable(device_t dev, const char *name)
-{
- struct twl_clks_softc *sc = device_get_softc(dev);
- struct twl_clk_entry *clk;
- int err = EINVAL;
-
- TWL_CLKS_SLOCK(sc);
-
- LIST_FOREACH(clk, &sc->sc_clks_list, link) {
- if (strcmp(clk->name, name) == 0) {
- err = twl_clks_set_state(sc, clk, 0);
- break;
- }
- }
-
- TWL_CLKS_SUNLOCK(sc);
- return (err);
-}
-
-/**
- * twl_clks_enable - enables a clock output
- * @dev: TWL clk device
- * @name: the name of the clock
- *
- * LOCKING:
- * Internally the function takes and releases the TWL CLKS lock.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-int
-twl_clks_enable(device_t dev, const char *name)
-{
- struct twl_clks_softc *sc = device_get_softc(dev);
- struct twl_clk_entry *clk;
- int err = EINVAL;
-
- TWL_CLKS_SLOCK(sc);
-
- LIST_FOREACH(clk, &sc->sc_clks_list, link) {
- if (strcmp(clk->name, name) == 0) {
- err = twl_clks_set_state(sc, clk, 1);
- break;
- }
- }
-
- TWL_CLKS_SUNLOCK(sc);
- return (err);
-}
-
-/**
- * twl_clks_sysctl_clock - reads the state of the clock
- * @SYSCTL_HANDLER_ARGS: arguments for the callback
- *
- * Returns the clock status; disabled is zero and enabled is non-zero.
- *
- * LOCKING:
- * It's expected the TWL lock is held while this function is called.
- *
- * RETURNS:
- * EIO if device is not present, otherwise 0 is returned.
- */
-static int
-twl_clks_sysctl_clock(SYSCTL_HANDLER_ARGS)
-{
- struct twl_clks_softc *sc = (struct twl_clks_softc*)arg1;
- int err;
- int enabled = 0;
-
- if ((err = twl_clks_is_enabled(sc->sc_dev, oidp->oid_name, &enabled)) != 0)
- return err;
-
- return sysctl_handle_int(oidp, &enabled, 0, req);
-}
-
-/**
- * twl_clks_add_clock - adds single clock sysctls for the device
- * @sc: device soft context
- * @name: the name of the regulator
- * @nsub: the number of the subdevice
- * @regbase: the base address of the clocks registers
- *
- * Adds a single clock to the device and also a sysctl interface for
- * querying it's status.
- *
- * LOCKING:
- * It's expected the exclusive lock is held while this function is called.
- *
- * RETURNS:
- * Pointer to the new clock entry on success, otherwise NULL on failure.
- */
-static struct twl_clk_entry*
-twl_clks_add_clock(struct twl_clks_softc *sc, const char *name,
- uint8_t nsub, uint8_t regbase)
-{
- struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
- struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
- struct twl_clk_entry *new;
-
- TWL_CLKS_ASSERT_LOCKED(sc);
-
- new = malloc(sizeof(struct twl_clk_entry), M_DEVBUF, M_NOWAIT | M_ZERO);
- if (new == NULL)
- return (NULL);
-
- strncpy(new->name, name, TWL_CLKS_MAX_NAMELEN);
- new->name[TWL_CLKS_MAX_NAMELEN - 1] = '\0';
-
- new->sub_dev = nsub;
- new->reg_off = regbase;
-
- /* Add a sysctl entry for the clock */
- new->oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, name,
- CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
- twl_clks_sysctl_clock, "I", "external clock");
-
- /* Finally add the regulator to list of supported regulators */
- LIST_INSERT_HEAD(&sc->sc_clks_list, new, link);
-
- return (new);
-}
-
-/**
- * twl_clks_add_clocks - populates the internal list of clocks
- * @sc: device soft context
- * @chip: the name of the chip used in the hints
- * @clks the list of clocks supported by the device
- *
- * Loops over the list of clocks and adds them to the device context. Also
- * scans the FDT to determine if there are any clocks that should be
- * enabled/disabled automatically.
- *
- * LOCKING:
- * Internally takes the exclusive lock while adding the clocks to the
- * device context.
- *
- * RETURNS:
- * Always returns 0.
- */
-static int
-twl_clks_add_clocks(struct twl_clks_softc *sc, const struct twl_clock *clks)
-{
- int err;
- const struct twl_clock *walker;
- struct twl_clk_entry *entry;
- phandle_t child;
- char rnames[256];
- char *name, *state;
- int len = 0, prop_len;
- int enable;
-
- TWL_CLKS_XLOCK(sc);
-
- /* Add the regulators from the list */
- walker = &clks[0];
- while (walker->name != NULL) {
- /* Add the regulator to the list */
- entry = twl_clks_add_clock(sc, walker->name, walker->subdev,
- walker->regbase);
- if (entry == NULL)
- continue;
-
- walker++;
- }
-
- /* Check for any FDT settings that need to be applied */
- child = ofw_bus_get_node(sc->sc_pdev);
- if (child) {
- prop_len = OF_getprop(child, "external-clocks", rnames, sizeof(rnames));
- while (len < prop_len) {
- name = rnames + len;
- len += strlen(name) + 1;
- if ((len >= prop_len) || (name[0] == '\0'))
- break;
-
- state = rnames + len;
- len += strlen(state) + 1;
- if (state[0] == '\0')
- break;
-
- enable = !strncmp(state, "on", 2);
-
- LIST_FOREACH(entry, &sc->sc_clks_list, link) {
- if (strcmp(entry->name, name) == 0) {
- twl_clks_set_state(sc, entry, enable);
- break;
- }
- }
- }
- }
-
- TWL_CLKS_XUNLOCK(sc);
-
- if (twl_clks_debug) {
- LIST_FOREACH(entry, &sc->sc_clks_list, link) {
- err = twl_clks_is_enabled(sc->sc_dev, entry->name, &enable);
- if (!err)
- device_printf(sc->sc_dev, "%s : %s\n", entry->name,
- enable ? "on" : "off");
- }
- }
-
- return (0);
-}
-
-/**
- * twl_clks_init - initialises the list of clocks
- * @dev: the twl_clks device
- *
- * This function is called as an intrhook once interrupts have been enabled,
- * this is done so that the driver has the option to enable/disable a clock
- * based on settings providied in the FDT.
- *
- * LOCKING:
- * May takes the exclusive lock in the function.
- */
-static void
-twl_clks_init(void *dev)
-{
- struct twl_clks_softc *sc;
-
- sc = device_get_softc((device_t)dev);
-
- if (twl_is_4030(sc->sc_pdev))
- twl_clks_add_clocks(sc, twl4030_clocks);
- else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev))
- twl_clks_add_clocks(sc, twl6030_clocks);
-
- config_intrhook_disestablish(&sc->sc_init_hook);
-}
-
-static int
-twl_clks_probe(device_t dev)
-{
- if (twl_is_4030(device_get_parent(dev)))
- device_set_desc(dev, "TI TWL4030 PMIC External Clocks");
- else if (twl_is_6025(device_get_parent(dev)) ||
- twl_is_6030(device_get_parent(dev)))
- device_set_desc(dev, "TI TWL6025/TWL6030 PMIC External Clocks");
- else
- return (ENXIO);
-
- return (0);
-}
-
-static int
-twl_clks_attach(device_t dev)
-{
- struct twl_clks_softc *sc;
-
- sc = device_get_softc(dev);
- sc->sc_dev = dev;
- sc->sc_pdev = device_get_parent(dev);
-
- TWL_CLKS_LOCK_INIT(sc);
-
- LIST_INIT(&sc->sc_clks_list);
-
- sc->sc_init_hook.ich_func = twl_clks_init;
- sc->sc_init_hook.ich_arg = dev;
-
- if (config_intrhook_establish(&sc->sc_init_hook) != 0)
- return (ENOMEM);
-
- return (0);
-}
-
-static int
-twl_clks_detach(device_t dev)
-{
- struct twl_clks_softc *sc;
- struct twl_clk_entry *clk;
- struct twl_clk_entry *tmp;
-
- sc = device_get_softc(dev);
-
- TWL_CLKS_XLOCK(sc);
-
- LIST_FOREACH_SAFE(clk, &sc->sc_clks_list, link, tmp) {
- LIST_REMOVE(clk, link);
- sysctl_remove_oid(clk->oid, 1, 0);
- free(clk, M_DEVBUF);
- }
-
- TWL_CLKS_XUNLOCK(sc);
-
- TWL_CLKS_LOCK_DESTROY(sc);
-
- return (0);
-}
-
-static device_method_t twl_clks_methods[] = {
- DEVMETHOD(device_probe, twl_clks_probe),
- DEVMETHOD(device_attach, twl_clks_attach),
- DEVMETHOD(device_detach, twl_clks_detach),
-
- {0, 0},
-};
-
-static driver_t twl_clks_driver = {
- "twl_clks",
- twl_clks_methods,
- sizeof(struct twl_clks_softc),
-};
-
-DRIVER_MODULE(twl_clks, twl, twl_clks_driver, 0, 0);
-MODULE_VERSION(twl_clks, 1);
diff --git a/sys/arm/ti/twl/twl_vreg.h b/sys/arm/ti/twl/twl_vreg.h
deleted file mode 100644
--- a/sys/arm/ti/twl/twl_vreg.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#ifndef _TWL_VREG_H_
-#define _TWL_VREG_H_
-
-int twl_vreg_get_voltage(device_t dev, const char *name, int *millivolts);
-int twl_vreg_set_voltage(device_t dev, const char *name, int millivolts);
-
-#endif /* _TWL_VREG_H_ */
diff --git a/sys/arm/ti/twl/twl_vreg.c b/sys/arm/ti/twl/twl_vreg.c
deleted file mode 100644
--- a/sys/arm/ti/twl/twl_vreg.c
+++ /dev/null
@@ -1,1026 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-/*
- * Texas Instruments TWL4030/TWL5030/TWL60x0/TPS659x0 Power Management.
- *
- * This driver covers the voltages regulators (LDO), allows for enabling &
- * disabling the voltage output and adjusting the voltage level.
- *
- * Voltage regulators can belong to different power groups, in this driver we
- * put the regulators under our control in the "Application power group".
- *
- *
- * FLATTENED DEVICE TREE (FDT)
- * Startup override settings can be specified in the FDT, if they are they
- * should be under the twl parent device and take the following form:
- *
- * voltage-regulators = "name1", "millivolts1",
- * "name2", "millivolts2";
- *
- * Each override should be a pair, the first entry is the name of the regulator
- * the second is the voltage (in millivolts) to set for the given regulator.
- *
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/sysctl.h>
-#include <sys/sx.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <machine/intr.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-
-#include "twl.h"
-#include "twl_vreg.h"
-
-static int twl_vreg_debug = 1;
-
-/*
- * Power Groups bits for the 4030 and 6030 devices
- */
-#define TWL4030_P3_GRP 0x80 /* Peripherals, power group */
-#define TWL4030_P2_GRP 0x40 /* Modem power group */
-#define TWL4030_P1_GRP 0x20 /* Application power group (FreeBSD control) */
-
-#define TWL6030_P3_GRP 0x04 /* Modem power group */
-#define TWL6030_P2_GRP 0x02 /* Connectivity power group */
-#define TWL6030_P1_GRP 0x01 /* Application power group (FreeBSD control) */
-
-/*
- * Register offsets within a LDO regulator register set
- */
-#define TWL_VREG_GRP 0x00 /* Regulator GRP register */
-#define TWL_VREG_STATE 0x02
-#define TWL_VREG_VSEL 0x03 /* Voltage select register */
-
-#define UNDF 0xFFFF
-
-static const uint16_t twl6030_voltages[] = {
- 0000, 1000, 1100, 1200, 1300, 1400, 1500, 1600,
- 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400,
- 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200,
- 3300, UNDF, UNDF, UNDF, UNDF, UNDF, UNDF, 2750
-};
-
-static const uint16_t twl4030_vaux1_voltages[] = {
- 1500, 1800, 2500, 2800, 3000, 3000, 3000, 3000
-};
-static const uint16_t twl4030_vaux2_voltages[] = {
- 1700, 1700, 1900, 1300, 1500, 1800, 2000, 2500,
- 2100, 2800, 2200, 2300, 2400, 2400, 2400, 2400
-};
-static const uint16_t twl4030_vaux3_voltages[] = {
- 1500, 1800, 2500, 2800, 3000, 3000, 3000, 3000
-};
-static const uint16_t twl4030_vaux4_voltages[] = {
- 700, 1000, 1200, 1300, 1500, 1800, 1850, 2500,
- 2600, 2800, 2850, 3000, 3150, 3150, 3150, 3150
-};
-static const uint16_t twl4030_vmmc1_voltages[] = {
- 1850, 2850, 3000, 3150
-};
-static const uint16_t twl4030_vmmc2_voltages[] = {
- 1000, 1000, 1200, 1300, 1500, 1800, 1850, 2500,
- 2600, 2800, 2850, 3000, 3150, 3150, 3150, 3150
-};
-static const uint16_t twl4030_vpll1_voltages[] = {
- 1000, 1200, 1300, 1800, 2800, 3000, 3000, 3000
-};
-static const uint16_t twl4030_vpll2_voltages[] = {
- 700, 1000, 1200, 1300, 1500, 1800, 1850, 2500,
- 2600, 2800, 2850, 3000, 3150, 3150, 3150, 3150
-};
-static const uint16_t twl4030_vsim_voltages[] = {
- 1000, 1200, 1300, 1800, 2800, 3000, 3000, 3000
-};
-static const uint16_t twl4030_vdac_voltages[] = {
- 1200, 1300, 1800, 1800
-};
-#if 0 /* vdd1, vdd2, vdio, not currently used. */
-static const uint16_t twl4030_vdd1_voltages[] = {
- 800, 1450
-};
-static const uint16_t twl4030_vdd2_voltages[] = {
- 800, 1450, 1500
-};
-static const uint16_t twl4030_vio_voltages[] = {
- 1800, 1850
-};
-#endif
-static const uint16_t twl4030_vintana2_voltages[] = {
- 2500, 2750
-};
-
-/**
- * Support voltage regulators for the different IC's
- */
-struct twl_regulator {
- const char *name;
- uint8_t subdev;
- uint8_t regbase;
-
- uint16_t fixedvoltage;
-
- const uint16_t *voltages;
- uint32_t num_voltages;
-};
-
-#define TWL_REGULATOR_ADJUSTABLE(name, subdev, reg, voltages) \
- { name, subdev, reg, 0, voltages, (sizeof(voltages)/sizeof(voltages[0])) }
-#define TWL_REGULATOR_FIXED(name, subdev, reg, voltage) \
- { name, subdev, reg, voltage, NULL, 0 }
-
-static const struct twl_regulator twl4030_regulators[] = {
- TWL_REGULATOR_ADJUSTABLE("vaux1", 0, 0x17, twl4030_vaux1_voltages),
- TWL_REGULATOR_ADJUSTABLE("vaux2", 0, 0x1B, twl4030_vaux2_voltages),
- TWL_REGULATOR_ADJUSTABLE("vaux3", 0, 0x1F, twl4030_vaux3_voltages),
- TWL_REGULATOR_ADJUSTABLE("vaux4", 0, 0x23, twl4030_vaux4_voltages),
- TWL_REGULATOR_ADJUSTABLE("vmmc1", 0, 0x27, twl4030_vmmc1_voltages),
- TWL_REGULATOR_ADJUSTABLE("vmmc2", 0, 0x2B, twl4030_vmmc2_voltages),
- TWL_REGULATOR_ADJUSTABLE("vpll1", 0, 0x2F, twl4030_vpll1_voltages),
- TWL_REGULATOR_ADJUSTABLE("vpll2", 0, 0x33, twl4030_vpll2_voltages),
- TWL_REGULATOR_ADJUSTABLE("vsim", 0, 0x37, twl4030_vsim_voltages),
- TWL_REGULATOR_ADJUSTABLE("vdac", 0, 0x3B, twl4030_vdac_voltages),
- TWL_REGULATOR_ADJUSTABLE("vintana2", 0, 0x43, twl4030_vintana2_voltages),
- TWL_REGULATOR_FIXED("vintana1", 0, 0x3F, 1500),
- TWL_REGULATOR_FIXED("vintdig", 0, 0x47, 1500),
- TWL_REGULATOR_FIXED("vusb1v5", 0, 0x71, 1500),
- TWL_REGULATOR_FIXED("vusb1v8", 0, 0x74, 1800),
- TWL_REGULATOR_FIXED("vusb3v1", 0, 0x77, 3100),
- { NULL, 0, 0x00, 0, NULL, 0 }
-};
-
-static const struct twl_regulator twl6030_regulators[] = {
- TWL_REGULATOR_ADJUSTABLE("vaux1", 0, 0x84, twl6030_voltages),
- TWL_REGULATOR_ADJUSTABLE("vaux2", 0, 0x89, twl6030_voltages),
- TWL_REGULATOR_ADJUSTABLE("vaux3", 0, 0x8C, twl6030_voltages),
- TWL_REGULATOR_ADJUSTABLE("vmmc", 0, 0x98, twl6030_voltages),
- TWL_REGULATOR_ADJUSTABLE("vpp", 0, 0x9C, twl6030_voltages),
- TWL_REGULATOR_ADJUSTABLE("vusim", 0, 0xA4, twl6030_voltages),
- TWL_REGULATOR_FIXED("vmem", 0, 0x64, 1800),
- TWL_REGULATOR_FIXED("vusb", 0, 0xA0, 3300),
- TWL_REGULATOR_FIXED("v1v8", 0, 0x46, 1800),
- TWL_REGULATOR_FIXED("v2v1", 0, 0x4C, 2100),
- TWL_REGULATOR_FIXED("v1v29", 0, 0x40, 1290),
- TWL_REGULATOR_FIXED("vcxio", 0, 0x90, 1800),
- TWL_REGULATOR_FIXED("vdac", 0, 0x94, 1800),
- TWL_REGULATOR_FIXED("vana", 0, 0x80, 2100),
- { NULL, 0, 0x00, 0, NULL, 0 }
-};
-
-#define TWL_VREG_MAX_NAMELEN 32
-
-struct twl_regulator_entry {
- LIST_ENTRY(twl_regulator_entry) entries;
- char name[TWL_VREG_MAX_NAMELEN];
- struct sysctl_oid *oid;
- uint8_t sub_dev; /* TWL sub-device group */
- uint8_t reg_off; /* base register offset for the LDO */
- uint16_t fixed_voltage; /* the (milli)voltage if LDO is fixed */
- const uint16_t *supp_voltages; /* pointer to an array of possible voltages */
- uint32_t num_supp_voltages; /* the number of supplied voltages */
-};
-
-struct twl_vreg_softc {
- device_t sc_dev;
- device_t sc_pdev;
- struct sx sc_sx;
-
- struct intr_config_hook sc_init_hook;
- LIST_HEAD(twl_regulator_list, twl_regulator_entry) sc_vreg_list;
-};
-
-#define TWL_VREG_XLOCK(_sc) sx_xlock(&(_sc)->sc_sx)
-#define TWL_VREG_XUNLOCK(_sc) sx_xunlock(&(_sc)->sc_sx)
-#define TWL_VREG_SLOCK(_sc) sx_slock(&(_sc)->sc_sx)
-#define TWL_VREG_SUNLOCK(_sc) sx_sunlock(&(_sc)->sc_sx)
-#define TWL_VREG_LOCK_INIT(_sc) sx_init(&(_sc)->sc_sx, "twl_vreg")
-#define TWL_VREG_LOCK_DESTROY(_sc) sx_destroy(&(_sc)->sc_sx);
-
-#define TWL_VREG_ASSERT_LOCKED(_sc) sx_assert(&(_sc)->sc_sx, SA_LOCKED);
-
-#define TWL_VREG_LOCK_UPGRADE(_sc) \
- do { \
- while (!sx_try_upgrade(&(_sc)->sc_sx)) \
- pause("twl_vreg_ex", (hz / 100)); \
- } while(0)
-#define TWL_VREG_LOCK_DOWNGRADE(_sc) sx_downgrade(&(_sc)->sc_sx);
-
-/**
- * twl_vreg_read_1 - read single register from the TWL device
- * twl_vreg_write_1 - write a single register in the TWL device
- * @sc: device context
- * @clk: the clock device we're reading from / writing to
- * @off: offset within the clock's register set
- * @val: the value to write or a pointer to a variable to store the result
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static inline int
-twl_vreg_read_1(struct twl_vreg_softc *sc, struct twl_regulator_entry *regulator,
- uint8_t off, uint8_t *val)
-{
- return (twl_read(sc->sc_pdev, regulator->sub_dev,
- regulator->reg_off + off, val, 1));
-}
-
-static inline int
-twl_vreg_write_1(struct twl_vreg_softc *sc, struct twl_regulator_entry *regulator,
- uint8_t off, uint8_t val)
-{
- return (twl_write(sc->sc_pdev, regulator->sub_dev,
- regulator->reg_off + off, &val, 1));
-}
-
-/**
- * twl_millivolt_to_vsel - gets the vsel bit value to write into the register
- * for a desired voltage and regulator
- * @sc: the device soft context
- * @regulator: pointer to the regulator device
- * @millivolts: the millivolts to find the bit value for
- * @vsel: upon return will contain the corresponding register value
- *
- * Accepts a (milli)voltage value and tries to find the closest match to the
- * actual supported voltages for the given regulator. If a match is found
- * within 100mv of the target, @vsel is written with the match and 0 is
- * returned. If no voltage match is found the function returns an non-zero
- * value.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static int
-twl_vreg_millivolt_to_vsel(struct twl_vreg_softc *sc,
- struct twl_regulator_entry *regulator, int millivolts, uint8_t *vsel)
-{
- int delta, smallest_delta;
- unsigned i, closest_idx;
-
- TWL_VREG_ASSERT_LOCKED(sc);
-
- if (regulator->supp_voltages == NULL)
- return (EINVAL);
-
- /* Loop over the support voltages and try and find the closest match */
- closest_idx = 0;
- smallest_delta = 0x7fffffff;
- for (i = 0; i < regulator->num_supp_voltages; i++) {
- /* Ignore undefined values */
- if (regulator->supp_voltages[i] == UNDF)
- continue;
-
- /* Calculate the difference */
- delta = millivolts - (int)regulator->supp_voltages[i];
- if (abs(delta) < smallest_delta) {
- smallest_delta = abs(delta);
- closest_idx = i;
- }
- }
-
- /* Check we got a voltage that was within 100mv of the actual target, this
- * is just a value I picked out of thin air.
- */
- if ((smallest_delta > 100) && (closest_idx < 0x100))
- return (EINVAL);
-
- *vsel = closest_idx;
- return (0);
-}
-
-/**
- * twl_vreg_is_regulator_enabled - returns the enabled status of the regulator
- * @sc: the device soft context
- * @regulator: pointer to the regulator device
- * @enabled: stores the enabled status, zero disabled, non-zero enabled
- *
- * LOCKING:
- * On entry expects the TWL VREG lock to be held. Will upgrade the lock to
- * exclusive if not already but, if so, it will be downgraded again before
- * returning.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static int
-twl_vreg_is_regulator_enabled(struct twl_vreg_softc *sc,
- struct twl_regulator_entry *regulator, int *enabled)
-{
- int err;
- uint8_t grp;
- uint8_t state;
- int xlocked;
-
- if (enabled == NULL)
- return (EINVAL);
-
- TWL_VREG_ASSERT_LOCKED(sc);
-
- xlocked = sx_xlocked(&sc->sc_sx);
- if (!xlocked)
- TWL_VREG_LOCK_UPGRADE(sc);
-
- /* The status reading is different for the different devices */
- if (twl_is_4030(sc->sc_pdev)) {
- err = twl_vreg_read_1(sc, regulator, TWL_VREG_GRP, &state);
- if (err)
- goto done;
-
- *enabled = (state & TWL4030_P1_GRP);
-
- } else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev)) {
- /* Check the regulator is in the application group */
- if (twl_is_6030(sc->sc_pdev)) {
- err = twl_vreg_read_1(sc, regulator, TWL_VREG_GRP, &grp);
- if (err)
- goto done;
-
- if (!(grp & TWL6030_P1_GRP)) {
- *enabled = 0; /* disabled */
- goto done;
- }
- }
-
- /* Read the application mode state and verify it's ON */
- err = twl_vreg_read_1(sc, regulator, TWL_VREG_STATE, &state);
- if (err)
- goto done;
-
- *enabled = ((state & 0x0C) == 0x04);
-
- } else {
- err = EINVAL;
- }
-
-done:
- if (!xlocked)
- TWL_VREG_LOCK_DOWNGRADE(sc);
-
- return (err);
-}
-
-/**
- * twl_vreg_disable_regulator - disables a voltage regulator
- * @sc: the device soft context
- * @regulator: pointer to the regulator device
- *
- * Disables the regulator which will stop the output drivers.
- *
- * LOCKING:
- * On entry expects the TWL VREG lock to be held. Will upgrade the lock to
- * exclusive if not already but, if so, it will be downgraded again before
- * returning.
- *
- * RETURNS:
- * Zero on success or a positive error code on failure.
- */
-static int
-twl_vreg_disable_regulator(struct twl_vreg_softc *sc,
- struct twl_regulator_entry *regulator)
-{
- int err = 0;
- uint8_t grp;
- int xlocked;
-
- TWL_VREG_ASSERT_LOCKED(sc);
-
- xlocked = sx_xlocked(&sc->sc_sx);
- if (!xlocked)
- TWL_VREG_LOCK_UPGRADE(sc);
-
- if (twl_is_4030(sc->sc_pdev)) {
- /* Read the regulator CFG_GRP register */
- err = twl_vreg_read_1(sc, regulator, TWL_VREG_GRP, &grp);
- if (err)
- goto done;
-
- /* On the TWL4030 we just need to remove the regulator from all the
- * power groups.
- */
- grp &= ~(TWL4030_P1_GRP | TWL4030_P2_GRP | TWL4030_P3_GRP);
- err = twl_vreg_write_1(sc, regulator, TWL_VREG_GRP, grp);
-
- } else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev)) {
- /* On TWL6030 we need to make sure we disable power for all groups */
- if (twl_is_6030(sc->sc_pdev))
- grp = TWL6030_P1_GRP | TWL6030_P2_GRP | TWL6030_P3_GRP;
- else
- grp = 0x00;
-
- /* Write the resource state to "OFF" */
- err = twl_vreg_write_1(sc, regulator, TWL_VREG_STATE, (grp << 5));
- }
-
-done:
- if (!xlocked)
- TWL_VREG_LOCK_DOWNGRADE(sc);
-
- return (err);
-}
-
-/**
- * twl_vreg_enable_regulator - enables the voltage regulator
- * @sc: the device soft context
- * @regulator: pointer to the regulator device
- *
- * Enables the regulator which will enable the voltage out at the currently
- * set voltage. Set the voltage before calling this function to avoid
- * driving the voltage too high/low by mistake.
- *
- * LOCKING:
- * On entry expects the TWL VREG lock to be held. Will upgrade the lock to
- * exclusive if not already but, if so, it will be downgraded again before
- * returning.
- *
- * RETURNS:
- * Zero on success or a positive error code on failure.
- */
-static int
-twl_vreg_enable_regulator(struct twl_vreg_softc *sc,
- struct twl_regulator_entry *regulator)
-{
- int err;
- uint8_t grp;
- int xlocked;
-
- TWL_VREG_ASSERT_LOCKED(sc);
-
- xlocked = sx_xlocked(&sc->sc_sx);
- if (!xlocked)
- TWL_VREG_LOCK_UPGRADE(sc);
-
- err = twl_vreg_read_1(sc, regulator, TWL_VREG_GRP, &grp);
- if (err)
- goto done;
-
- /* Enable the regulator by ensuring it's in the application power group
- * and is in the "on" state.
- */
- if (twl_is_4030(sc->sc_pdev)) {
- /* On the TWL4030 we just need to ensure the regulator is in the right
- * power domain, don't need to turn on explicitly like TWL6030.
- */
- grp |= TWL4030_P1_GRP;
- err = twl_vreg_write_1(sc, regulator, TWL_VREG_GRP, grp);
-
- } else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev)) {
- if (twl_is_6030(sc->sc_pdev) && !(grp & TWL6030_P1_GRP)) {
- grp |= TWL6030_P1_GRP;
- err = twl_vreg_write_1(sc, regulator, TWL_VREG_GRP, grp);
- if (err)
- goto done;
- }
-
- /* Write the resource state to "ON" */
- err = twl_vreg_write_1(sc, regulator, TWL_VREG_STATE, (grp << 5) | 0x01);
- }
-
-done:
- if (!xlocked)
- TWL_VREG_LOCK_DOWNGRADE(sc);
-
- return (err);
-}
-
-/**
- * twl_vreg_write_regulator_voltage - sets the voltage level on a regulator
- * @sc: the device soft context
- * @regulator: pointer to the regulator structure
- * @millivolts: the voltage to set
- *
- * Sets the voltage output on a given regulator, if the regulator is not
- * enabled, it will be enabled.
- *
- * LOCKING:
- * On entry expects the TWL VREG lock to be held, may upgrade the lock to
- * exclusive but if so it will be downgraded once again before returning.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static int
-twl_vreg_write_regulator_voltage(struct twl_vreg_softc *sc,
- struct twl_regulator_entry *regulator, int millivolts)
-{
- int err;
- uint8_t vsel;
- int xlocked;
-
- TWL_VREG_ASSERT_LOCKED(sc);
-
- /* If millivolts is zero then we simply disable the output */
- if (millivolts == 0)
- return (twl_vreg_disable_regulator(sc, regulator));
-
- /* If the regulator has a fixed voltage then check the setting matches
- * and simply enable.
- */
- if (regulator->supp_voltages == NULL || regulator->num_supp_voltages == 0) {
- if (millivolts != regulator->fixed_voltage)
- return (EINVAL);
-
- return (twl_vreg_enable_regulator(sc, regulator));
- }
-
- /* Get the VSEL value for the given voltage */
- err = twl_vreg_millivolt_to_vsel(sc, regulator, millivolts, &vsel);
- if (err)
- return (err);
-
- /* Need to upgrade because writing the voltage and enabling should be atomic */
- xlocked = sx_xlocked(&sc->sc_sx);
- if (!xlocked)
- TWL_VREG_LOCK_UPGRADE(sc);
-
- /* Set voltage and enable (atomically) */
- err = twl_vreg_write_1(sc, regulator, TWL_VREG_VSEL, (vsel & 0x1f));
- if (!err) {
- err = twl_vreg_enable_regulator(sc, regulator);
- }
-
- if (!xlocked)
- TWL_VREG_LOCK_DOWNGRADE(sc);
-
- if ((twl_vreg_debug > 1) && !err)
- device_printf(sc->sc_dev, "%s : setting voltage to %dmV (vsel: 0x%x)\n",
- regulator->name, millivolts, vsel);
-
- return (err);
-}
-
-/**
- * twl_vreg_read_regulator_voltage - reads the voltage on a given regulator
- * @sc: the device soft context
- * @regulator: pointer to the regulator structure
- * @millivolts: upon return will contain the voltage on the regulator
- *
- * LOCKING:
- * On entry expects the TWL VREG lock to be held. It will upgrade the lock to
- * exclusive if not already, but if so, it will be downgraded again before
- * returning.
- *
- * RETURNS:
- * Zero on success, or otherwise an error code.
- */
-static int
-twl_vreg_read_regulator_voltage(struct twl_vreg_softc *sc,
- struct twl_regulator_entry *regulator, int *millivolts)
-{
- int err;
- int en = 0;
- int xlocked;
- uint8_t vsel;
-
- TWL_VREG_ASSERT_LOCKED(sc);
-
- /* Need to upgrade the lock because checking enabled state and voltage
- * should be atomic.
- */
- xlocked = sx_xlocked(&sc->sc_sx);
- if (!xlocked)
- TWL_VREG_LOCK_UPGRADE(sc);
-
- /* Check if the regulator is currently enabled */
- err = twl_vreg_is_regulator_enabled(sc, regulator, &en);
- if (err)
- goto done;
-
- *millivolts = 0;
- if (!en)
- goto done;
-
- /* Not all voltages are adjustable */
- if (regulator->supp_voltages == NULL || !regulator->num_supp_voltages) {
- *millivolts = regulator->fixed_voltage;
- goto done;
- }
-
- /* For variable voltages read the voltage register */
- err = twl_vreg_read_1(sc, regulator, TWL_VREG_VSEL, &vsel);
- if (err)
- goto done;
-
- vsel &= (regulator->num_supp_voltages - 1);
- if (regulator->supp_voltages[vsel] == UNDF) {
- err = EINVAL;
- goto done;
- }
-
- *millivolts = regulator->supp_voltages[vsel];
-
-done:
- if (!xlocked)
- TWL_VREG_LOCK_DOWNGRADE(sc);
-
- if ((twl_vreg_debug > 1) && !err)
- device_printf(sc->sc_dev, "%s : reading voltage is %dmV (vsel: 0x%x)\n",
- regulator->name, *millivolts, vsel);
-
- return (err);
-}
-
-/**
- * twl_vreg_get_voltage - public interface to read the voltage on a regulator
- * @dev: TWL VREG device
- * @name: the name of the regulator to read the voltage of
- * @millivolts: pointer to an integer that upon return will contain the mV
- *
- * If the regulator is disabled the function will set the @millivolts to zero.
- *
- * LOCKING:
- * Internally the function takes and releases the TWL VREG lock.
- *
- * RETURNS:
- * Zero on success or a negative error code on failure.
- */
-int
-twl_vreg_get_voltage(device_t dev, const char *name, int *millivolts)
-{
- struct twl_vreg_softc *sc;
- struct twl_regulator_entry *regulator;
- int err = EINVAL;
-
- if (millivolts == NULL)
- return (EINVAL);
-
- sc = device_get_softc(dev);
-
- TWL_VREG_SLOCK(sc);
-
- LIST_FOREACH(regulator, &sc->sc_vreg_list, entries) {
- if (strcmp(regulator->name, name) == 0) {
- err = twl_vreg_read_regulator_voltage(sc, regulator, millivolts);
- break;
- }
- }
-
- TWL_VREG_SUNLOCK(sc);
-
- return (err);
-}
-
-/**
- * twl_vreg_set_voltage - public interface to write the voltage on a regulator
- * @dev: TWL VREG device
- * @name: the name of the regulator to read the voltage of
- * @millivolts: the voltage to set in millivolts
- *
- * Sets the output voltage on a given regulator. If the regulator is a fixed
- * voltage reg then the @millivolts value should match the fixed voltage. If
- * a variable regulator then the @millivolt value must fit within the max/min
- * range of the given regulator.
- *
- * LOCKING:
- * Internally the function takes and releases the TWL VREG lock.
- *
- * RETURNS:
- * Zero on success or a negative error code on failure.
- */
-int
-twl_vreg_set_voltage(device_t dev, const char *name, int millivolts)
-{
- struct twl_vreg_softc *sc;
- struct twl_regulator_entry *regulator;
- int err = EINVAL;
-
- sc = device_get_softc(dev);
-
- TWL_VREG_SLOCK(sc);
-
- LIST_FOREACH(regulator, &sc->sc_vreg_list, entries) {
- if (strcmp(regulator->name, name) == 0) {
- err = twl_vreg_write_regulator_voltage(sc, regulator, millivolts);
- break;
- }
- }
-
- TWL_VREG_SUNLOCK(sc);
-
- return (err);
-}
-
-/**
- * twl_sysctl_voltage - reads or writes the voltage for a regulator
- * @SYSCTL_HANDLER_ARGS: arguments for the callback
- *
- * Callback for the sysctl entry for the regulator, simply used to return
- * the voltage on a particular regulator.
- *
- * LOCKING:
- * Takes the TWL_VREG shared lock internally.
- *
- * RETURNS:
- * Zero on success or an error code on failure.
- */
-static int
-twl_vreg_sysctl_voltage(SYSCTL_HANDLER_ARGS)
-{
- struct twl_vreg_softc *sc = (struct twl_vreg_softc*)arg1;
- struct twl_regulator_entry *regulator;
- int voltage;
- int found = 0;
-
- TWL_VREG_SLOCK(sc);
-
- /* Find the regulator with the matching name */
- LIST_FOREACH(regulator, &sc->sc_vreg_list, entries) {
- if (strcmp(regulator->name, oidp->oid_name) == 0) {
- found = 1;
- break;
- }
- }
-
- /* Sanity check that we found the regulator */
- if (!found) {
- TWL_VREG_SUNLOCK(sc);
- return (EINVAL);
- }
-
- twl_vreg_read_regulator_voltage(sc, regulator, &voltage);
-
- TWL_VREG_SUNLOCK(sc);
-
- return sysctl_handle_int(oidp, &voltage, 0, req);
-}
-
-/**
- * twl_add_regulator - adds single voltage regulator sysctls for the device
- * @sc: device soft context
- * @name: the name of the regulator
- * @nsub: the number of the subdevice
- * @regbase: the base address of the voltage regulator registers
- * @fixed_voltage: if a fixed voltage regulator this defines it's voltage
- * @voltages: if a variable voltage regulator, an array of possible voltages
- * @num_voltages: the number of entries @voltages
- *
- * Adds a voltage regulator to the device and also a sysctl interface for the
- * regulator.
- *
- * LOCKING:
- * The TWL_VEG exclusive lock must be held while this function is called.
- *
- * RETURNS:
- * Pointer to the new regulator entry on success, otherwise on failure NULL.
- */
-static struct twl_regulator_entry*
-twl_vreg_add_regulator(struct twl_vreg_softc *sc, const char *name,
- uint8_t nsub, uint8_t regbase, uint16_t fixed_voltage,
- const uint16_t *voltages, uint32_t num_voltages)
-{
- struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
- struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
- struct twl_regulator_entry *new;
-
- new = malloc(sizeof(struct twl_regulator_entry), M_DEVBUF, M_NOWAIT | M_ZERO);
- if (new == NULL)
- return (NULL);
-
- strncpy(new->name, name, TWL_VREG_MAX_NAMELEN);
- new->name[TWL_VREG_MAX_NAMELEN - 1] = '\0';
-
- new->sub_dev = nsub;
- new->reg_off = regbase;
-
- new->fixed_voltage = fixed_voltage;
-
- new->supp_voltages = voltages;
- new->num_supp_voltages = num_voltages;
-
- /* Add a sysctl entry for the voltage */
- new->oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, name,
- CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
- twl_vreg_sysctl_voltage, "I", "voltage regulator");
-
- /* Finally add the regulator to list of supported regulators */
- LIST_INSERT_HEAD(&sc->sc_vreg_list, new, entries);
-
- return (new);
-}
-
-/**
- * twl_vreg_add_regulators - adds any voltage regulators to the device
- * @sc: device soft context
- * @chip: the name of the chip used in the hints
- * @regulators: the list of possible voltage regulators
- *
- * Loops over the list of regulators and matches up with the FDT values,
- * adjusting the actual voltage based on the supplied values.
- *
- * LOCKING:
- * The TWL_VEG exclusive lock must be held while this function is called.
- *
- * RETURNS:
- * Always returns 0.
- */
-static int
-twl_vreg_add_regulators(struct twl_vreg_softc *sc,
- const struct twl_regulator *regulators)
-{
- int err;
- int millivolts;
- const struct twl_regulator *walker;
- struct twl_regulator_entry *entry;
- phandle_t child;
- char rnames[256];
- char *name, *voltage;
- int len = 0, prop_len;
-
- /* Add the regulators from the list */
- walker = &regulators[0];
- while (walker->name != NULL) {
- /* Add the regulator to the list */
- entry = twl_vreg_add_regulator(sc, walker->name, walker->subdev,
- walker->regbase, walker->fixedvoltage,
- walker->voltages, walker->num_voltages);
- if (entry == NULL)
- continue;
-
- walker++;
- }
-
- /* Check if the FDT is telling us to set any voltages */
- child = ofw_bus_get_node(sc->sc_pdev);
- if (child) {
- prop_len = OF_getprop(child, "voltage-regulators", rnames, sizeof(rnames));
- while (len < prop_len) {
- name = rnames + len;
- len += strlen(name) + 1;
- if ((len >= prop_len) || (name[0] == '\0'))
- break;
-
- voltage = rnames + len;
- len += strlen(voltage) + 1;
- if (voltage[0] == '\0')
- break;
-
- millivolts = strtoul(voltage, NULL, 0);
-
- LIST_FOREACH(entry, &sc->sc_vreg_list, entries) {
- if (strcmp(entry->name, name) == 0) {
- twl_vreg_write_regulator_voltage(sc, entry, millivolts);
- break;
- }
- }
- }
- }
-
- if (twl_vreg_debug) {
- LIST_FOREACH(entry, &sc->sc_vreg_list, entries) {
- err = twl_vreg_read_regulator_voltage(sc, entry, &millivolts);
- if (!err)
- device_printf(sc->sc_dev, "%s : %d mV\n", entry->name, millivolts);
- }
- }
-
- return (0);
-}
-
-/**
- * twl_vreg_init - initialises the list of regulators
- * @dev: the twl_vreg device
- *
- * This function is called as an intrhook once interrupts have been enabled,
- * this is done so that the driver has the option to enable/disable or set
- * the voltage level based on settings providied in the FDT.
- *
- * LOCKING:
- * Takes the exclusive lock in the function.
- */
-static void
-twl_vreg_init(void *dev)
-{
- struct twl_vreg_softc *sc;
-
- sc = device_get_softc((device_t)dev);
-
- TWL_VREG_XLOCK(sc);
-
- if (twl_is_4030(sc->sc_pdev))
- twl_vreg_add_regulators(sc, twl4030_regulators);
- else if (twl_is_6030(sc->sc_pdev) || twl_is_6025(sc->sc_pdev))
- twl_vreg_add_regulators(sc, twl6030_regulators);
-
- TWL_VREG_XUNLOCK(sc);
-
- config_intrhook_disestablish(&sc->sc_init_hook);
-}
-
-static int
-twl_vreg_probe(device_t dev)
-{
- if (twl_is_4030(device_get_parent(dev)))
- device_set_desc(dev, "TI TWL4030 PMIC Voltage Regulators");
- else if (twl_is_6025(device_get_parent(dev)) ||
- twl_is_6030(device_get_parent(dev)))
- device_set_desc(dev, "TI TWL6025/TWL6030 PMIC Voltage Regulators");
- else
- return (ENXIO);
-
- return (0);
-}
-
-static int
-twl_vreg_attach(device_t dev)
-{
- struct twl_vreg_softc *sc;
-
- sc = device_get_softc(dev);
- sc->sc_dev = dev;
- sc->sc_pdev = device_get_parent(dev);
-
- TWL_VREG_LOCK_INIT(sc);
-
- LIST_INIT(&sc->sc_vreg_list);
-
- /* We have to wait until interrupts are enabled. I2C read and write
- * only works if the interrupts are available.
- */
- sc->sc_init_hook.ich_func = twl_vreg_init;
- sc->sc_init_hook.ich_arg = dev;
-
- if (config_intrhook_establish(&sc->sc_init_hook) != 0)
- return (ENOMEM);
-
- return (0);
-}
-
-static int
-twl_vreg_detach(device_t dev)
-{
- struct twl_vreg_softc *sc;
- struct twl_regulator_entry *regulator;
- struct twl_regulator_entry *tmp;
-
- sc = device_get_softc(dev);
-
- /* Take the lock and free all the added regulators */
- TWL_VREG_XLOCK(sc);
-
- LIST_FOREACH_SAFE(regulator, &sc->sc_vreg_list, entries, tmp) {
- LIST_REMOVE(regulator, entries);
- sysctl_remove_oid(regulator->oid, 1, 0);
- free(regulator, M_DEVBUF);
- }
-
- TWL_VREG_XUNLOCK(sc);
-
- TWL_VREG_LOCK_DESTROY(sc);
-
- return (0);
-}
-
-static device_method_t twl_vreg_methods[] = {
- DEVMETHOD(device_probe, twl_vreg_probe),
- DEVMETHOD(device_attach, twl_vreg_attach),
- DEVMETHOD(device_detach, twl_vreg_detach),
-
- {0, 0},
-};
-
-static driver_t twl_vreg_driver = {
- "twl_vreg",
- twl_vreg_methods,
- sizeof(struct twl_vreg_softc),
-};
-
-DRIVER_MODULE(twl_vreg, twl, twl_vreg_driver, 0, 0);
-MODULE_VERSION(twl_vreg, 1);
diff --git a/sys/arm/ti/usb/omap_ehci.c b/sys/arm/ti/usb/omap_ehci.c
deleted file mode 100644
--- a/sys/arm/ti/usb/omap_ehci.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/conf.h>
-#include <sys/kernel.h>
-#include <sys/rman.h>
-#include <sys/module.h>
-#include <sys/proc.h>
-#include <sys/condvar.h>
-
-#include <dev/fdt/simplebus.h>
-#include <dev/fdt/fdt_common.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <dev/usb/usb.h>
-#include <dev/usb/usbdi.h>
-
-#include <dev/usb/usb_core.h>
-#include <dev/usb/usb_busdma.h>
-#include <dev/usb/usb_process.h>
-#include <dev/usb/usb_util.h>
-
-#include <dev/usb/usb_controller.h>
-#include <dev/usb/usb_bus.h>
-#include <dev/usb/controller/ehci.h>
-#include <dev/usb/controller/ehcireg.h>
-
-#include <machine/bus.h>
-
-#include <arm/ti/usb/omap_usb.h>
-
-#include <arm/ti/omap4/pandaboard/pandaboard.h>
-
-/* EHCI */
-#define OMAP_USBHOST_HCCAPBASE 0x0000
-#define OMAP_USBHOST_HCSPARAMS 0x0004
-#define OMAP_USBHOST_HCCPARAMS 0x0008
-#define OMAP_USBHOST_USBCMD 0x0010
-#define OMAP_USBHOST_USBSTS 0x0014
-#define OMAP_USBHOST_USBINTR 0x0018
-#define OMAP_USBHOST_FRINDEX 0x001C
-#define OMAP_USBHOST_CTRLDSSEGMENT 0x0020
-#define OMAP_USBHOST_PERIODICLISTBASE 0x0024
-#define OMAP_USBHOST_ASYNCLISTADDR 0x0028
-#define OMAP_USBHOST_CONFIGFLAG 0x0050
-#define OMAP_USBHOST_PORTSC(i) (0x0054 + (0x04 * (i)))
-#define OMAP_USBHOST_INSNREG00 0x0090
-#define OMAP_USBHOST_INSNREG01 0x0094
-#define OMAP_USBHOST_INSNREG02 0x0098
-#define OMAP_USBHOST_INSNREG03 0x009C
-#define OMAP_USBHOST_INSNREG04 0x00A0
-#define OMAP_USBHOST_INSNREG05_UTMI 0x00A4
-#define OMAP_USBHOST_INSNREG05_ULPI 0x00A4
-#define OMAP_USBHOST_INSNREG06 0x00A8
-#define OMAP_USBHOST_INSNREG07 0x00AC
-#define OMAP_USBHOST_INSNREG08 0x00B0
-
-#define OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND (1 << 5)
-
-#define OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT 31
-#define OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT 24
-#define OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT 22
-#define OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT 16
-#define OMAP_USBHOST_INSNREG05_ULPI_EXTREGADD_SHIFT 8
-#define OMAP_USBHOST_INSNREG05_ULPI_WRDATA_SHIFT 0
-
-#define ULPI_FUNC_CTRL_RESET (1 << 5)
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * Macros for Set and Clear
- * See ULPI 1.1 specification to find the registers with Set and Clear offsets
- */
-#define ULPI_SET(a) (a + 1)
-#define ULPI_CLR(a) (a + 2)
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * Register Map
- */
-#define ULPI_VENDOR_ID_LOW 0x00
-#define ULPI_VENDOR_ID_HIGH 0x01
-#define ULPI_PRODUCT_ID_LOW 0x02
-#define ULPI_PRODUCT_ID_HIGH 0x03
-#define ULPI_FUNC_CTRL 0x04
-#define ULPI_IFC_CTRL 0x07
-#define ULPI_OTG_CTRL 0x0a
-#define ULPI_USB_INT_EN_RISE 0x0d
-#define ULPI_USB_INT_EN_FALL 0x10
-#define ULPI_USB_INT_STS 0x13
-#define ULPI_USB_INT_LATCH 0x14
-#define ULPI_DEBUG 0x15
-#define ULPI_SCRATCH 0x16
-
-#define OMAP_EHCI_HC_DEVSTR "TI OMAP USB 2.0 controller"
-
-struct omap_ehci_softc {
- ehci_softc_t base; /* storage for EHCI code */
- device_t sc_dev;
-};
-
-static device_attach_t omap_ehci_attach;
-static device_detach_t omap_ehci_detach;
-
-/**
- * omap_ehci_read_4 - read a 32-bit value from the EHCI registers
- * omap_ehci_write_4 - write a 32-bit value from the EHCI registers
- * @sc: omap ehci device context
- * @off: byte offset within the register set to read from
- * @val: the value to write into the register
- *
- *
- * LOCKING:
- * None
- *
- * RETURNS:
- * nothing in case of write function, if read function returns the value read.
- */
-static inline uint32_t
-omap_ehci_read_4(struct omap_ehci_softc *sc, bus_size_t off)
-{
- return (bus_read_4(sc->base.sc_io_res, off));
-}
-
-static inline void
-omap_ehci_write_4(struct omap_ehci_softc *sc, bus_size_t off, uint32_t val)
-{
- bus_write_4(sc->base.sc_io_res, off, val);
-}
-
-/**
- * omap_ehci_soft_phy_reset - resets the phy using the reset command
- * @isc: omap ehci device context
- * @port: port to send the reset over
- *
- *
- * LOCKING:
- * none
- *
- * RETURNS:
- * nothing
- */
-static void
-omap_ehci_soft_phy_reset(struct omap_ehci_softc *isc, unsigned int port)
-{
- unsigned long timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
- uint32_t reg;
-
- reg = ULPI_FUNC_CTRL_RESET
- /* FUNCTION_CTRL_SET register */
- | (ULPI_SET(ULPI_FUNC_CTRL) << OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT)
- /* Write */
- | (2 << OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT)
- /* PORTn */
- | ((port + 1) << OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT)
- /* start ULPI access*/
- | (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT);
-
- omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg);
-
- /* Wait for ULPI access completion */
- while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI)
- & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) {
- /* Sleep for a tick */
- pause("USBPHY_RESET", 1);
-
- if (timeout-- == 0) {
- device_printf(isc->sc_dev, "PHY reset operation timed out\n");
- break;
- }
- }
-}
-
-/**
- * omap_ehci_init - initialises the USB host EHCI controller
- * @isc: omap ehci device context
- *
- * This initialisation routine is quite heavily based on the work done by the
- * OMAP Linux team (for which I thank them very much). The init sequence is
- * almost identical, diverging only for the FreeBSD specifics.
- *
- * LOCKING:
- * none
- *
- * RETURNS:
- * 0 on success, a negative error code on failure.
- */
-static int
-omap_ehci_init(struct omap_ehci_softc *isc)
-{
- uint32_t reg = 0;
- int i;
- device_t uhh_dev;
-
- uhh_dev = device_get_parent(isc->sc_dev);
- device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n");
-
- /* Set the interrupt threshold control, it controls the maximum rate at
- * which the host controller issues interrupts. We set it to 1 microframe
- * at startup - the default is 8 mircoframes (equates to 1ms).
- */
- reg = omap_ehci_read_4(isc, OMAP_USBHOST_USBCMD);
- reg &= 0xff00ffff;
- reg |= (1 << 16);
- omap_ehci_write_4(isc, OMAP_USBHOST_USBCMD, reg);
-
- /* Soft reset the PHY using PHY reset command over ULPI */
- for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
- if (omap_usb_port_mode(uhh_dev, i) == EHCI_HCD_OMAP_MODE_PHY)
- omap_ehci_soft_phy_reset(isc, i);
- }
-
- return(0);
-}
-
-/**
- * omap_ehci_probe - starts the given command
- * @dev:
- *
- * Effectively boilerplate EHCI resume code.
- *
- * LOCKING:
- * Caller should be holding the OMAP3_MMC lock.
- *
- * RETURNS:
- * EH_HANDLED or EH_NOT_HANDLED
- */
-static int
-omap_ehci_probe(device_t dev)
-{
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- if (!ofw_bus_is_compatible(dev, "ti,ehci-omap"))
- return (ENXIO);
-
- device_set_desc(dev, OMAP_EHCI_HC_DEVSTR);
-
- return (BUS_PROBE_DEFAULT);
-}
-
-/**
- * omap_ehci_attach - driver entry point, sets up the ECHI controller/driver
- * @dev: the new device handle
- *
- * Sets up bus spaces, interrupt handles, etc for the EHCI controller. It also
- * parses the resource hints and calls omap_ehci_init() to initialise the
- * H/W.
- *
- * LOCKING:
- * none
- *
- * RETURNS:
- * 0 on success or a positive error code on failure.
- */
-static int
-omap_ehci_attach(device_t dev)
-{
- struct omap_ehci_softc *isc = device_get_softc(dev);
- ehci_softc_t *sc = &isc->base;
-#ifdef SOC_OMAP4
- phandle_t root;
-#endif
- int err;
- int rid;
-
-#ifdef SOC_OMAP4
- /*
- * If we're running a Pandaboard, run Pandaboard-specific
- * init code.
- */
- root = OF_finddevice("/");
- if (ofw_bus_node_is_compatible(root, "ti,omap4-panda"))
- pandaboard_usb_hub_init();
-#endif
-
- /* initialise some bus fields */
- sc->sc_bus.parent = dev;
- sc->sc_bus.devices = sc->sc_devices;
- sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
- sc->sc_bus.dma_bits = 32;
-
- sprintf(sc->sc_vendor, "Texas Instruments");
-
- /* save the device */
- isc->sc_dev = dev;
-
- /* get all DMA memory */
- if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev),
- &ehci_iterate_hw_softc)) {
- return (ENOMEM);
- }
-
- /* Allocate resource for the EHCI register set */
- rid = 0;
- sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
- if (!sc->sc_io_res) {
- device_printf(dev, "Error: Could not map EHCI memory\n");
- goto error;
- }
- /* Request an interrupt resource */
- rid = 0;
- sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
- if (sc->sc_irq_res == NULL) {
- device_printf(dev, "Error: could not allocate irq\n");
- goto error;
- }
-
- /* Add this device as a child of the USBus device */
- sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
- if (!sc->sc_bus.bdev) {
- device_printf(dev, "Error: could not add USB device\n");
- goto error;
- }
-
- device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
- device_set_desc(sc->sc_bus.bdev, OMAP_EHCI_HC_DEVSTR);
-
- /* Initialise the ECHI registers */
- err = omap_ehci_init(isc);
- if (err) {
- device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err);
- goto error;
- }
-
- /* Set the tag and size of the register set in the EHCI context */
- sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
- sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
- sc->sc_io_size = rman_get_size(sc->sc_io_res);
-
- /* Setup the interrupt */
- err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
- NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
- if (err) {
- device_printf(dev, "Error: could not setup irq, %d\n", err);
- sc->sc_intr_hdl = NULL;
- goto error;
- }
-
- /* Finally we are ready to kick off the ECHI host controller */
- err = ehci_init(sc);
- if (err == 0) {
- err = device_probe_and_attach(sc->sc_bus.bdev);
- }
- if (err) {
- device_printf(dev, "Error: USB init failed err=%d\n", err);
- goto error;
- }
-
- return (0);
-
-error:
- omap_ehci_detach(dev);
- return (ENXIO);
-}
-
-/**
- * omap_ehci_detach - detach the device and cleanup the driver
- * @dev: device handle
- *
- * Clean-up routine where everything initialised in omap_ehci_attach is
- * freed and cleaned up. This function calls omap_ehci_fini() to shutdown
- * the on-chip module.
- *
- * LOCKING:
- * none
- *
- * RETURNS:
- * Always returns 0 (success).
- */
-static int
-omap_ehci_detach(device_t dev)
-{
- struct omap_ehci_softc *isc = device_get_softc(dev);
- ehci_softc_t *sc = &isc->base;
- int err;
-
- /* during module unload there are lots of children leftover */
- device_delete_children(dev);
-
- /*
- * disable interrupts that might have been switched on in ehci_init
- */
- if (sc->sc_io_res) {
- EWRITE4(sc, EHCI_USBINTR, 0);
- }
-
- if (sc->sc_irq_res && sc->sc_intr_hdl) {
- /*
- * only call ehci_detach() after ehci_init()
- */
- ehci_detach(sc);
-
- err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl);
- if (err)
- device_printf(dev, "Error: could not tear down irq, %d\n", err);
- sc->sc_intr_hdl = NULL;
- }
-
- /* Free the resources stored in the base EHCI handler */
- if (sc->sc_irq_res) {
- bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
- sc->sc_irq_res = NULL;
- }
- if (sc->sc_io_res) {
- bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res);
- sc->sc_io_res = NULL;
- }
-
- return (0);
-}
-
-static device_method_t ehci_methods[] = {
- /* Device interface */
- DEVMETHOD(device_probe, omap_ehci_probe),
- DEVMETHOD(device_attach, omap_ehci_attach),
- DEVMETHOD(device_detach, omap_ehci_detach),
-
- DEVMETHOD(device_suspend, bus_generic_suspend),
- DEVMETHOD(device_resume, bus_generic_resume),
- DEVMETHOD(device_shutdown, bus_generic_shutdown),
-
- /* Bus interface */
- DEVMETHOD(bus_print_child, bus_generic_print_child),
- {0, 0}
-};
-
-static driver_t ehci_driver = {
- "ehci",
- ehci_methods,
- sizeof(struct omap_ehci_softc),
-};
-
-DRIVER_MODULE(omap_ehci, omap_uhh, ehci_driver, 0, 0);
diff --git a/sys/arm/ti/usb/omap_host.c b/sys/arm/ti/usb/omap_host.c
deleted file mode 100644
--- a/sys/arm/ti/usb/omap_host.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*-
- * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
- * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/conf.h>
-#include <sys/kernel.h>
-#include <sys/rman.h>
-#include <sys/module.h>
-
-#include <dev/fdt/simplebus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <machine/bus.h>
-
-#include <arm/ti/ti_sysc.h>
-#include <arm/ti/usb/omap_usb.h>
-
-/*
- * USB Host Module
- */
-
-/* UHH */
-#define OMAP_USBHOST_UHH_REVISION 0x0000
-#define OMAP_USBHOST_UHH_SYSCONFIG 0x0010
-#define OMAP_USBHOST_UHH_SYSSTATUS 0x0014
-#define OMAP_USBHOST_UHH_HOSTCONFIG 0x0040
-#define OMAP_USBHOST_UHH_DEBUG_CSR 0x0044
-
-/* UHH Register Set */
-#define UHH_SYSCONFIG_MIDLEMODE_MASK (3UL << 12)
-#define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY (2UL << 12)
-#define UHH_SYSCONFIG_MIDLEMODE_NOSTANDBY (1UL << 12)
-#define UHH_SYSCONFIG_MIDLEMODE_FORCESTANDBY (0UL << 12)
-#define UHH_SYSCONFIG_CLOCKACTIVITY (1UL << 8)
-#define UHH_SYSCONFIG_SIDLEMODE_MASK (3UL << 3)
-#define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE (2UL << 3)
-#define UHH_SYSCONFIG_SIDLEMODE_NOIDLE (1UL << 3)
-#define UHH_SYSCONFIG_SIDLEMODE_FORCEIDLE (0UL << 3)
-#define UHH_SYSCONFIG_ENAWAKEUP (1UL << 2)
-#define UHH_SYSCONFIG_SOFTRESET (1UL << 1)
-#define UHH_SYSCONFIG_AUTOIDLE (1UL << 0)
-
-#define UHH_HOSTCONFIG_APP_START_CLK (1UL << 31)
-#define UHH_HOSTCONFIG_P3_CONNECT_STATUS (1UL << 10)
-#define UHH_HOSTCONFIG_P2_CONNECT_STATUS (1UL << 9)
-#define UHH_HOSTCONFIG_P1_CONNECT_STATUS (1UL << 8)
-#define UHH_HOSTCONFIG_ENA_INCR_ALIGN (1UL << 5)
-#define UHH_HOSTCONFIG_ENA_INCR16 (1UL << 4)
-#define UHH_HOSTCONFIG_ENA_INCR8 (1UL << 3)
-#define UHH_HOSTCONFIG_ENA_INCR4 (1UL << 2)
-#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN (1UL << 1)
-#define UHH_HOSTCONFIG_P1_ULPI_BYPASS (1UL << 0)
-
-/* The following are on rev2 (OMAP44xx) of the EHCI only */
-#define UHH_SYSCONFIG_IDLEMODE_MASK (3UL << 2)
-#define UHH_SYSCONFIG_IDLEMODE_NOIDLE (1UL << 2)
-#define UHH_SYSCONFIG_STANDBYMODE_MASK (3UL << 4)
-#define UHH_SYSCONFIG_STANDBYMODE_NOSTDBY (1UL << 4)
-
-#define UHH_HOSTCONFIG_P1_MODE_MASK (3UL << 16)
-#define UHH_HOSTCONFIG_P1_MODE_ULPI_PHY (0UL << 16)
-#define UHH_HOSTCONFIG_P1_MODE_UTMI_PHY (1UL << 16)
-#define UHH_HOSTCONFIG_P1_MODE_HSIC (3UL << 16)
-#define UHH_HOSTCONFIG_P2_MODE_MASK (3UL << 18)
-#define UHH_HOSTCONFIG_P2_MODE_ULPI_PHY (0UL << 18)
-#define UHH_HOSTCONFIG_P2_MODE_UTMI_PHY (1UL << 18)
-#define UHH_HOSTCONFIG_P2_MODE_HSIC (3UL << 18)
-
-/*
- * Values of UHH_REVISION - Note: these are not given in the TRM but taken
- * from the linux OMAP EHCI driver (thanks guys). It has been verified on
- * a Panda and Beagle board.
- */
-#define OMAP_UHH_REV1 0x00000010 /* OMAP3 */
-#define OMAP_UHH_REV2 0x50700100 /* OMAP4 */
-
-struct omap_uhh_softc {
- struct simplebus_softc simplebus_sc;
- device_t sc_dev;
-
- /* UHH register set */
- struct resource* uhh_mem_res;
-
- /* The revision of the HS USB HOST read from UHH_REVISION */
- uint32_t uhh_rev;
-
- /* The following details are provided by conf hints */
- int port_mode[3];
-};
-
-static device_attach_t omap_uhh_attach;
-static device_detach_t omap_uhh_detach;
-
-static inline uint32_t
-omap_uhh_read_4(struct omap_uhh_softc *sc, bus_size_t off)
-{
- return bus_read_4(sc->uhh_mem_res, off);
-}
-
-static inline void
-omap_uhh_write_4(struct omap_uhh_softc *sc, bus_size_t off, uint32_t val)
-{
- bus_write_4(sc->uhh_mem_res, off, val);
-}
-
-static int
-omap_uhh_init(struct omap_uhh_softc *isc)
-{
- uint8_t tll_ch_mask;
- uint32_t reg;
- int i;
-
- /* Enable Clocks for high speed USBHOST */
- ti_sysc_clock_enable(device_get_parent(isc->sc_dev));
-
- /* Read the UHH revision */
- isc->uhh_rev = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_REVISION);
- device_printf(isc->sc_dev, "UHH revision 0x%08x\n", isc->uhh_rev);
-
- /* FIXME */
-#if 0
- if (isc->uhh_rev == OMAP_UHH_REV2) {
- /* For OMAP44xx devices you have to enable the per-port clocks:
- * PHY_MODE - External ULPI clock
- * TTL_MODE - Internal UTMI clock
- * HSIC_MODE - Internal 480Mhz and 60Mhz clocks
- */
- switch(isc->port_mode[0]) {
- case EHCI_HCD_OMAP_MODE_UNKNOWN:
- break;
- case EHCI_HCD_OMAP_MODE_PHY:
- if (ti_prcm_clk_set_source(USBP1_PHY_CLK, EXT_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock source for port 0\n");
- if (ti_prcm_clk_enable(USBP1_PHY_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock USBP1_PHY_CLK source for port 0\n");
- break;
- case EHCI_HCD_OMAP_MODE_TLL:
- if (ti_prcm_clk_enable(USBP1_UTMI_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock USBP1_PHY_CLK source for port 0\n");
- break;
- case EHCI_HCD_OMAP_MODE_HSIC:
- if (ti_prcm_clk_enable(USBP1_HSIC_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock USBP1_PHY_CLK source for port 0\n");
- break;
- default:
- device_printf(isc->sc_dev, "unknown port mode %d for port 0\n", isc->port_mode[0]);
- }
- switch(isc->port_mode[1]) {
- case EHCI_HCD_OMAP_MODE_UNKNOWN:
- break;
- case EHCI_HCD_OMAP_MODE_PHY:
- if (ti_prcm_clk_set_source(USBP2_PHY_CLK, EXT_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock source for port 0\n");
- if (ti_prcm_clk_enable(USBP2_PHY_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock USBP2_PHY_CLK source for port 1\n");
- break;
- case EHCI_HCD_OMAP_MODE_TLL:
- if (ti_prcm_clk_enable(USBP2_UTMI_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock USBP2_UTMI_CLK source for port 1\n");
- break;
- case EHCI_HCD_OMAP_MODE_HSIC:
- if (ti_prcm_clk_enable(USBP2_HSIC_CLK))
- device_printf(isc->sc_dev,
- "failed to set clock USBP2_HSIC_CLK source for port 1\n");
- break;
- default:
- device_printf(isc->sc_dev, "unknown port mode %d for port 1\n", isc->port_mode[1]);
- }
- }
-#endif
-
- /* Put UHH in SmartIdle/SmartStandby mode */
- reg = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_SYSCONFIG);
- if (isc->uhh_rev == OMAP_UHH_REV1) {
- reg &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK |
- UHH_SYSCONFIG_MIDLEMODE_MASK);
- reg |= (UHH_SYSCONFIG_ENAWAKEUP |
- UHH_SYSCONFIG_AUTOIDLE |
- UHH_SYSCONFIG_CLOCKACTIVITY |
- UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE |
- UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY);
- } else if (isc->uhh_rev == OMAP_UHH_REV2) {
- reg &= ~UHH_SYSCONFIG_IDLEMODE_MASK;
- reg |= UHH_SYSCONFIG_IDLEMODE_NOIDLE;
- reg &= ~UHH_SYSCONFIG_STANDBYMODE_MASK;
- reg |= UHH_SYSCONFIG_STANDBYMODE_NOSTDBY;
- }
- omap_uhh_write_4(isc, OMAP_USBHOST_UHH_SYSCONFIG, reg);
- device_printf(isc->sc_dev, "OMAP_UHH_SYSCONFIG: 0x%08x\n", reg);
-
- reg = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_HOSTCONFIG);
-
- /* Setup ULPI bypass and burst configurations */
- reg |= (UHH_HOSTCONFIG_ENA_INCR4 |
- UHH_HOSTCONFIG_ENA_INCR8 |
- UHH_HOSTCONFIG_ENA_INCR16);
- reg &= ~UHH_HOSTCONFIG_ENA_INCR_ALIGN;
-
- if (isc->uhh_rev == OMAP_UHH_REV1) {
- if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
- reg &= ~UHH_HOSTCONFIG_P1_CONNECT_STATUS;
- if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
- reg &= ~UHH_HOSTCONFIG_P2_CONNECT_STATUS;
- if (isc->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
- reg &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
-
- /* Bypass the TLL module for PHY mode operation */
- if ((isc->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
- (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
- (isc->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
- reg &= ~UHH_HOSTCONFIG_P1_ULPI_BYPASS;
- else
- reg |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
-
- } else if (isc->uhh_rev == OMAP_UHH_REV2) {
- reg |= UHH_HOSTCONFIG_APP_START_CLK;
-
- /* Clear port mode fields for PHY mode*/
- reg &= ~UHH_HOSTCONFIG_P1_MODE_MASK;
- reg &= ~UHH_HOSTCONFIG_P2_MODE_MASK;
-
- if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
- reg |= UHH_HOSTCONFIG_P1_MODE_UTMI_PHY;
- else if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_HSIC)
- reg |= UHH_HOSTCONFIG_P1_MODE_HSIC;
-
- if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
- reg |= UHH_HOSTCONFIG_P2_MODE_UTMI_PHY;
- else if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_HSIC)
- reg |= UHH_HOSTCONFIG_P2_MODE_HSIC;
- }
-
- omap_uhh_write_4(isc, OMAP_USBHOST_UHH_HOSTCONFIG, reg);
- device_printf(isc->sc_dev, "UHH setup done, uhh_hostconfig=0x%08x\n", reg);
-
- /* I found the code and comments in the Linux EHCI driver - thanks guys :)
- *
- * "An undocumented "feature" in the OMAP3 EHCI controller, causes suspended
- * ports to be taken out of suspend when the USBCMD.Run/Stop bit is cleared
- * (for example when we do omap_uhh_bus_suspend). This breaks suspend-resume if
- * the root-hub is allowed to suspend. Writing 1 to this undocumented
- * register bit disables this feature and restores normal behavior."
- */
-#if 0
- omap_uhh_write_4(isc, OMAP_USBHOST_INSNREG04,
- OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND);
-#endif
- tll_ch_mask = 0;
- for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
- if (isc->port_mode[i] == EHCI_HCD_OMAP_MODE_TLL)
- tll_ch_mask |= (1 << i);
- }
- if (tll_ch_mask)
- omap_tll_utmi_enable(tll_ch_mask);
-
- return(0);
-}
-
-/**
- * omap_uhh_fini - shutdown the EHCI controller
- * @isc: omap ehci device context
- *
- *
- *
- * LOCKING:
- * none
- *
- * RETURNS:
- * 0 on success, a negative error code on failure.
- */
-static void
-omap_uhh_fini(struct omap_uhh_softc *isc)
-{
- unsigned long timeout;
-
- device_printf(isc->sc_dev, "Stopping TI EHCI USB Controller\n");
-
- /* Set the timeout */
- if (hz < 10)
- timeout = 1;
- else
- timeout = (100 * hz) / 1000;
-
- /* Reset the UHH, OHCI and EHCI modules */
- omap_uhh_write_4(isc, OMAP_USBHOST_UHH_SYSCONFIG, 0x0002);
- while ((omap_uhh_read_4(isc, OMAP_USBHOST_UHH_SYSSTATUS) & 0x07) == 0x00) {
- /* Sleep for a tick */
- pause("USBRESET", 1);
-
- if (timeout-- == 0) {
- device_printf(isc->sc_dev, "operation timed out\n");
- break;
- }
- }
-
- /* Disable functional and interface clocks for the TLL and HOST modules */
- ti_sysc_clock_disable(device_get_parent(isc->sc_dev));
-
- device_printf(isc->sc_dev, "Clock to USB host has been disabled\n");
-}
-
-int
-omap_usb_port_mode(device_t dev, int port)
-{
- struct omap_uhh_softc *isc;
-
- isc = device_get_softc(dev);
- if ((port < 0) || (port >= OMAP_HS_USB_PORTS))
- return (-1);
-
- return isc->port_mode[port];
-}
-
-static int
-omap_uhh_probe(device_t dev)
-{
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- if (!ofw_bus_is_compatible(dev, "ti,usbhs-host"))
- return (ENXIO);
-
- device_set_desc(dev, "TI OMAP USB 2.0 Host module");
-
- return (BUS_PROBE_DEFAULT);
-}
-
-static int
-omap_uhh_attach(device_t dev)
-{
- struct omap_uhh_softc *isc = device_get_softc(dev);
- int err;
- int rid;
- int i;
- phandle_t node;
- char propname[16];
- char *mode;
-
- /* save the device */
- isc->sc_dev = dev;
-
- /* Allocate resource for the UHH register set */
- rid = 0;
- isc->uhh_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
- if (!isc->uhh_mem_res) {
- device_printf(dev, "Error: Could not map UHH memory\n");
- goto error;
- }
-
- node = ofw_bus_get_node(dev);
-
- if (node == -1)
- goto error;
-
- /* Get port modes from FDT */
- for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
- isc->port_mode[i] = EHCI_HCD_OMAP_MODE_UNKNOWN;
- snprintf(propname, sizeof(propname),
- "port%d-mode", i+1);
-
- if (OF_getprop_alloc(node, propname, (void**)&mode) <= 0)
- continue;
- if (strcmp(mode, "ehci-phy") == 0)
- isc->port_mode[i] = EHCI_HCD_OMAP_MODE_PHY;
- else if (strcmp(mode, "ehci-tll") == 0)
- isc->port_mode[i] = EHCI_HCD_OMAP_MODE_TLL;
- else if (strcmp(mode, "ehci-hsic") == 0)
- isc->port_mode[i] = EHCI_HCD_OMAP_MODE_HSIC;
- }
-
- /* Initialise the ECHI registers */
- err = omap_uhh_init(isc);
- if (err) {
- device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err);
- goto error;
- }
-
- simplebus_init(dev, node);
-
- /*
- * Allow devices to identify.
- */
- bus_generic_probe(dev);
-
- /*
- * Now walk the OFW tree and attach top-level devices.
- */
- for (node = OF_child(node); node > 0; node = OF_peer(node))
- simplebus_add_device(dev, node, 0, NULL, -1, NULL);
- return (bus_generic_attach(dev));
-
-error:
- omap_uhh_detach(dev);
- return (ENXIO);
-}
-
-static int
-omap_uhh_detach(device_t dev)
-{
- struct omap_uhh_softc *isc = device_get_softc(dev);
-
- /* during module unload there are lots of children leftover */
- device_delete_children(dev);
-
- if (isc->uhh_mem_res) {
- bus_release_resource(dev, SYS_RES_MEMORY, 0, isc->uhh_mem_res);
- isc->uhh_mem_res = NULL;
- }
-
- omap_uhh_fini(isc);
-
- return (0);
-}
-
-static device_method_t omap_uhh_methods[] = {
- /* Device interface */
- DEVMETHOD(device_probe, omap_uhh_probe),
- DEVMETHOD(device_attach, omap_uhh_attach),
- DEVMETHOD(device_detach, omap_uhh_detach),
-
- DEVMETHOD(device_suspend, bus_generic_suspend),
- DEVMETHOD(device_resume, bus_generic_resume),
- DEVMETHOD(device_shutdown, bus_generic_shutdown),
-
- DEVMETHOD_END
-};
-
-DEFINE_CLASS_1(omap_uhh, omap_uhh_driver, omap_uhh_methods,
- sizeof(struct omap_uhh_softc), simplebus_driver);
-DRIVER_MODULE(omap_uhh, simplebus, omap_uhh_driver, 0, 0);
diff --git a/sys/arm/ti/usb/omap_tll.c b/sys/arm/ti/usb/omap_tll.c
deleted file mode 100644
--- a/sys/arm/ti/usb/omap_tll.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*-
- * Copyright (c) 2011
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/conf.h>
-#include <sys/kernel.h>
-#include <sys/rman.h>
-#include <sys/module.h>
-
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <machine/bus.h>
-
-#include <arm/ti/ti_sysc.h>
-#include <arm/ti/usb/omap_usb.h>
-
-/*
- * USB TLL Module
- */
-#define OMAP_USBTLL_REVISION 0x0000
-#define OMAP_USBTLL_SYSCONFIG 0x0010
-#define OMAP_USBTLL_SYSSTATUS 0x0014
-#define OMAP_USBTLL_IRQSTATUS 0x0018
-#define OMAP_USBTLL_IRQENABLE 0x001C
-#define OMAP_USBTLL_TLL_SHARED_CONF 0x0030
-#define OMAP_USBTLL_TLL_CHANNEL_CONF(i) (0x0040 + (0x04 * (i)))
-#define OMAP_USBTLL_SAR_CNTX(i) (0x0400 + (0x04 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_ID_LO(i) (0x0800 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_ID_HI(i) (0x0801 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_PRODUCT_ID_LO(i) (0x0802 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_PRODUCT_ID_HI(i) (0x0803 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_FUNCTION_CTRL(i) (0x0804 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_FUNCTION_CTRL_SET(i) (0x0805 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_FUNCTION_CTRL_CLR(i) (0x0806 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_INTERFACE_CTRL(i) (0x0807 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_INTERFACE_CTRL_SET(i) (0x0808 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_INTERFACE_CTRL_CLR(i) (0x0809 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_OTG_CTRL(i) (0x080A + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_OTG_CTRL_SET(i) (0x080B + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_OTG_CTRL_CLR(i) (0x080C + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_EN_RISE(i) (0x080D + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_EN_RISE_SET(i) (0x080E + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_EN_RISE_CLR(i) (0x080F + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_EN_FALL(i) (0x0810 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_EN_FALL_SET(i) (0x0811 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_EN_FALL_CLR(i) (0x0812 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_STATUS(i) (0x0813 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_LATCH(i) (0x0814 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_DEBUG(i) (0x0815 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_SCRATCH_REGISTER(i) (0x0816 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_SCRATCH_REGISTER_SET(i) (0x0817 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_SCRATCH_REGISTER_CLR(i) (0x0818 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_EXTENDED_SET_ACCESS(i) (0x082F + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_EN(i) (0x0830 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_EN_SET(i) (0x0831 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_EN_CLR(i) (0x0832 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_STATUS(i) (0x0833 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_LATCH(i) (0x0834 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VSTATUS(i) (0x0835 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VSTATUS_SET(i) (0x0836 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_UTMI_VSTATUS_CLR(i) (0x0837 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_USB_INT_LATCH_NOCLR(i) (0x0838 + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_INT_EN(i) (0x083B + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_INT_EN_SET(i) (0x083C + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_INT_EN_CLR(i) (0x083D + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_INT_STATUS(i) (0x083E + (0x100 * (i)))
-#define OMAP_USBTLL_ULPI_VENDOR_INT_LATCH(i) (0x083F + (0x100 * (i)))
-
-/* TLL Register Set */
-#define TLL_SYSCONFIG_CACTIVITY (1UL << 8)
-#define TLL_SYSCONFIG_SIDLE_SMART_IDLE (2UL << 3)
-#define TLL_SYSCONFIG_SIDLE_NO_IDLE (1UL << 3)
-#define TLL_SYSCONFIG_SIDLE_FORCED_IDLE (0UL << 3)
-#define TLL_SYSCONFIG_ENAWAKEUP (1UL << 2)
-#define TLL_SYSCONFIG_SOFTRESET (1UL << 1)
-#define TLL_SYSCONFIG_AUTOIDLE (1UL << 0)
-
-#define TLL_SYSSTATUS_RESETDONE (1UL << 0)
-
-#define TLL_SHARED_CONF_USB_90D_DDR_EN (1UL << 6)
-#define TLL_SHARED_CONF_USB_180D_SDR_EN (1UL << 5)
-#define TLL_SHARED_CONF_USB_DIVRATIO_MASK (7UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_128 (7UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_64 (6UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_32 (5UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_16 (4UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_8 (3UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_4 (2UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_2 (1UL << 2)
-#define TLL_SHARED_CONF_USB_DIVRATIO_1 (0UL << 2)
-#define TLL_SHARED_CONF_FCLK_REQ (1UL << 1)
-#define TLL_SHARED_CONF_FCLK_IS_ON (1UL << 0)
-
-#define TLL_CHANNEL_CONF_DRVVBUS (1UL << 16)
-#define TLL_CHANNEL_CONF_CHRGVBUS (1UL << 15)
-#define TLL_CHANNEL_CONF_ULPINOBITSTUFF (1UL << 11)
-#define TLL_CHANNEL_CONF_ULPIAUTOIDLE (1UL << 10)
-#define TLL_CHANNEL_CONF_UTMIAUTOIDLE (1UL << 9)
-#define TLL_CHANNEL_CONF_ULPIDDRMODE (1UL << 8)
-#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE (1UL << 7)
-#define TLL_CHANNEL_CONF_TLLFULLSPEED (1UL << 6)
-#define TLL_CHANNEL_CONF_TLLCONNECT (1UL << 5)
-#define TLL_CHANNEL_CONF_TLLATTACH (1UL << 4)
-#define TLL_CHANNEL_CONF_UTMIISADEV (1UL << 3)
-#define TLL_CHANNEL_CONF_CHANEN (1UL << 0)
-
-struct omap_tll_softc {
- device_t sc_dev;
-
- /* TLL register set */
- struct resource* tll_mem_res;
- int tll_mem_rid;
-};
-
-static struct omap_tll_softc *omap_tll_sc;
-
-static int omap_tll_attach(device_t dev);
-static int omap_tll_detach(device_t dev);
-
-static inline uint32_t
-omap_tll_read_4(struct omap_tll_softc *sc, bus_size_t off)
-{
- return bus_read_4(sc->tll_mem_res, off);
-}
-
-static inline void
-omap_tll_write_4(struct omap_tll_softc *sc, bus_size_t off, uint32_t val)
-{
- bus_write_4(sc->tll_mem_res, off, val);
-}
-
-void
-omap_tll_utmi_enable(unsigned int en_mask)
-{
- struct omap_tll_softc *sc;
- unsigned int i;
- uint32_t reg;
-
- sc = omap_tll_sc;
- if (sc == NULL)
- return;
-
- /* There are 3 TLL channels, one per USB controller so set them all up the
- * same, SDR mode, bit stuffing and no autoidle.
- */
- for (i=0; i<3; i++) {
- reg = omap_tll_read_4(sc, OMAP_USBTLL_TLL_CHANNEL_CONF(i));
-
- reg &= ~(TLL_CHANNEL_CONF_UTMIAUTOIDLE
- | TLL_CHANNEL_CONF_ULPINOBITSTUFF
- | TLL_CHANNEL_CONF_ULPIDDRMODE);
-
- omap_tll_write_4(sc, OMAP_USBTLL_TLL_CHANNEL_CONF(i), reg);
- }
-
- /* Program the common TLL register */
- reg = omap_tll_read_4(sc, OMAP_USBTLL_TLL_SHARED_CONF);
-
- reg &= ~( TLL_SHARED_CONF_USB_90D_DDR_EN
- | TLL_SHARED_CONF_USB_DIVRATIO_MASK);
- reg |= ( TLL_SHARED_CONF_FCLK_IS_ON
- | TLL_SHARED_CONF_USB_DIVRATIO_2
- | TLL_SHARED_CONF_USB_180D_SDR_EN);
-
- omap_tll_write_4(sc, OMAP_USBTLL_TLL_SHARED_CONF, reg);
-
- /* Enable channels now */
- for (i = 0; i < 3; i++) {
- reg = omap_tll_read_4(sc, OMAP_USBTLL_TLL_CHANNEL_CONF(i));
-
- /* Enable only the reg that is needed */
- if ((en_mask & (1 << i)) == 0)
- continue;
-
- reg |= TLL_CHANNEL_CONF_CHANEN;
- omap_tll_write_4(sc, OMAP_USBTLL_TLL_CHANNEL_CONF(i), reg);
- }
-}
-
-static int
-omap_tll_init(struct omap_tll_softc *sc)
-{
- unsigned long timeout;
- int ret = 0;
-
- /* Enable the USB TLL */
- ti_sysc_clock_enable(device_get_parent(sc->sc_dev));
-
- /* Perform TLL soft reset, and wait until reset is complete */
- omap_tll_write_4(sc, OMAP_USBTLL_SYSCONFIG, TLL_SYSCONFIG_SOFTRESET);
-
- /* Set the timeout to 100ms*/
- timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
-
- /* Wait for TLL reset to complete */
- while ((omap_tll_read_4(sc, OMAP_USBTLL_SYSSTATUS) &
- TLL_SYSSTATUS_RESETDONE) == 0x00) {
- /* Sleep for a tick */
- pause("USBRESET", 1);
-
- if (timeout-- == 0) {
- device_printf(sc->sc_dev, "TLL reset operation timed out\n");
- ret = EINVAL;
- goto err_sys_status;
- }
- }
-
- /* CLOCKACTIVITY = 1 : OCP-derived internal clocks ON during idle
- * SIDLEMODE = 2 : Smart-idle mode. Sidleack asserted after Idlereq
- * assertion when no more activity on the USB.
- * ENAWAKEUP = 1 : Wakeup generation enabled
- */
- omap_tll_write_4(sc, OMAP_USBTLL_SYSCONFIG, TLL_SYSCONFIG_ENAWAKEUP |
- TLL_SYSCONFIG_AUTOIDLE |
- TLL_SYSCONFIG_SIDLE_SMART_IDLE |
- TLL_SYSCONFIG_CACTIVITY);
-
- return(0);
-
-err_sys_status:
- /* Disable the TLL clocks */
- ti_sysc_clock_disable(device_get_parent(sc->sc_dev));
-
- return(ret);
-}
-
-static void
-omap_tll_disable(struct omap_tll_softc *sc)
-{
- unsigned long timeout;
-
- timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
-
- /* Reset the TLL module */
- omap_tll_write_4(sc, OMAP_USBTLL_SYSCONFIG, 0x0002);
- while ((omap_tll_read_4(sc, OMAP_USBTLL_SYSSTATUS) & (0x01)) == 0x00) {
- /* Sleep for a tick */
- pause("USBRESET", 1);
-
- if (timeout-- == 0) {
- device_printf(sc->sc_dev, "operation timed out\n");
- break;
- }
- }
-
- /* Disable functional and interface clocks for the TLL and HOST modules */
- ti_sysc_clock_disable(device_get_parent(sc->sc_dev));
-}
-
-static int
-omap_tll_probe(device_t dev)
-{
-
- if (!ofw_bus_status_okay(dev))
- return (ENXIO);
-
- if (!ofw_bus_is_compatible(dev, "ti,usbhs-tll"))
- return (ENXIO);
-
- device_set_desc(dev, "TI OMAP USB 2.0 TLL module");
-
- return (BUS_PROBE_DEFAULT);
-}
-
-static int
-omap_tll_attach(device_t dev)
-{
- struct omap_tll_softc *sc;
-
- sc = device_get_softc(dev);
- /* save the device */
- sc->sc_dev = dev;
-
- /* Allocate resource for the TLL register set */
- sc->tll_mem_rid = 0;
- sc->tll_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &sc->tll_mem_rid, RF_ACTIVE);
- if (!sc->tll_mem_res) {
- device_printf(dev, "Error: Could not map TLL memory\n");
- goto error;
- }
-
- omap_tll_init(sc);
-
- omap_tll_sc = sc;
-
- return (0);
-
-error:
- omap_tll_detach(dev);
- return (ENXIO);
-}
-
-static int
-omap_tll_detach(device_t dev)
-{
- struct omap_tll_softc *sc;
-
- sc = device_get_softc(dev);
- omap_tll_disable(sc);
-
- /* Release the other register set memory maps */
- if (sc->tll_mem_res) {
- bus_release_resource(dev, SYS_RES_MEMORY,
- sc->tll_mem_rid, sc->tll_mem_res);
- sc->tll_mem_res = NULL;
- }
-
- omap_tll_sc = NULL;
-
- return (0);
-}
-
-static device_method_t omap_tll_methods[] = {
- /* Device interface */
- DEVMETHOD(device_probe, omap_tll_probe),
- DEVMETHOD(device_attach, omap_tll_attach),
- DEVMETHOD(device_detach, omap_tll_detach),
- DEVMETHOD(device_suspend, bus_generic_suspend),
- DEVMETHOD(device_resume, bus_generic_resume),
- DEVMETHOD(device_shutdown, bus_generic_shutdown),
- {0, 0}
-};
-
-static driver_t omap_tll_driver = {
- "omap_tll",
- omap_tll_methods,
- sizeof(struct omap_tll_softc),
-};
-
-DRIVER_MODULE(omap_tll, simplebus, omap_tll_driver, 0, 0);
diff --git a/sys/arm/ti/usb/omap_usb.h b/sys/arm/ti/usb/omap_usb.h
deleted file mode 100644
--- a/sys/arm/ti/usb/omap_usb.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-4-Clause
- *
- * Copyright (c) 2010
- * Ben Gray <ben.r.gray@gmail.com>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Ben Gray.
- * 4. The name of the company nor the name of the author may be used to
- * endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _OMAP_USB_H_
-#define _OMAP_USB_H_
-
-#define OMAP_HS_USB_PORTS 3
-
-#define EHCI_HCD_OMAP_MODE_UNKNOWN 0
-#define EHCI_HCD_OMAP_MODE_PHY 1
-#define EHCI_HCD_OMAP_MODE_TLL 2
-#define EHCI_HCD_OMAP_MODE_HSIC 3
-
-void omap_tll_utmi_enable(unsigned int en_mask);
-int omap_usb_port_mode(device_t dev, int port);
-
-#endif /* _OMAP_USB_H_ */

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