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Index: sys/arm64/arm64/gic_v3.c
===================================================================
--- sys/arm64/arm64/gic_v3.c
+++ sys/arm64/arm64/gic_v3.c
@@ -382,9 +382,15 @@
mtx_init(&sc->gic_mbi_mtx, "GICv3 mbi lock", NULL, MTX_DEF);
if (sc->gic_mbi_start > 0) {
+ if (sc->gic_mbi_end >= sc->gic_nirqs) {
+ /*
+ * This is to address SPI based msi ranges, where
+ * SPI range is not specified in ACPI
+ */
+ sc->gic_mbi_end = sc->gic_nirqs - 1;
+ }
gic_v3_reserve_msi_range(dev, sc->gic_mbi_start,
- sc->gic_mbi_end - sc->gic_mbi_start);
-
+ sc->gic_mbi_end - sc->gic_mbi_start);
if (bootverbose) {
device_printf(dev, "using spi %u to %u\n", sc->gic_mbi_start,
sc->gic_mbi_end);
Index: sys/arm64/arm64/gic_v3_acpi.c
===================================================================
--- sys/arm64/arm64/gic_v3_acpi.c
+++ sys/arm64/arm64/gic_v3_acpi.c
@@ -306,6 +306,8 @@
return (sc->gic_redists.nregions > 0 ? 0 : ENXIO);
}
+#define HV_MSI_SPI_START 64
+#define HV_MSI_SPI_LAST GIC_I_NUM_MAX
static int
gic_v3_acpi_attach(device_t dev)
{
@@ -320,6 +322,8 @@
if (err != 0)
goto count_error;
+ sc->gic_mbi_start = HV_MSI_SPI_START;
+ sc->gic_mbi_end = HV_MSI_SPI_LAST;
err = gic_v3_attach(dev);
if (err != 0)
goto error;
@@ -330,6 +334,17 @@
err = ENXIO;
goto error;
}
+ /*
+ * Registering for MSI with SPI rnage, as this is
+ * required for Hyper-V GIC to work in ARM64.
+ */
+ if (vm_guest == VM_GUEST_HV) {
+ err = intr_msi_register(dev, ACPI_MSI_XREF);
+ if (err) {
+ device_printf(dev, "could not register MSI\n");
+ goto error;
+ }
+ }
if (intr_pic_claim_root(dev, ACPI_INTR_XREF, arm_gic_v3_intr, sc,
GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) {

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