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diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -3086,10 +3086,10 @@
* register.
*/
if ((desc->id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64))
- cache_size = (CCSIDR_NSETS_64(ccs) + 1) *
- (CCSIDR_ASSOC_64(ccs) + 1);
+ cache_size = (CCSIDR_NumSets64(ccs) + 1) *
+ (CCSIDR_Assoc64(ccs) + 1);
else
- cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1);
+ cache_size = (CCSIDR_NumSets(ccs) + 1) * (CCSIDR_Assoc(ccs) + 1);
cache_size *= line_size;
sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024,
@@ -3377,7 +3377,7 @@
int j = 0;
if ((clidr & CLIDR_CTYPE_IO)) {
WRITE_SPECIALREG(csselr_el1,
- CSSELR_Level(i) | CSSELR_InD);
+ CSSELR_Level(i) | CSSELR_InD_IC);
desc->ccsidr[i][j++] =
READ_SPECIALREG(ccsidr_el1);
}
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -167,30 +167,71 @@
#define APIBKeyLo_EL1_op2 2
/* CCSIDR_EL1 - Cache Size ID Register */
-#define CCSIDR_NumSets_MASK 0x0FFFE000
-#define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000
-#define CCSIDR_NumSets_SHIFT 13
-#define CCSIDR_NumSets64_SHIFT 32
-#define CCSIDR_Assoc_MASK 0x00001FF8
-#define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8
+#define CCSIDR_EL1_REG MRS_REG_ALT_NAME(CCSIDR_EL1)
+#define CCSIDR_EL1_op0 2
+#define CCSIDR_EL1_op1 1
+#define CCSIDR_EL1_CRn 0
+#define CCSIDR_EL1_CRm 0
+#define CCSIDR_EL1_op2 0
+#define CCSIDR_LineSize_SHIFT 0
+#define CCSIDR_LineSize_WIDTH 3
+#define CCSIDR_LineSize_MASK (UL(0x7) << CCSIDR_LineSize_SHIFT)
+#define CCSIDR_LineSize_VAL(x) ((x) & CCSIDR_LineSize_MASK)
#define CCSIDR_Assoc_SHIFT 3
+#define CCSIDR_Assoc_WIDTH 10
+#define CCSIDR_Assoc_MASK (UL(0x3ff) << CCSIDR_Assoc_SHIFT)
+#define CCSIDR_Assoc_VAL(x) ((x) & CCSIDR_Assoc_MASK)
+#define CCSIDR_NumSets_SHIFT 13
+#define CCSIDR_NumSets_WIDTH 15
+#define CCSIDR_NumSets_MASK (UL(0x7fff) << CCSIDR_NumSets_SHIFT)
+#define CCSIDR_NumSets_VAL(x) ((x) & CCSIDR_NumSets_MASK)
+/* FEAT_CCIDX - Extended Cache Index */
#define CCSIDR_Assoc64_SHIFT 3
-#define CCSIDR_LineSize_MASK 0x7
-#define CCSIDR_NSETS(idr) \
+#define CCSIDR_Assoc64_WIDTH 20
+#define CCSIDR_Assoc64_MASK (UL(0x1fffff) << CCSIDR_Assoc64_SHIFT)
+#define CCSIDR_Assoc64_VAL(x) ((x) & CCSIDR_Assoc64_MASK)
+#define CCSIDR_NumSets64_SHIFT 32
+#define CCSIDR_NumSets64_WIDTH 23
+#define CCSIDR_NumSets64_MASK (UL(0xffffff) << CCSIDR_NumSets64_SHIFT)
+#define CCSIDR_NumSets64_VAL(x) ((x) & CCSIDR_NumSets64_MASK)
+#define CCSIDR_NumSets(idr) \
(((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT)
-#define CCSIDR_ASSOC(idr) \
- (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
-#define CCSIDR_NSETS_64(idr) \
+#define CCSIDR_NumSets64(idr) \
(((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT)
-#define CCSIDR_ASSOC_64(idr) \
+#define CCSIDR_Assoc(idr) \
+ (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
+#define CCSIDR_Assoc64(idr) \
(((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT)
/* CLIDR_EL1 - Cache level ID register */
-#define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */
-#define CLIDR_CTYPE_IO 0x1 /* Instruction only */
-#define CLIDR_CTYPE_DO 0x2 /* Data only */
-#define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */
-#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */
+#define CLIDR_EL1_REG MRS_REG_ALT_NAME(CLIDR_EL1)
+#define CLIDR_EL1_op0 2
+#define CLIDR_EL1_op1 1
+#define CLIDR_EL1_CRn 0
+#define CLIDR_EL1_CRm 0
+#define CLIDR_EL1_op2 1
+#define CLIDR_CTYPE_MASK UL(0x7)
+#define CLIDR_CTYPE_NONE 0x0 /* No cache */
+#define CLIDR_CTYPE_IC 0x1 /* Instruction cache only */
+#define CLIDR_CTYPE_DC 0x2 /* Data cache only */
+#define CLIDR_CTYPE_IO 0x3 /* Separate instruction & data cache */
+#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified cache */
+#define CLIDR_LoUIS_SHIFT 21
+#define CLIDR_LoUIS_WIDTH 3
+#define CLIDR_LoUIS_MASK (UL(0x7) << CLIDR_LoUIS_SHIFT)
+#define CLIDR_LoUIS_VAL(x) ((x) & CLIDR_LoUIS_MASK)
+#define CLIDR_LoC_SHIFT 24
+#define CLIDR_LoC_WIDTH 3
+#define CLIDR_LoC_MASK (UL(0x7) << CLIDR_LoC_SHIFT)
+#define CLIDR_LoC_VAL(x) ((x) & CLIDR_LoC_MASK)
+#define CLIDR_LoUU_SHIFT 27
+#define CLIDR_LoUU_WIDTH 3
+#define CLIDR_LoUU_MASK (UL(0x7) << CLIDR_LoUU_SHIFT)
+#define CLIDR_LoUU_VAL(x) ((x) & CLIDR_LoUU_MASK)
+#define CLIDR_ICB_SHIFT 30
+#define CLIDR_ICB_WIDTH 3
+#define CLIDR_ICB_MASK (UL(0x7) << CLIDR_ICB_SHIFT)
+#define CLIDR_ICB_VAL(x) ((x) & CLIDR_ICB_MASK)
/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */
#define CNTKCTL_EL1_op0 3
@@ -342,8 +383,22 @@
#define CPACR_EL12_op2 2
/* CSSELR_EL1 - Cache size selection register */
-#define CSSELR_Level(i) (i << 1)
-#define CSSELR_InD 0x00000001
+#define CSSELR_EL1_REG MRS_REG_ALT_NAME(CSSELR_EL1)
+#define CSSELR_EL1_op0 3
+#define CSSELR_EL1_op1 2
+#define CSSELR_EL1_CRn 0
+#define CSSELR_EL1_CRm 0
+#define CSSELR_EL1_op2 0
+#define CSSELR_InD_SHIFT 0
+#define CSSELR_InD_WIDTH 1
+#define CSSELR_InD_MASK (UL(0x1) << CSSELR_InD_SHIFT)
+#define CSSELR_InD_VAL(x) ((x) & CSSELR_InD_MASK)
+#define CSSELR_InD_DC (0x0 << CSSELR_InD_SHIFT) /* Data or unified cache */
+#define CSSELR_InD_IC (0x1 << CSSELR_InD_SHIFT) /* Instruction cache */
+#define CSSELR_Level_SHIFT 1
+#define CSSELR_Level_WIDTH 3
+#define CSSELR_Level_MASK (UL(0x7) << CSSELR_Level_SHIFT)
+#define CSSELR_Level(i) (i << CSSELR_Level_SHIFT)
/* CTR_EL0 - Cache Type Register */
#define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0)

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