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D58102.diff
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D58102.diff

diff --git a/sys/dev/pci/pci_dw.h b/sys/dev/pci/pci_dw.h
--- a/sys/dev/pci/pci_dw.h
+++ b/sys/dev/pci/pci_dw.h
@@ -78,9 +78,10 @@
#define IATU_CTRL2_REGION_EN (1U << 31)
#define DW_IATU_LWR_BASE_ADDR 0x90C
#define DW_IATU_UPPER_BASE_ADDR 0x910
-#define DW_IATU_LIMIT_ADDR 0x914
+#define DW_IATU_LWR_LIMIT_ADDR 0x914
#define DW_IATU_LWR_TARGET_ADDR 0x918
#define DW_IATU_UPPER_TARGET_ADDR 0x91C
+#define DW_IATU_UPPER_LIMIT_ADDR 0x920
/* Modern (4.80+) "unroll" iATU mode */
#define DW_IATU_UR_STEP 0x200
@@ -89,9 +90,10 @@
#define IATU_UR_CTRL2 0x04
#define IATU_UR_LWR_BASE_ADDR 0x08
#define IATU_UR_UPPER_BASE_ADDR 0x0C
-#define IATU_UR_LIMIT_ADDR 0x10
+#define IATU_UR_LWR_LIMIT_ADDR 0x10
#define IATU_UR_LWR_TARGET_ADDR 0x14
#define IATU_UR_UPPER_TARGET_ADDR 0x18
+#define IATU_UR_UPPER_LIMIT_ADDR 0x20
#define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000
#define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000
diff --git a/sys/dev/pci/pci_dw.c b/sys/dev/pci/pci_dw.c
--- a/sys/dev/pci/pci_dw.c
+++ b/sys/dev/pci/pci_dw.c
@@ -255,8 +255,10 @@
pa & 0xFFFFFFFF);
IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_BASE_ADDR),
(pa >> 32) & 0xFFFFFFFF);
- IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LIMIT_ADDR),
+ IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_LIMIT_ADDR),
(pa + size - 1) & 0xFFFFFFFF);
+ IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_LIMIT_ADDR),
+ ((pa + size - 1) >>32) & 0xFFFFFFFF);
IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_TARGET_ADDR),
pci_addr & 0xFFFFFFFF);
IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_TARGET_ADDR),
@@ -292,7 +294,9 @@
DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(idx));
DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF);
DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF);
- DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF);
+ DBI_WR4(sc, DW_IATU_LWR_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF);
+ DBI_WR4(sc, DW_IATU_UPPER_LIMIT_ADDR,
+ ((pa + size - 1) >> 32) & 0xFFFFFFFF);
DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF);
DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF);
DBI_WR4(sc, DW_IATU_CTRL1, IATU_CTRL1_TYPE(type));

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