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diff --git a/share/man/man4/qat.4 b/share/man/man4/qat.4
--- a/share/man/man4/qat.4
+++ b/share/man/man4/qat.4
@@ -1,6 +1,6 @@
.\" SPDX-License-Identifier: BSD-3-Clause
-.\" Copyright(c) 2007-2022 Intel Corporation
-.Dd May 16, 2025
+.\" Copyright(c) 2007-2025 Intel Corporation
+.Dd June 02, 2025
.Dt QAT 4
.Os
.Sh NAME
@@ -108,6 +108,14 @@
Override the number of uio user space processes
that can connect to the QAT device.
Default: 2
+.It Va dev.qat.X.disable_safe_dc_mode
+Override history buffer mitigation.
+Disabled by default.
+If enabled, decompression throughput increases but may result in a data leak if
+.Va dev.qat.X.num_user_processes
+is more than 1.
+Enable this option only if your system is not prone to user data leaks.
+
.El
.Pp
The following
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -2869,3 +2869,7 @@
# File system monitoring
device filemon # file monitoring for make(1) meta-mode
+
+
+# Options for the Intel QuickAssist (QAT) driver.
+options QAT_DISABLE_SAFE_DC_MODE # Disable QAT safe data compression mode (only for 4940 devices).
diff --git a/sys/conf/options b/sys/conf/options
--- a/sys/conf/options
+++ b/sys/conf/options
@@ -1014,3 +1014,6 @@
# This option is insecure except in controlled environments where the static
# environment's contents are known to be safe.
PRESERVE_EARLY_KENV opt_global.h
+
+# Options for the Intel QuickAssist (QAT) driver.
+QAT_DISABLE_SAFE_DC_MODE opt_qat.h
diff --git a/sys/contrib/dev/qat/qat_4xxx.bin b/sys/contrib/dev/qat/qat_4xxx.bin
index 23eb8077241a4c4b338e6a8be5e4a46cbe43ac84..7783d361a93cedba410590a22cc964526b73b1b3
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diff --git a/sys/dev/qat/include/adf_cfg_device.h b/sys/dev/qat/include/adf_cfg_device.h
--- a/sys/dev/qat/include/adf_cfg_device.h
+++ b/sys/dev/qat/include/adf_cfg_device.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_CFG_DEVICE_H_
#define ADF_CFG_DEVICE_H_
@@ -79,4 +79,6 @@
void adf_cfg_device_clear(struct adf_cfg_device *device,
struct adf_accel_dev *accel_dev);
+void adf_cfg_device_clear_all(struct adf_accel_dev *accel_dev);
+
#endif
diff --git a/sys/dev/qat/include/adf_dbgfs.h b/sys/dev/qat/include/adf_dbgfs.h
new file mode 100644
--- /dev/null
+++ b/sys/dev/qat/include/adf_dbgfs.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
+
+#ifndef ADF_DBGFS_H
+#define ADF_DBGFS_H
+
+void adf_dbgfs_init(struct adf_accel_dev *accel_dev);
+void adf_dbgfs_add(struct adf_accel_dev *accel_dev);
+void adf_dbgfs_rm(struct adf_accel_dev *accel_dev);
+void adf_dbgfs_exit(struct adf_accel_dev *accel_dev);
+#endif
diff --git a/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h b/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h
--- a/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h
+++ b/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_GEN4VF_HW_CSR_DATA_H_
#define ADF_GEN4VF_HW_CSR_DATA_H_
@@ -51,7 +51,7 @@
struct resource *_csr_base_addr = csr_base_addr; \
u32 _bank = bank; \
u32 _ring = ring; \
- dma_addr_t _value = value; \
+ bus_addr_t _value = value; \
u32 l_base = 0, u_base = 0; \
l_base = (u32)((_value)&0xFFFFFFFF); \
u_base = (u32)(((_value)&0xFFFFFFFF00000000ULL) >> 32); \
diff --git a/sys/dev/qat/include/adf_heartbeat.h b/sys/dev/qat/include/adf_heartbeat.h
--- a/sys/dev/qat/include/adf_heartbeat.h
+++ b/sys/dev/qat/include/adf_heartbeat.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_HEARTBEAT_H_
#define ADF_HEARTBEAT_H_
@@ -18,8 +18,8 @@
u64 last_hb_check_time;
enum adf_device_heartbeat_status last_hb_status;
struct qat_sysctl heartbeat;
- struct qat_sysctl *heartbeat_sent;
- struct qat_sysctl *heartbeat_failed;
+ struct qat_sysctl heartbeat_sent;
+ struct qat_sysctl heartbeat_failed;
};
int adf_heartbeat_init(struct adf_accel_dev *accel_dev);
diff --git a/sys/dev/qat/include/adf_pfvf_vf_msg.h b/sys/dev/qat/include/adf_pfvf_vf_msg.h
--- a/sys/dev/qat/include/adf_pfvf_vf_msg.h
+++ b/sys/dev/qat/include/adf_pfvf_vf_msg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_PFVF_VF_MSG_H
#define ADF_PFVF_VF_MSG_H
@@ -8,5 +8,6 @@
int adf_vf2pf_request_version(struct adf_accel_dev *accel_dev);
int adf_vf2pf_get_capabilities(struct adf_accel_dev *accel_dev);
int adf_vf2pf_get_ring_to_svc(struct adf_accel_dev *accel_dev);
+void adf_vf2pf_restarting_complete(struct adf_accel_dev *accel_dev);
#endif /* ADF_PFVF_VF_MSG_H */
diff --git a/sys/dev/qat/include/common/adf_accel_devices.h b/sys/dev/qat/include/common/adf_accel_devices.h
--- a/sys/dev/qat/include/common/adf_accel_devices.h
+++ b/sys/dev/qat/include/common/adf_accel_devices.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_ACCEL_DEVICES_H_
#define ADF_ACCEL_DEVICES_H_
@@ -7,6 +7,8 @@
#include "adf_cfg_common.h"
#include "adf_pfvf_msg.h"
+#include "opt_qat.h"
+
#define ADF_CFG_NUM_SERVICES 4
#define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
@@ -446,6 +448,7 @@
uint8_t num_accel;
uint8_t num_logical_accel;
uint8_t num_engines;
+ bool get_ring_to_svc_done;
int (*get_storage_enabled)(struct adf_accel_dev *accel_dev,
uint32_t *storage_enabled);
u8 query_storage_cap;
@@ -683,10 +686,18 @@
struct sysctl_oid *ras_reset;
struct sysctl_oid *pke_replay_dbgfile;
struct sysctl_oid *misc_error_dbgfile;
+ struct sysctl_oid *fw_version_oid;
+ struct sysctl_oid *mmp_version_oid;
+ struct sysctl_oid *hw_version_oid;
+ struct sysctl_oid *cnv_error_oid;
struct list_head list;
struct adf_accel_pci accel_pci_dev;
struct adf_accel_compat_manager *cm;
u8 compat_ver;
+#ifdef QAT_DISABLE_SAFE_DC_MODE
+ struct sysctl_oid *safe_dc_mode;
+ u8 disable_safe_dc_mode;
+#endif /* QAT_DISABLE_SAFE_DC_MODE */
union {
struct {
/* vf_info is non-zero when SR-IOV is init'ed */
@@ -711,5 +722,6 @@
bool is_vf;
u32 accel_id;
void *lac_dev;
+ struct mutex lock; /* protect accel_dev during start/stop e.t.c */
};
#endif
diff --git a/sys/dev/qat/include/common/adf_cfg_common.h b/sys/dev/qat/include/common/adf_cfg_common.h
--- a/sys/dev/qat/include/common/adf_cfg_common.h
+++ b/sys/dev/qat/include/common/adf_cfg_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_CFG_COMMON_H_
#define ADF_CFG_COMMON_H_
@@ -62,7 +62,7 @@
unsigned char bus;
unsigned char dev;
unsigned char func;
-} __packed;
+};
#define ADF_CFG_SERV_RING_PAIR_0_SHIFT 0
#define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3
diff --git a/sys/dev/qat/include/common/adf_common_drv.h b/sys/dev/qat/include/common/adf_common_drv.h
--- a/sys/dev/qat/include/common/adf_common_drv.h
+++ b/sys/dev/qat/include/common/adf_common_drv.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_DRV_H
#define ADF_DRV_H
@@ -304,6 +304,7 @@
int adf_pf2vf_handle_pf_restarting(struct adf_accel_dev *accel_dev);
int adf_pf2vf_handle_pf_rp_reset(struct adf_accel_dev *accel_dev,
struct pfvf_message msg);
+int adf_pf2vf_handle_pf_error(struct adf_accel_dev *accel_dev);
bool adf_recv_and_handle_pf2vf_msg(struct adf_accel_dev *accel_dev);
static inline int
adf_sriov_configure(device_t *pdev, int numvfs)
diff --git a/sys/dev/qat/include/common/adf_gen4_hw_data.h b/sys/dev/qat/include/common/adf_gen4_hw_data.h
--- a/sys/dev/qat/include/common/adf_gen4_hw_data.h
+++ b/sys/dev/qat/include/common/adf_gen4_hw_data.h
@@ -1,5 +1,5 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2021 Intel Corporation */
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_GEN4_HW_CSR_DATA_H_
#define ADF_GEN4_HW_CSR_DATA_H_
@@ -62,7 +62,7 @@
struct resource *_csr_base_addr = csr_base_addr; \
u32 _bank = bank; \
u32 _ring = ring; \
- dma_addr_t _value = value; \
+ bus_addr_t _value = value; \
u32 l_base = 0, u_base = 0; \
l_base = lower_32_bits(_value); \
u_base = upper_32_bits(_value); \
diff --git a/sys/dev/qat/include/common/adf_pfvf_msg.h b/sys/dev/qat/include/common/adf_pfvf_msg.h
--- a/sys/dev/qat/include/common/adf_pfvf_msg.h
+++ b/sys/dev/qat/include/common/adf_pfvf_msg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_PFVF_MSG_H
#define ADF_PFVF_MSG_H
@@ -97,6 +97,7 @@
ADF_PF2VF_MSGTYPE_RESTARTING = 0x01,
ADF_PF2VF_MSGTYPE_VERSION_RESP = 0x02,
ADF_PF2VF_MSGTYPE_BLKMSG_RESP = 0x03,
+ ADF_PF2VF_MSGTYPE_FATAL_ERROR = 0x04,
/* Values from 0x10 are Gen4 specific, message type is only 4 bits in
Gen2 devices. */
ADF_PF2VF_MSGTYPE_RP_RESET_RESP = 0x10,
@@ -111,6 +112,7 @@
ADF_VF2PF_MSGTYPE_LARGE_BLOCK_REQ = 0x07,
ADF_VF2PF_MSGTYPE_MEDIUM_BLOCK_REQ = 0x08,
ADF_VF2PF_MSGTYPE_SMALL_BLOCK_REQ = 0x09,
+ ADF_VF2PF_MSGTYPE_RESTARTING_COMPLETE = 0x0a,
/* Values from 0x10 are Gen4 specific, message type is only 4 bits in
Gen2 devices. */
ADF_VF2PF_MSGTYPE_RP_RESET = 0x10,
@@ -124,8 +126,10 @@
ADF_PFVF_COMPAT_FAST_ACK = 0x03,
/* Ring to service mapping support for non-standard mappings */
ADF_PFVF_COMPAT_RING_TO_SVC_MAP = 0x04,
+ /* Fallback compat */
+ ADF_PFVF_COMPAT_FALLBACK = 0x05,
/* Reference to the latest version */
- ADF_PFVF_COMPAT_THIS_VERSION = 0x04,
+ ADF_PFVF_COMPAT_THIS_VERSION = 0x05,
};
/* PF->VF Version Response */
diff --git a/sys/dev/qat/include/common/adf_uio_cleanup.h b/sys/dev/qat/include/common/adf_uio_cleanup.h
--- a/sys/dev/qat/include/common/adf_uio_cleanup.h
+++ b/sys/dev/qat/include/common/adf_uio_cleanup.h
@@ -1,10 +1,9 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2023 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_UIO_CLEANUP_H
#define ADF_UIO_CLEANUP_H
void adf_uio_do_cleanup_orphan(int bank,
struct adf_uio_control_accel *accel);
-
#endif
diff --git a/sys/dev/qat/include/common/adf_uio_control.h b/sys/dev/qat/include/common/adf_uio_control.h
--- a/sys/dev/qat/include/common/adf_uio_control.h
+++ b/sys/dev/qat/include/common/adf_uio_control.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2023 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef QAT_UIO_CONTROL_H
#define QAT_UIO_CONTROL_H
#include <sys/condvar.h>
@@ -38,5 +38,4 @@
};
-
#endif /* end of include guard: QAT_UIO_CONTROL_H */
diff --git a/sys/dev/qat/include/icp_qat_fw_init_admin.h b/sys/dev/qat/include/icp_qat_fw_init_admin.h
--- a/sys/dev/qat/include/icp_qat_fw_init_admin.h
+++ b/sys/dev/qat/include/icp_qat_fw_init_admin.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef _ICP_QAT_FW_INIT_ADMIN_H_
#define _ICP_QAT_FW_INIT_ADMIN_H_
@@ -43,6 +43,8 @@
CNV_ERR_TYPE_UNKNOWN_ERROR
};
+#define ICP_QAT_FW_INIT_DISABLE_SAFE_DC_MODE_FLAG 0x02
+
#define CNV_ERROR_TYPE_GET(latest_error) \
({ \
__typeof__(latest_error) _lerror = latest_error; \
@@ -69,7 +71,8 @@
struct {
u64 resrvd2;
u16 ibuf_size_in_kb;
- u16 resrvd3;
+ u8 fw_flags;
+ u8 resrvd3;
u32 resrvd4;
};
/* ICP_QAT_FW_CONSTANTS_CFG */
@@ -195,8 +198,8 @@
enum icp_qat_fw_init_admin_init_flag { ICP_QAT_FW_INIT_FLAG_PKE_DISABLED = 0 };
struct icp_qat_fw_init_admin_hb_cnt {
- u16 resp_heartbeat_cnt;
u16 req_heartbeat_cnt;
+ u16 resp_heartbeat_cnt;
};
#define ICP_QAT_FW_COMN_HEARTBEAT_OK 0
diff --git a/sys/dev/qat/qat/qat_ocf.c b/sys/dev/qat/qat/qat_ocf.c
--- a/sys/dev/qat/qat/qat_ocf.c
+++ b/sys/dev/qat/qat/qat_ocf.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/* System headers */
#include <sys/param.h>
#include <sys/systm.h>
@@ -1280,7 +1280,6 @@
.size = sizeof(struct qat_ocf_softc),
};
-
DRIVER_MODULE_ORDERED(qat,
nexus,
qat_ocf_driver,
diff --git a/sys/dev/qat/qat_api/common/compression/dc_datapath.c b/sys/dev/qat/qat_api/common/compression/dc_datapath.c
--- a/sys/dev/qat/qat_api/common/compression/dc_datapath.c
+++ b/sys/dev/qat/qat_api/common/compression/dc_datapath.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file dc_datapath.c
@@ -118,14 +118,19 @@
/* Cast response message to compression response message type */
pCompRespMsg = (icp_qat_fw_comp_resp_t *)pRespMsg;
-
+ if (!(pCompRespMsg)) {
+ QAT_UTILS_LOG("pCompRespMsg is NULL\n");
+ return;
+ }
/* Extract request data pointer from the opaque data */
LAC_MEM_SHARED_READ_TO_PTR(pCompRespMsg->opaque_data, pReqData);
+ if (!(pReqData)) {
+ QAT_UTILS_LOG("pReqData is NULL\n");
+ return;
+ }
/* Extract fields from the request data structure */
pCookie = (dc_compression_cookie_t *)pReqData;
- if (!pCookie)
- return;
pSessionDesc = DC_SESSION_DESC_FROM_CTX_GET(pCookie->pSessionHandle);
pService = (sal_compression_service_t *)(pCookie->dcInstance);
@@ -523,7 +528,7 @@
if (CPA_TRUE == pOpData->integrityCrcCheck &&
NULL == pOpData->pCrcData) {
LAC_INVALID_PARAM_LOG("Integrity CRC data structure "
- "not intialized in CpaDcOpData");
+ "not initialized in CpaDcOpData");
return CPA_STATUS_INVALID_PARAM;
}
@@ -1401,7 +1406,6 @@
CpaInstanceHandle insHandle = NULL;
Cpa64U srcBuffSize = 0;
-
if (CPA_INSTANCE_HANDLE_SINGLE == dcInstance) {
insHandle = dcGetFirstHandle();
} else {
@@ -1507,7 +1511,6 @@
return CPA_STATUS_INVALID_PARAM;
}
-
if ((CPA_TRUE == pOpData->compressAndVerify) &&
(CPA_TRUE == pOpData->compressAndVerifyAndRecover) &&
(CPA_FALSE == pOpData->integrityCrcCheck)) {
@@ -1526,7 +1529,6 @@
return CPA_STATUS_UNSUPPORTED;
}
-
if (CPA_INSTANCE_HANDLE_SINGLE == dcInstance) {
insHandle = dcGetFirstHandle();
} else {
@@ -1703,7 +1705,6 @@
return CPA_STATUS_INVALID_PARAM;
}
-
*srcBufferSize = srcBuffSize;
return CPA_STATUS_SUCCESS;
@@ -1724,7 +1725,6 @@
Cpa64U srcBuffSize = 0;
CpaStatus status = CPA_STATUS_SUCCESS;
-
if (CPA_INSTANCE_HANDLE_SINGLE == dcInstance) {
insHandle = dcGetFirstHandle();
} else {
@@ -1783,7 +1783,6 @@
return CPA_STATUS_INVALID_PARAM;
}
-
if (CPA_DC_STATEFUL == pSessionDesc->sessState) {
/* Lock the session to check if there are in-flight stateful
* requests */
@@ -1864,7 +1863,6 @@
callbackTag);
}
-
if (CPA_INSTANCE_HANDLE_SINGLE == dcInstance) {
insHandle = dcGetFirstHandle();
} else {
@@ -1931,7 +1929,6 @@
return CPA_STATUS_INVALID_PARAM;
}
-
if (CPA_DC_STATEFUL == pSessionDesc->sessState) {
/* Lock the session to check if there are in-flight stateful
* requests */
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_session.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_session.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_session.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_session.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -56,7 +56,7 @@
* while there are requests in flight.
*
* <b>Reference Count</b>\n
- * - The perform funcion increments the reference count for the session.
+ * - The perform function increments the reference count for the session.
* - The callback function decrements the reference count for the session.
* - The Remove function checks the reference count to ensure that it is 0.
*
@@ -256,14 +256,14 @@
/**< Cipher slice type to be used, set at init session time */
Cpa8U cipherAesXtsKey1Forward[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< Cached AES XTS Forward key
- * For CPM2.0 AES XTS key convertion need to be done in SW.
+ * For CPM2.0 AES XTS key conversions need to be done in SW.
* Because use can update session direction at any time,
* also forward key needs to be cached
*/
Cpa8U cipherAesXtsKey1Reverse[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< AES XTS Reverse key
- * For CPM2.0 AES XTS key convertion need to be done in SW.
- * Reverse key always will be calcilated at session setup time and
+ * For CPM2.0 AES XTS key conversions need to be done in SW.
+ * Reverse key always will be calculated at session setup time and
* cached to be used when needed */
Cpa8U cipherAesXtsKey2[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< For AES XTS session need to store Key2 value in order to generate
@@ -442,14 +442,14 @@
/**< Cipher slice type to be used, set at init session time */
Cpa8U cipherAesXtsKey1Forward[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< Cached AES XTS Forward key
- * For CPM2.0 AES XTS key convertion need to be done in SW.
+ * For CPM2.0 AES XTS key conversions need to be done in SW.
* Because use can update session direction at any time,
* also forward key needs to be cached
*/
Cpa8U cipherAesXtsKey1Reverse[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< AES XTS Reverse key
- * For CPM2.0 AES XTS key convertion need to be done in SW.
- * Reverse key always will be calcilated at session setup time and
+ * For CPM2.0 AES XTS key conversions need to be done in SW.
+ * Reverse key always will be calculated at session setup time and
* cached to be used when needed */
Cpa8U cipherAesXtsKey2[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< For AES XTS session need to store Key2 value in order to generate
@@ -594,14 +594,14 @@
/**< Cipher slice type to be used, set at init session time */
Cpa8U cipherAesXtsKey1Forward[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< Cached AES XTS Forward key
- * For CPM2.0 AES XTS key convertion need to be done in SW.
+ * For CPM2.0 AES XTS key conversions need to be done in SW.
* Because use can update session direction at any time,
* also forward key needs to be cached
*/
Cpa8U cipherAesXtsKey1Reverse[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< AES XTS Reverse key
- * For CPM2.0 AES XTS key convertion need to be done in SW.
- * Reverse key always will be calcilated at session setup time and
+ * For CPM2.0 AES XTS key conversions need to be done in SW.
+ * Reverse key always will be calculated at session setup time and
* cached to be used when needed */
Cpa8U cipherAesXtsKey2[LAC_CIPHER_AES_XTS_KEY_MAX_LENGTH];
/**< For AES XTS session need to store Key2 value in order to generate
@@ -625,7 +625,7 @@
sizeof(LAC_ARCH_UINT))
/**< @ingroup LacSym_Session
* Size of the memory that the client has to allocate for a session. Extra
- * memory is needed to internally re-align the data. The pointer to the algined
+ * memory is needed to internally re-align the data. The pointer to the aligned
* data is stored at the start of the user allocated memory hence the extra
* space for an LAC_ARCH_UINT */
@@ -669,7 +669,7 @@
*
* @param[in] instanceHandle_in Instance Handle
* @param[in] pSymCb callback function
-* @param[in] pSessionSetupData pointer to the strucutre containing the setup
+* @param[in] pSessionSetupData pointer to the structure containing the setup
*data
* @param[in] isDpSession CPA_TRUE for a data plane session
* @param[out] pSessionCtx Pointer to session context
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -18,7 +18,7 @@
* The symmetric component demuliplexes the following crypto operations to
* the appropriate sub-components: cipher, hash, algorithm chaining and
* authentication encryption. It is a common layer between the above
- * mentioned components where common resources are allocated and paramater
+ * mentioned components where common resources are allocated and parameter
* checks are done. The operation specific resource allocation and parameter
* checks are done in the sub-component itself.
*
@@ -32,15 +32,15 @@
* chain to ensure it is valid.
* - \ref LacSymStats "Statistics": Manages statistics for symmetric
* - \ref LacSymQat "Symmetric QAT": The symmetric qat component is
- * initialiased by the symmetric component.
- * - \ref LacCipher "Cipher" : demultiplex cipher opertions to this component.
- * - \ref LacHash "Hash" : demultiplex hash opertions to this component.
+ * initialised by the symmetric component.
+ * - \ref LacCipher "Cipher" : demultiplex cipher operations to this component.
+ * - \ref LacHash "Hash" : demultiplex hash operations to this component.
* to this component.
* - \ref LacAlgChain "Algorithm Chaining": The algorithm chaining component
* - OSAL : Memory allocation, Mutex's, atomics
*
* @lld_initialisation
- * This component is initialied during the LAC initialisation sequence. It
+ * This component is initialized during the LAC initialisation sequence. It
* initialises the session table, statistics, symmetric QAT, initialises the
* hash definitions lookup table, the hash alg supported lookup table and
* registers a callback function with the symmetric response handler to process
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_alg_chain.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_alg_chain.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_alg_chain.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_alg_chain.h
@@ -1,8 +1,5 @@
-/***************************************************************************
- *
- * <COPYRIGHT_TAG>
- *
- ***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cb.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cb.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cb.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cb.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -21,7 +21,7 @@
* Dequeue pending requests
* @description
* This function is called by a callback function of a blocking
- * operation (either a partial packet or a hash precompute operaion)
+ * operation (either a partial packet or a hash precompute operation)
* in softIRQ context. It dequeues requests for the following reasons:
* 1. All pre-computes that happened when initialising a session
* have completed. Dequeue any requests that were queued on the
@@ -40,7 +40,7 @@
/**
*****************************************************************************
* @ingroup LacSym
- * Register symmetric callback funcion handlers
+ * Register symmetric callback function handlers
*
* @description
* This function registers the symmetric callback handler functions with
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cipher.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cipher.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cipher.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_cipher.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -23,14 +23,14 @@
* and Triple-DES cipher algorithms, in ECB, CBC and CTR modes. The ARC4 stream
* cipher algorithm is also supported. Data may be provided as a full packet,
* or as a sequence of partial packets. The result of the operation can be
- * written back to the source buffer (in-place) or to a seperate output buffer
+ * written back to the source buffer (in-place) or to a separate output buffer
* (out-of-place). Data must be encapsulated in ICP buffers.
*
* The cipher component is responsible for implementing the cipher-specific
* functionality for registering and de-registering a session, for the perform
* operation and for processing the QAT responses to cipher requests. Statistics
* are maintained for cipher in the symmetric \ref CpaCySymStats64 "stats"
- * structure. This module has been seperated out into two. The cipher QAT module
+ * structure. This module has been separated out into two. The cipher QAT module
* deals entirely with QAT data structures. The cipher module itself has minimal
* exposure to the QAT data structures.
*
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash.h
@@ -1,8 +1,5 @@
-/***************************************************************************
- *
- * <COPYRIGHT_TAG>
- *
- ***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -24,7 +21,7 @@
*
* The hash component supports hashing in 3 modes. PLAIN, AUTH and NESTED.
* Plain mode is used to provide data integrity while auth mode is used to
- * provide integrity as well as its authenticity. Nested mode is inteded
+ * provide integrity as well as its authenticity. Nested mode is intended
* for use by non standard HMAC like algorithms such as for the SSL master
* key secret. Partial packets is supported for both plain and auth modes.
* In-place and out-of-place processing is supported for all modes. The
@@ -33,7 +30,7 @@
* The hash component is responsible for implementing the hash specific
* functionality for initialising a session and for a perform operation.
* Statistics are maintained in the symmetric \ref CpaCySymStats64 "stats"
- * structure. This module has been seperated out into two. The hash QAT module
+ * structure. This module has been separated out into two. The hash QAT module
* deals entirely with QAT data structures. The hash module itself has minimal
* exposure to the QAT data structures.
*
@@ -62,7 +59,7 @@
* the data path by the length of time it takes to do two hashes on a block
* size of data. Note: a partial packet operation generates an intermediate
* state. The final operation on a partial packet or when a full packet is
- * used applies padding and gives the final hash result. Esentially for the
+ * used applies padding and gives the final hash result. Essentially for the
* inner hash, a partial packet final is issued on the data, using the
* precomputed intermediate state and returns the digest.
*
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_defs.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_defs.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_defs.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_defs.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -313,7 +313,7 @@
/**< @ingroup LacSymQatHash
* Macro to check for qat hash mode is set to 2 and the hash mode is
* Auth. This applies to HMAC algorithms (no pre compute). This is used
- * to differntiate between TLS and HMAC */
+ * to differentiate between TLS and HMAC */
#define IS_HASH_MODE_2_NESTED(qatHashMode, hashMode) \
((IS_HASH_MODE_2(qatHashMode)) && \
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_precomputes.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_precomputes.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_precomputes.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_hash_precomputes.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -34,7 +34,7 @@
/**< maximum size of the working data for the HMAC precompute operations
*
* Maximum size of lac_sym_hash_precomp_op_data_t is 264 bytes. For hash
- * precomputes there are 2 of these structrues and a further
+ * precomputes there are 2 of these structures and a further
* lac_sym_hash_precomp_op_t structure required. This comes to a total of 536
* bytes.
* For the asynchronous version of the precomputes, the memory for the hash
@@ -122,7 +122,7 @@
Cpa8U contentDesc[LAC_SYM_QAT_MAX_CIPHER_SETUP_BLK_SZ];
/**< Content descriptor for a cipher operation */
Cpa8U data[LAC_SYM_HASH_PRECOMP_MAX_AES_ECB_DATA];
- /**< The data to be ciphered is conatined here and the result is
+ /**< The data to be ciphered is contained here and the result is
* written in place back into this buffer */
icp_qat_fw_la_cipher_req_params_t cipherReqParams;
/**< Request parameters as read in by the QAT */
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_key.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_key.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_key.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_key.h
@@ -1,8 +1,5 @@
-/***************************************************************************
- *
- * <COPYRIGHT_TAG>
- *
- ***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -16,7 +13,7 @@
*
* @lld_overview
*
- * Key generation component is reponsible for SSL, TLS & MGF operations. All
+ * Key generation component is responsible for SSL, TLS & MGF operations. All
* memory required for the keygen operations is got from the keygen cookie
* structure which is carved up as required.
*
@@ -24,8 +21,8 @@
* outer hash and SHA1 as the inner hash.
*
* Refer to sections in draft-freier-ssl-version3-02.txt:
- * 6.1 Asymmetric cryptographic computations - This refers to coverting
- * the pre master secret to the master secret.
+ * 6.1 Asymmetric cryptographic computations - This refers to converting
+ * the pre-master secret to the master secret.
* 6.2.2 Converting the master secret into keys and MAC secrets - Using
* the master secret to generate the key material.
*
@@ -40,11 +37,11 @@
*
* @lld_dependencies
* \ref LacSymQatHash: for building up hash content descriptor
- * \ref LacMem: for virt to phys coversions
+ * \ref LacMem: for virt to phys conversions
*
* @lld_initialisation
- * The reponse handler is registered with Symmetric. The Maximum SSL is
- * allocated. A structure is allocated containing all the TLS lables that
+ * The response handler is registered with Symmetric. The Maximum SSL is
+ * allocated. A structure is allocated containing all the TLS labels that
* are supported. On shutdown the memory for these structures are freed.
*
* @lld_module_algorithms
@@ -115,7 +112,7 @@
*
* @description
* This structure is used to hold the various TLS labels. Each field is
- * on an 8 byte boundary provided the structure itslef is 8 bytes aligned.
+ * on an 8 byte boundary provided the structure itself is 8 bytes aligned.
*****************************************************************************/
typedef struct lac_sym_key_tls_labels_s {
Cpa8U masterSecret[ICP_QAT_FW_LA_TLS_LABEL_LEN_MAX];
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_partial.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_partial.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_partial.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_partial.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -20,7 +20,7 @@
* proceed where they would get an incorrect digest, cipher result.
*
* Maintain a SpinLock for partials in flight per session. Try and acquire this
- * SpinLock. If it cant be acquired return an error straight away to the client
+ * SpinLock. If it can't be acquired return an error straight away to the client
* as there is already a partial in flight. There is no blocking in the data
* path for this.
*
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -24,7 +24,7 @@
* - \ref LacMem "Memory" - Inline memory functions
*
* @lld_initialisation
- * This component is initialied during the LAC initialisation sequence. It
+ * This component is initialized during the LAC initialisation sequence. It
* is called by the Symmetric Initialisation function.
*
* @lld_module_algorithms
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_cipher.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_cipher.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_cipher.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_cipher.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -172,7 +172,7 @@
* LacSymQat_CipherCtrlBlockInitialize()
*
* @description
- * intialize the cipher control block with all zeros
+ * initialize the cipher control block with all zeros
*
* @param[in] pMsg Pointer to the common request message
*
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -42,7 +42,7 @@
* hash precomputes
*
* @description
- * This structure contains infomation on the hash precomputes
+ * This structure contains information on the hash precomputes
*
*****************************************************************************/
typedef struct lac_sym_qat_hash_precompute_info_s {
@@ -62,7 +62,7 @@
* hash state prefix buffer info
*
* @description
- * This structure contains infomation on the hash state prefix aad buffer
+ * This structure contains information on the hash state prefix aad buffer
*
*****************************************************************************/
typedef struct lac_sym_qat_hash_state_buffer_info_s {
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash_defs_lookup.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash_defs_lookup.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash_defs_lookup.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_qat_hash_defs_lookup.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -117,7 +117,7 @@
/**
*******************************************************************************
* @ingroup LacSymQatHashDefsLookup
-* get hash defintions from lookup table.
+* get hash definitions from lookup table.
*
* @description
* This function looks up the hash lookup array for a structure
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_stats.h b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_stats.h
--- a/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_stats.h
+++ b/sys/dev/qat/qat_api/common/crypto/sym/include/lac_sym_stats.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -9,7 +9,7 @@
*
* @ingroup LacSym
*
- * Symetric Common consists of common statistics, buffer and partial packet
+ * Symmetric Common consists of common statistics, buffer and partial packet
* functionality.
*
***************************************************************************/
@@ -123,7 +123,7 @@
/**
*******************************************************************************
* @ingroup LacSymStats
-* Inrement a stat
+* Increment a stat
*
* @description
* This function incrementes a stat for a specific engine.
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/key/lac_sym_key.c b/sys/dev/qat/qat_api/common/crypto/sym/key/lac_sym_key.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/key/lac_sym_key.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/key/lac_sym_key.c
@@ -1,8 +1,5 @@
-/***************************************************************************
- *
- * <COPYRIGHT_TAG>
- *
- ***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -365,7 +362,6 @@
{
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -393,7 +389,6 @@
{
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -917,7 +912,6 @@
{
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -956,7 +950,6 @@
{
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -2167,6 +2160,14 @@
}
}
+ /* check 0 secret length as it is not valid for SSL3 Key Gen
+ * request */
+ if (0 == uSecretLen) {
+ LAC_INVALID_PARAM_LOG1("%u secret.dataLenInBytes",
+ uSecretLen);
+ return CPA_STATUS_INVALID_PARAM;
+ }
+
/* Only seed length for SSL3 Key Gen request */
if (maxSeedLen != uSeedLen) {
LAC_INVALID_PARAM_LOG("seed.dataLenInBytes");
@@ -2194,11 +2195,11 @@
/* Api max value */
/* ICP_QAT_FW_LA_TLS_V1_1_SECRET_LEN_MAX needs to be
* multiplied
- * by 4 in order to verifiy the 512 conditions. We did
+ * by 4 in order to verify the 512 conditions. We did
* not change
* ICP_QAT_FW_LA_TLS_V1_1_SECRET_LEN_MAX as it
* represents
- * the max value tha firmware can handle.
+ * the max value that firmware can handle.
*/
maxSecretLen =
ICP_QAT_FW_LA_TLS_V1_1_SECRET_LEN_MAX * 4;
@@ -2206,11 +2207,11 @@
/* Api max value */
/* ICP_QAT_FW_LA_TLS_V1_2_SECRET_LEN_MAX needs to be
* multiplied
- * by 8 in order to verifiy the 512 conditions. We did
+ * by 8 in order to verify the 512 conditions. We did
* not change
* ICP_QAT_FW_LA_TLS_V1_2_SECRET_LEN_MAX as it
* represents
- * the max value tha firmware can handle.
+ * the max value that firmware can handle.
*/
maxSecretLen =
ICP_QAT_FW_LA_TLS_V1_2_SECRET_LEN_MAX * 8;
@@ -2596,7 +2597,6 @@
{
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -2669,7 +2669,6 @@
{
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -2756,7 +2755,6 @@
return CPA_STATUS_INVALID_PARAM;
}
-
return LacSymKey_KeyGenSslTls(instanceHandle_in,
pKeyGenCb,
pCallbackTag,
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_alg_chain.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_alg_chain.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_alg_chain.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_alg_chain.c
@@ -1,8 +1,5 @@
-/***************************************************************************
- *
- * <COPYRIGHT_TAG>
- *
- ***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -403,7 +400,6 @@
&sizeInBytes);
}
}
-
static Cpa16U
LacAlgChain_GetCipherConfigSize(lac_session_desc_t *pSessionDesc)
{
@@ -1178,7 +1174,7 @@
&cipherOffsetInConstantsTable,
&hashOffsetInConstantsTable);
- /* for a certain combination of Algorthm Chaining we want to
+ /* for a certain combination of Algorithm Chaining we want to
use an optimised cd block */
if (pSessionDesc->symOperation ==
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_api.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_api.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_api.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_api.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -336,7 +336,6 @@
return CPA_STATUS_SUCCESS;
}
-
/**
* @ingroup LacSym
* Function which perform parameter checks on data buffers for symmetric
@@ -445,7 +444,7 @@
}
}
- /* check for partial packet suport for the session operation */
+ /* check for partial packet support for the session operation */
if (CPA_CY_SYM_PACKET_TYPE_FULL != pOpData->packetType) {
if (CPA_FALSE == pSessionDesc->isPartialSupported) {
/* return out here to simplify cleanup */
@@ -569,7 +568,6 @@
return CPA_STATUS_INVALID_PARAM;
}
-
pCipherSetupData = &pSessionSetupData->cipherSetupData;
pHashSetupData = &pSessionSetupData->hashSetupData;
@@ -673,7 +671,6 @@
CpaInstanceHandle instanceHandle = NULL;
Cpa64U numPendingRequests = 0;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -794,7 +791,6 @@
}
}
-
/* If synchronous Operation - Callback function stored in the session
* descriptor so a flag is set in the perform to indicate that
* the perform is being re-called for the synchronous operation */
@@ -872,7 +868,7 @@
pVerifyResult);
if (CPA_STATUS_SUCCESS == status) {
- /* check for partial packet suport for the session operation */
+ /* check for partial packet support for the session operation */
if (CPA_CY_SYM_PACKET_TYPE_FULL != pOpData->packetType) {
LacSym_PartialPacketStateUpdate(
pOpData->packetType, &pSessionDesc->partialState);
@@ -923,7 +919,6 @@
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -955,7 +950,6 @@
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle =
Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO_SYM);
@@ -1037,7 +1031,6 @@
/* Choose Session Context size */
getCtxSize(pSessionSetupData, pSessionCtxSizeInBytes);
-
return CPA_STATUS_SUCCESS;
}
@@ -1116,6 +1109,5 @@
(sizeof(icp_flat_buffer_desc_t) * numBuffers) +
ICP_DESCRIPTOR_ALIGNMENT_BYTES;
-
return CPA_STATUS_SUCCESS;
}
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_auth_enc.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_auth_enc.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_auth_enc.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_auth_enc.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -91,7 +91,6 @@
return CPA_STATUS_SUCCESS;
}
-
/**
* @ingroup LacAuthEnc
*/
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cb.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cb.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cb.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cb.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -296,7 +296,7 @@
/* For CCM and GCM, if qatRespStatusOkFlag is false, the data has to be
* cleaned as stated in RFC 3610; in DP mode, it is the user
- * responsability to do so */
+ * responsibility to do so */
if (((CPA_CY_SYM_OP_CIPHER == pSessionDesc->symOperation) &&
SPC != pSessionDesc->singlePassState) ||
@@ -450,12 +450,11 @@
}
/*
- * Now we'll attempt to send the message directly to QAT. We'll
- * keep looing until it succeeds (or at least a very high number
- * of retries), as the failure only happens when the ring is
- * full, and this is only a temporary situation. After a few
- * retries, space will become availble, allowing the putMsg to
- * succeed.
+ * Now we'll attempt to send the message directly to QAT. We'll keep
+ * looking until it succeeds (or at least a very high number of
+ * retries), as the failure only happens when the ring is full,
+ * and this is only a temporary situation. After a few retries,
+ * space will become available, allowing the putMsg to succeed.
*/
retries = 0;
do {
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cipher.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cipher.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cipher.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_cipher.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -143,7 +143,7 @@
CPA_TRUE;
}
/* For subsequent partials in a sequence, we'll
- * re-use the IV that was written back by the
+ * reuse the IV that was written back by the
* QAT, using internal request queueing if
* necessary to ensure that the next partial
* request isn't issued to the QAT until the
@@ -215,7 +215,6 @@
return CPA_STATUS_SUCCESS;
}
-
CpaStatus
LacCipher_SessionSetupDataCheck(const CpaCySymCipherSetupData *pCipherSetupData,
Cpa32U capabilitiesMask)
@@ -440,7 +439,7 @@
Cpa32U capabilitiesMask =
pService->generic_service_info.capabilitiesMask;
- /* UCS Slice is supproted only in Gen4 */
+ /* UCS Slice is supported only in Gen4 */
if (isCyGen4x(pService)) {
if (LAC_CIPHER_IS_XTS_MODE(cipherAlgorithm) ||
LAC_CIPHER_IS_CHACHA(cipherAlgorithm) ||
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_compile_check.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_compile_check.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_compile_check.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_compile_check.c
@@ -1,8 +1,5 @@
-/***************************************************************************
- *
- * <COPYRIGHT_TAG>
- *
- ***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_dp.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_dp.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_dp.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_dp.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -962,7 +962,6 @@
CpaStatus status = CPA_STATUS_FAIL;
sal_service_t *pService = NULL;
-
LAC_CHECK_INSTANCE_HANDLE(instanceHandle);
SAL_CHECK_INSTANCE_TYPE(instanceHandle,
(SAL_SERVICE_TYPE_CRYPTO |
@@ -999,7 +998,6 @@
{
sal_crypto_service_t *pService = (sal_crypto_service_t *)instanceHandle;
-
LAC_CHECK_INSTANCE_HANDLE(instanceHandle);
SAL_CHECK_INSTANCE_TYPE(instanceHandle,
(SAL_SERVICE_TYPE_CRYPTO |
@@ -1021,7 +1019,6 @@
CpaStatus status = CPA_STATUS_SUCCESS;
-
LAC_CHECK_NULL_PARAM(pRequest);
status = LacDp_EnqueueParamCheck(pRequest);
if (CPA_STATUS_SUCCESS != status) {
@@ -1064,7 +1061,6 @@
{
icp_comms_trans_handle trans_handle = NULL;
-
LAC_CHECK_INSTANCE_HANDLE(instanceHandle);
SAL_CHECK_INSTANCE_TYPE(instanceHandle,
(SAL_SERVICE_TYPE_CRYPTO |
@@ -1097,7 +1093,6 @@
CpaStatus status = CPA_STATUS_SUCCESS;
sal_crypto_service_t *pService = NULL;
-
LAC_CHECK_NULL_PARAM(pRequests);
LAC_CHECK_NULL_PARAM(pRequests[0]);
LAC_CHECK_NULL_PARAM(pRequests[0]->instanceHandle);
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -366,7 +366,6 @@
return status;
}
-
/** @ingroup LacHash */
CpaStatus
LacHash_HashContextCheck(CpaInstanceHandle instanceHandle,
@@ -752,10 +751,13 @@
&pHashAlgInfo);
/* check if the message is a multiple of the block size. */
- if ((pOpData->messageLenToHashInBytes %
- pHashAlgInfo->blockLength) != 0) {
- LAC_INVALID_PARAM_LOG(
- "messageLenToHashInBytes not block size");
+ if (pOpData->messageLenToHashInBytes %
+ pHashAlgInfo->blockLength !=
+ 0) {
+ LAC_INVALID_PARAM_LOG2(
+ "message(%d) not block-size(%d) multiple",
+ pOpData->messageLenToHashInBytes,
+ pHashAlgInfo->blockLength);
return CPA_STATUS_INVALID_PARAM;
}
}
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash_sw_precomputes.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash_sw_precomputes.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash_sw_precomputes.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_hash_sw_precomputes.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -53,7 +53,7 @@
* Note: from SHA hashes appropriate endian swapping is required.
* For sha1, sha224 and sha256 double words based swapping.
* For sha384 and sha512 quad words swapping.
- * No endianes swapping for md5 is required.
+ * No endianness swapping for md5 is required.
*/
CpaStatus status = CPA_STATUS_FAIL;
Cpa32U i = 0;
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_queue.c b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_queue.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_queue.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/lac_sym_queue.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -111,7 +111,7 @@
*/
if (CPA_CY_SYM_PACKET_TYPE_FULL !=
pRequest->pOpData->packetType) {
- /* Select blocking operations which this reqest will
+ /* Select blocking operations which this request will
* complete */
pSessionDesc->nonBlockingOpsInProgress = CPA_FALSE;
}
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat.c b/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -244,7 +244,7 @@
*pCipherOffset = 0;
*pHashOffset = 0;
- /* for chaining can we use the optimised content descritor */
+ /* for chaining can we use the optimised content descriptor */
if (pSession->laCmdId == ICP_QAT_FW_LA_CMD_CIPHER_HASH ||
pSession->laCmdId == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
useOptimisedContentDesc =
@@ -297,7 +297,7 @@
(pSession->qatHashMode == ICP_QAT_HW_AUTH_MODE1)) {
/* we can only use the SHA1-mode1 in the SHRAM constants
* table when
- * we are using the opimised content desc */
+ * we are using the optimised content desc */
return CPA_FALSE;
}
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_cipher.c b/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_cipher.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_cipher.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_cipher.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -214,6 +214,11 @@
ICP_QAT_HW_CIPHER_ALGO_AES256 /* ICP_QAT_HW_AES_256_F8_KEY_SZ */
};
+/* This array must be kept aligned with CpaCySymCipherAlgorithm enum but
+ * offset by -1 as that enum starts at 1. LacSymQat_CipherGetCfgData()
+ * below relies on that alignment and uses that enum -1 to index into this
+ * array.
+ */
typedef struct _icp_qat_hw_cipher_info {
icp_qat_hw_cipher_algo_t algorithm;
icp_qat_hw_cipher_mode_t mode;
@@ -478,7 +483,7 @@
in this case, and add padding. It makes no sense
to force applications to provide such key length for couple reasons:
1. It won't be possible to distinguish between AES 192 and 256 based
- on key lenght only
+ on key length only
2. Only some modes of AES will use UCS slice, then application will
have to know which ones */
if (ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE == sliceType &&
@@ -542,7 +547,7 @@
sal_crypto_service_t *pService =
(sal_crypto_service_t *)pSession->pInstance;
- CpaCySymCipherAlgorithm cipherAlgorithm = 0;
+ int cipherIdx = 0;
icp_qat_hw_cipher_dir_t cipherDirection = 0;
/* Set defaults */
@@ -551,21 +556,33 @@
*pMode = ICP_QAT_HW_CIPHER_ECB_MODE;
*pDir = ICP_QAT_HW_CIPHER_ENCRYPT;
- /* decrease since it's numbered from 1 instead of 0 */
- cipherAlgorithm = pSession->cipherAlgorithm - 1;
+ /* offset index as CpaCySymCipherAlgorithm enum starts from 1, not from
+ * 0 */
+ cipherIdx = pSession->cipherAlgorithm - 1;
cipherDirection =
pSession->cipherDirection == CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT ?
ICP_QAT_HW_CIPHER_ENCRYPT :
ICP_QAT_HW_CIPHER_DECRYPT;
- *pAlgorithm = icp_qat_alg_info[cipherAlgorithm].algorithm;
- *pMode = icp_qat_alg_info[cipherAlgorithm].mode;
- *pDir = icp_qat_alg_info[cipherAlgorithm].dir[cipherDirection];
+ /* Boundary check against the last value in the algorithm enum */
+ if (!(pSession->cipherAlgorithm <= CPA_CY_SYM_CIPHER_SM4_CTR)) {
+ QAT_UTILS_LOG("Invalid cipherAlgorithm value\n");
+ return;
+ }
+
+ if (!(cipherDirection <= ICP_QAT_HW_CIPHER_DECRYPT)) {
+ QAT_UTILS_LOG("Invalid cipherDirection value\n");
+ return;
+ }
+
+ *pAlgorithm = icp_qat_alg_info[cipherIdx].algorithm;
+ *pMode = icp_qat_alg_info[cipherIdx].mode;
+ *pDir = icp_qat_alg_info[cipherIdx].dir[cipherDirection];
*pKey_convert =
- icp_qat_alg_info[cipherAlgorithm].key_convert[cipherDirection];
+ icp_qat_alg_info[cipherIdx].key_convert[cipherDirection];
- if (IS_KEY_DEP_NO != icp_qat_alg_info[cipherAlgorithm].isKeyLenDepend) {
- *pAlgorithm = icp_qat_alg_info[cipherAlgorithm]
+ if (IS_KEY_DEP_NO != icp_qat_alg_info[cipherIdx].isKeyLenDepend) {
+ *pAlgorithm = icp_qat_alg_info[cipherIdx]
.pAlgByKeySize[pSession->cipherKeyLenInBytes];
}
@@ -657,12 +674,11 @@
/* Special handling of AES 192 key for UCS slice.
UCS requires it to have 32 bytes - set is as targetKeyLen
in this case, and add padding. It makes no sense
- to force applications to provide such key length for couple
- reasons:
- 1. It won't be possible to distinguish between AES 192 and
- 256 based on key lenght only
- 2. Only some modes of AES will use UCS slice, then
- application will have to know which ones */
+ to force applications to provide such key length for couple reasons:
+ 1. It won't be possible to distinguish between AES 192 and 256 based
+ on key length only
+ 2. Only some modes of AES will use UCS slice, then application will
+ have to know which ones */
if (ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE == sliceType &&
ICP_QAT_HW_AES_192_KEY_SZ == targetKeyLenInBytes) {
targetKeyLenInBytes = ICP_QAT_HW_UCS_AES_192_KEY_SZ;
@@ -918,10 +934,10 @@
/* Populate the field with the contents of the buffer,
* zero field first as data may be smaller than the field */
- /* In case of XTS mode using UCS slice always embedd IV.
- * IV provided by user needs to be encrypted to calculate
- * initial tweak, use pCipherReqParams->u.cipher_IV_array as
- * destination buffer for tweak value */
+ /* In case of XTS mode using UCS slice always encrypt the embedded IV.
+ * IV provided by user needs to be encrypted to calculate initial tweak,
+ * use pCipherReqParams->u.cipher_IV_array as destination buffer for
+ * tweak value */
if (ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE ==
pSessionDesc->cipherSliceType &&
LAC_CIPHER_IS_XTS_MODE(pSessionDesc->cipherAlgorithm)) {
diff --git a/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_hash_defs_lookup.c b/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_hash_defs_lookup.c
--- a/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_hash_defs_lookup.c
+++ b/sys/dev/qat/qat_api/common/crypto/sym/qat/lac_sym_qat_hash_defs_lookup.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -42,7 +42,7 @@
CpaCySymHashAlgorithm hashAlgorithm;
/* hash algorithm */
lac_sym_qat_hash_defs_t hashDefs;
- /* hash defintions pointers */
+ /* hash definitions pointers */
} lac_sym_qat_hash_def_map_t;
/*
@@ -219,7 +219,7 @@
static lac_sym_qat_hash_alg_info_t polyInfo = { LAC_HASH_POLY_DIGEST_SIZE,
LAC_HASH_POLY_BLOCK_SIZE,
- NULL, /* intial state */
+ NULL, /* initial state */
LAC_HASH_POLY_STATE_SIZE };
static lac_sym_qat_hash_alg_info_t xcbcMacInfo = {
@@ -239,7 +239,7 @@
static lac_sym_qat_hash_alg_info_t aesCcmInfo = {
LAC_HASH_AES_CCM_DIGEST_SIZE,
LAC_HASH_AES_CCM_BLOCK_SIZE,
- NULL, /* intial state */
+ NULL, /* initial state */
0 /* state size */
};
diff --git a/sys/dev/qat/qat_api/common/ctrl/sal_compression.c b/sys/dev/qat/qat_api/common/ctrl/sal_compression.c
--- a/sys/dev/qat/qat_api/common/ctrl/sal_compression.c
+++ b/sys/dev/qat/qat_api/common/ctrl/sal_compression.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file sal_compression.c
@@ -371,9 +371,6 @@
SAL_SERVICE_GOOD_FOR_INIT(pCompressionService);
- pCompressionService->generic_service_info.state =
- SAL_SERVICE_STATE_INITIALIZING;
-
if (CPA_FALSE == pCompressionService->generic_service_info.is_dyn) {
section = icpGetProcessName();
}
@@ -1438,7 +1435,8 @@
pInstanceInfo2->isOffloaded = CPA_TRUE;
/* Get the instance name and part name from the config file */
dev = icp_adf_getAccelDevByAccelId(pCompressionService->pkgID);
- if (NULL == dev) {
+ if (NULL == dev ||
+ 0 == strnlen(dev->deviceName, ADF_DEVICE_TYPE_LENGTH + 1)) {
QAT_UTILS_LOG("Can not find device for the instance.\n");
LAC_OS_BZERO(pInstanceInfo2, sizeof(CpaInstanceInfo2));
return CPA_STATUS_FAIL;
diff --git a/sys/dev/qat/qat_api/common/ctrl/sal_crypto.c b/sys/dev/qat/qat_api/common/ctrl/sal_crypto.c
--- a/sys/dev/qat/qat_api/common/ctrl/sal_crypto.c
+++ b/sys/dev/qat/qat_api/common/ctrl/sal_crypto.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -73,6 +73,15 @@
#define NUM_CRYPTO_ASYM_RX_RINGS 1
#define NUM_CRYPTO_NRBG_RX_RINGS 1
+CpaStatus Lac_GetCyInstancesByType(
+ const CpaAccelerationServiceType accelerationServiceType,
+ Cpa16U numInstances,
+ CpaInstanceHandle *pInstances);
+
+CpaStatus Lac_GetCyNumInstancesByType(
+ const CpaAccelerationServiceType accelerationServiceType,
+ Cpa16U *pNumInstances);
+
static CpaInstanceHandle
Lac_CryptoGetFirstHandle(void)
{
@@ -88,7 +97,6 @@
return instHandle;
}
-
/* Function to release the sym handles. */
static CpaStatus
SalCtrl_SymReleaseTransHandle(sal_service_t *service)
@@ -116,7 +124,6 @@
return ret_status;
}
-
/*
* @ingroup sal_crypto
* Frees resources (memory and transhandles) if allocated
@@ -153,7 +160,6 @@
return status;
}
-
/**
***********************************************************************
* @ingroup SalCtrl
@@ -175,7 +181,6 @@
} \
} while (0)
-
/* Function that creates the Sym Handles. */
static CpaStatus
SalCtrl_SymCreateTransHandle(icp_accel_dev_t *device,
@@ -325,7 +330,6 @@
return ++offset;
}
-
static CpaStatus
SalCtrl_SymInit(icp_accel_dev_t *device, sal_service_t *service)
{
@@ -342,7 +346,6 @@
section = icpGetProcessName();
}
-
/* Register callbacks for the symmetric services
* (Hash, Cipher, Algorithm-Chaining) (returns void)*/
LacSymCb_CallbacksRegister();
@@ -581,7 +584,6 @@
section = icpGetProcessName();
}
-
/* Get Config Info: Accel Num, bank Num, packageID,
coreAffinity, nodeAffinity and response mode */
@@ -847,7 +849,6 @@
return CPA_STATUS_FAIL;
}
-
/* Free memory and transhandles */
switch (svc_type) {
case SAL_SERVICE_TYPE_CRYPTO_ASYM:
@@ -886,7 +887,6 @@
{
CpaStatus status = CPA_STATUS_SUCCESS;
-
LAC_CHECK_NULL_PARAM(pStatusText);
switch (errStatus) {
@@ -969,7 +969,6 @@
CpaStatus status = CPA_STATUS_SUCCESS;
sal_crypto_service_t *pService = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle = Lac_GetFirstHandle(SAL_SERVICE_TYPE_CRYPTO);
if (!instanceHandle) {
@@ -1021,7 +1020,6 @@
CpaStatus status = CPA_STATUS_SUCCESS;
sal_crypto_service_t *pService = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle = Lac_CryptoGetFirstHandle();
} else {
@@ -1066,7 +1064,6 @@
CpaStatus status = CPA_STATUS_SUCCESS;
sal_service_t *gen_handle = instanceHandle;
-
LAC_CHECK_NULL_PARAM(gen_handle);
gen_handle->notification_cb = pInstanceNotificationCb;
gen_handle->cb_tag = pCallbackTag;
@@ -1080,84 +1077,8 @@
CpaStatus
cpaCyGetNumInstances(Cpa16U *pNumInstances)
{
- CpaStatus status = CPA_STATUS_SUCCESS;
- CpaInstanceHandle cyInstanceHandle;
- CpaInstanceInfo2 info;
- icp_accel_dev_t **pAdfInsts = NULL;
- icp_accel_dev_t *dev_addr = NULL;
- sal_t *base_addr = NULL;
- sal_list_t *list_temp = NULL;
- Cpa16U num_accel_dev = 0;
- Cpa16U num_inst = 0;
- Cpa16U i = 0;
-
- LAC_CHECK_NULL_PARAM(pNumInstances);
-
- /* Get the number of accel_dev in the system */
- status = icp_amgr_getNumInstances(&num_accel_dev);
- LAC_CHECK_STATUS(status);
-
- /* Allocate memory to store addr of accel_devs */
- pAdfInsts =
- malloc(num_accel_dev * sizeof(icp_accel_dev_t *), M_QAT, M_WAITOK);
- num_accel_dev = 0;
- /* Get ADF to return all accel_devs that support either
- * symmetric or asymmetric crypto */
- status = icp_amgr_getAllAccelDevByCapabilities(
- (ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
- ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC),
- pAdfInsts,
- &num_accel_dev);
- if (CPA_STATUS_SUCCESS != status) {
- LAC_LOG_ERROR("No support for crypto\n");
- *pNumInstances = 0;
- free(pAdfInsts, M_QAT);
- return status;
- }
-
- for (i = 0; i < num_accel_dev; i++) {
- dev_addr = (icp_accel_dev_t *)pAdfInsts[i];
- if (NULL == dev_addr || NULL == dev_addr->pSalHandle) {
- continue;
- }
-
- base_addr = dev_addr->pSalHandle;
- list_temp = base_addr->crypto_services;
- while (NULL != list_temp) {
- cyInstanceHandle = SalList_getObject(list_temp);
- status = cpaCyInstanceGetInfo2(cyInstanceHandle, &info);
- if (CPA_STATUS_SUCCESS == status &&
- CPA_TRUE == info.isPolled) {
- num_inst++;
- }
- list_temp = SalList_next(list_temp);
- }
- list_temp = base_addr->asym_services;
- while (NULL != list_temp) {
- cyInstanceHandle = SalList_getObject(list_temp);
- status = cpaCyInstanceGetInfo2(cyInstanceHandle, &info);
- if (CPA_STATUS_SUCCESS == status &&
- CPA_TRUE == info.isPolled) {
- num_inst++;
- }
- list_temp = SalList_next(list_temp);
- }
- list_temp = base_addr->sym_services;
- while (NULL != list_temp) {
- cyInstanceHandle = SalList_getObject(list_temp);
- status = cpaCyInstanceGetInfo2(cyInstanceHandle, &info);
- if (CPA_STATUS_SUCCESS == status &&
- CPA_TRUE == info.isPolled) {
- num_inst++;
- }
- list_temp = SalList_next(list_temp);
- }
- }
- *pNumInstances = num_inst;
- free(pAdfInsts, M_QAT);
-
-
- return status;
+ return Lac_GetCyNumInstancesByType(CPA_ACC_SVC_TYPE_CRYPTO,
+ pNumInstances);
}
/**
@@ -1167,119 +1088,9 @@
CpaStatus
cpaCyGetInstances(Cpa16U numInstances, CpaInstanceHandle *pCyInstances)
{
- CpaStatus status = CPA_STATUS_SUCCESS;
- CpaInstanceHandle cyInstanceHandle;
- CpaInstanceInfo2 info;
- icp_accel_dev_t **pAdfInsts = NULL;
- icp_accel_dev_t *dev_addr = NULL;
- sal_t *base_addr = NULL;
- sal_list_t *list_temp = NULL;
- Cpa16U num_accel_dev = 0;
- Cpa16U num_allocated_instances = 0;
- Cpa16U index = 0;
- Cpa16U i = 0;
-
-
- LAC_CHECK_NULL_PARAM(pCyInstances);
- if (0 == numInstances) {
- LAC_INVALID_PARAM_LOG("NumInstances is 0");
- return CPA_STATUS_INVALID_PARAM;
- }
-
- /* Get the number of crypto instances */
- status = cpaCyGetNumInstances(&num_allocated_instances);
- if (CPA_STATUS_SUCCESS != status) {
- return status;
- }
-
- if (numInstances > num_allocated_instances) {
- QAT_UTILS_LOG("Only %d crypto instances available\n",
- num_allocated_instances);
- return CPA_STATUS_RESOURCE;
- }
-
- /* Get the number of accel devices in the system */
- status = icp_amgr_getNumInstances(&num_accel_dev);
- LAC_CHECK_STATUS(status);
-
- /* Allocate memory to store addr of accel_devs */
- pAdfInsts =
- malloc(num_accel_dev * sizeof(icp_accel_dev_t *), M_QAT, M_WAITOK);
-
- num_accel_dev = 0;
- /* Get ADF to return all accel_devs that support either
- * symmetric or asymmetric crypto */
- status = icp_amgr_getAllAccelDevByCapabilities(
- (ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
- ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC),
- pAdfInsts,
- &num_accel_dev);
- if (CPA_STATUS_SUCCESS != status) {
- LAC_LOG_ERROR("No support for crypto\n");
- free(pAdfInsts, M_QAT);
- return status;
- }
-
- for (i = 0; i < num_accel_dev; i++) {
- dev_addr = (icp_accel_dev_t *)pAdfInsts[i];
- /* Note dev_addr cannot be NULL here as numInstances = 0
- * is not valid and if dev_addr = NULL then index = 0 (which
- * is less than numInstances and status is set to _RESOURCE
- * above
- */
- base_addr = dev_addr->pSalHandle;
- if (NULL == base_addr) {
- continue;
- }
- list_temp = base_addr->crypto_services;
- while (NULL != list_temp) {
- if (index > (numInstances - 1)) {
- break;
- }
- cyInstanceHandle = SalList_getObject(list_temp);
- status = cpaCyInstanceGetInfo2(cyInstanceHandle, &info);
- list_temp = SalList_next(list_temp);
- if (CPA_STATUS_SUCCESS != status ||
- CPA_TRUE != info.isPolled) {
- continue;
- }
- pCyInstances[index] = cyInstanceHandle;
- index++;
- }
- list_temp = base_addr->asym_services;
- while (NULL != list_temp) {
- if (index > (numInstances - 1)) {
- break;
- }
- cyInstanceHandle = SalList_getObject(list_temp);
- status = cpaCyInstanceGetInfo2(cyInstanceHandle, &info);
- list_temp = SalList_next(list_temp);
- if (CPA_STATUS_SUCCESS != status ||
- CPA_TRUE != info.isPolled) {
- continue;
- }
- pCyInstances[index] = cyInstanceHandle;
- index++;
- }
- list_temp = base_addr->sym_services;
- while (NULL != list_temp) {
- if (index > (numInstances - 1)) {
- break;
- }
- cyInstanceHandle = SalList_getObject(list_temp);
- status = cpaCyInstanceGetInfo2(cyInstanceHandle, &info);
- list_temp = SalList_next(list_temp);
- if (CPA_STATUS_SUCCESS != status ||
- CPA_TRUE != info.isPolled) {
- continue;
- }
- pCyInstances[index] = cyInstanceHandle;
- index++;
- }
- }
- free(pAdfInsts, M_QAT);
-
- return status;
+ return Lac_GetCyInstancesByType(CPA_ACC_SVC_TYPE_CRYPTO,
+ numInstances,
+ pCyInstances);
}
/**
@@ -1359,7 +1170,6 @@
char valStr[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = { 0 };
char *section = DYN_SEC;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle = Lac_CryptoGetFirstHandle();
} else {
@@ -1423,9 +1233,10 @@
}
pInstanceInfo2->isOffloaded = CPA_TRUE;
- /* Get the instance name and part name*/
+ /* Get the instance name and part name */
dev = icp_adf_getAccelDevByAccelId(pCryptoService->pkgID);
- if (NULL == dev) {
+ if (NULL == dev ||
+ 0 == strnlen(dev->deviceName, ADF_DEVICE_TYPE_LENGTH + 1)) {
LAC_LOG_ERROR("Can not find device for the instance\n");
LAC_OS_BZERO(pInstanceInfo2, sizeof(CpaInstanceInfo2));
return CPA_STATUS_FAIL;
@@ -1474,7 +1285,6 @@
/* Verify Instance exists */
CpaInstanceHandle instanceHandle = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle = Lac_CryptoGetFirstHandle();
} else {
@@ -1634,7 +1444,6 @@
CpaInstanceHandle instanceHandle = NULL;
sal_service_t *pService = NULL;
-
if (CPA_INSTANCE_HANDLE_SINGLE == instanceHandle_in) {
instanceHandle = Lac_CryptoGetFirstHandle();
} else {
@@ -1756,7 +1565,6 @@
return status;
}
-
/**
******************************************************************************
* @ingroup cpaCyCommon
@@ -1910,7 +1718,6 @@
default:
LAC_LOG_ERROR("Invalid service type\n");
return NULL;
- break;
}
/* Only need 1 dev with crypto enabled - so check all devices*/
status = icp_amgr_getAllAccelDevByEachCapability(capabilities,
@@ -1978,7 +1785,6 @@
numInflightRequests);
}
-
CpaStatus
icp_sal_dp_SymGetInflightRequests(CpaInstanceHandle instanceHandle,
Cpa32U *maxInflightRequests,
@@ -1994,7 +1800,6 @@
numInflightRequests);
}
-
CpaStatus
icp_sal_setForceAEADMACVerify(CpaInstanceHandle instanceHandle,
CpaBoolean forceAEADMacVerify)
diff --git a/sys/dev/qat/qat_api/common/ctrl/sal_get_instances.c b/sys/dev/qat/qat_api/common/ctrl/sal_get_instances.c
--- a/sys/dev/qat/qat_api/common/ctrl/sal_get_instances.c
+++ b/sys/dev/qat/qat_api/common/ctrl/sal_get_instances.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
@@ -10,7 +10,9 @@
* @ingroup SalCtrl
*
* @description
- * This file contains the main function to get SAL instances.
+ * This file contains generic functions to get instances of a specified
+ * service type. Note these are complementary to the already existing
+ * service-specific functions.
*
*****************************************************************************/
@@ -34,19 +36,22 @@
#include "lac_mem.h"
#include "lac_list.h"
#include "lac_sal_types.h"
+#include "lac_sal_types_crypto.h"
/**
******************************************************************************
* @ingroup SalCtrl
* @description
- * Get either sym or asym instance number
+ * Get the total number of either sym, asym or cy instances
*****************************************************************************/
-static CpaStatus
-Lac_GetSingleCyNumInstances(
+CpaStatus
+Lac_GetCyNumInstancesByType(
const CpaAccelerationServiceType accelerationServiceType,
Cpa16U *pNumInstances)
{
CpaStatus status = CPA_STATUS_SUCCESS;
+ CpaInstanceHandle instanceHandle;
+ CpaInstanceInfo2 info;
icp_accel_dev_t **pAdfInsts = NULL;
icp_accel_dev_t *dev_addr = NULL;
sal_t *base_addr = NULL;
@@ -71,6 +76,12 @@
service = "sym";
break;
+ case CPA_ACC_SVC_TYPE_CRYPTO:
+ accel_capability = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+ service = "cy";
+ break;
+
default:
QAT_UTILS_LOG("Invalid service type\n");
return CPA_STATUS_INVALID_PARAM;
@@ -106,14 +117,48 @@
}
base_addr = dev_addr->pSalHandle;
- if (CPA_ACC_SVC_TYPE_CRYPTO_ASYM == accelerationServiceType) {
+ if (CPA_ACC_SVC_TYPE_CRYPTO == accelerationServiceType) {
+ list_temp = base_addr->crypto_services;
+ while (NULL != list_temp) {
+ instanceHandle = SalList_getObject(list_temp);
+ status = cpaCyInstanceGetInfo2(instanceHandle,
+ &info);
+ if (CPA_STATUS_SUCCESS == status &&
+ CPA_TRUE == info.isPolled) {
+ num_inst++;
+ }
+ list_temp = SalList_next(list_temp);
+ }
+ }
+
+ if (CPA_ACC_SVC_TYPE_CRYPTO_ASYM == accelerationServiceType ||
+ CPA_ACC_SVC_TYPE_CRYPTO == accelerationServiceType) {
list_temp = base_addr->asym_services;
- } else {
- list_temp = base_addr->sym_services;
+ while (NULL != list_temp) {
+ instanceHandle = SalList_getObject(list_temp);
+ status = cpaCyInstanceGetInfo2(instanceHandle,
+ &info);
+ if (CPA_STATUS_SUCCESS == status &&
+ CPA_TRUE == info.isPolled) {
+ num_inst++;
+ }
+ list_temp = SalList_next(list_temp);
+ }
}
- while (NULL != list_temp) {
- num_inst++;
- list_temp = SalList_next(list_temp);
+
+ if (CPA_ACC_SVC_TYPE_CRYPTO_SYM == accelerationServiceType ||
+ CPA_ACC_SVC_TYPE_CRYPTO == accelerationServiceType) {
+ list_temp = base_addr->sym_services;
+ while (NULL != list_temp) {
+ instanceHandle = SalList_getObject(list_temp);
+ status = cpaCyInstanceGetInfo2(instanceHandle,
+ &info);
+ if (CPA_STATUS_SUCCESS == status &&
+ CPA_TRUE == info.isPolled) {
+ num_inst++;
+ }
+ list_temp = SalList_next(list_temp);
+ }
}
}
@@ -127,15 +172,17 @@
******************************************************************************
* @ingroup SalCtrl
* @description
- * Get either sym or asym instance
+ * Get either sym, asym or cy instance
*****************************************************************************/
-static CpaStatus
-Lac_GetSingleCyInstances(
+CpaStatus
+Lac_GetCyInstancesByType(
const CpaAccelerationServiceType accelerationServiceType,
Cpa16U numInstances,
CpaInstanceHandle *pInstances)
{
CpaStatus status = CPA_STATUS_SUCCESS;
+ CpaInstanceHandle instanceHandle = NULL;
+ CpaInstanceInfo2 info;
icp_accel_dev_t **pAdfInsts = NULL;
icp_accel_dev_t *dev_addr = NULL;
sal_t *base_addr = NULL;
@@ -163,14 +210,21 @@
accel_capability = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
service = "sym";
break;
+
+ case CPA_ACC_SVC_TYPE_CRYPTO:
+ accel_capability = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+ service = "cy";
+ break;
+
default:
QAT_UTILS_LOG("Invalid service type\n");
return CPA_STATUS_INVALID_PARAM;
}
/* Get the number of instances */
- status = cpaGetNumInstances(accelerationServiceType,
- &num_allocated_instances);
+ status = Lac_GetCyNumInstancesByType(accelerationServiceType,
+ &num_allocated_instances);
if (CPA_STATUS_SUCCESS != status) {
return status;
}
@@ -216,17 +270,63 @@
continue;
}
- if (CPA_ACC_SVC_TYPE_CRYPTO_ASYM == accelerationServiceType)
+ if (CPA_ACC_SVC_TYPE_CRYPTO == accelerationServiceType) {
+ list_temp = base_addr->crypto_services;
+ while (NULL != list_temp) {
+ if (index > (numInstances - 1))
+ break;
+
+ instanceHandle = SalList_getObject(list_temp);
+ status = cpaCyInstanceGetInfo2(instanceHandle,
+ &info);
+ list_temp = SalList_next(list_temp);
+ if (CPA_STATUS_SUCCESS != status ||
+ CPA_TRUE != info.isPolled) {
+ continue;
+ }
+ pInstances[index] = instanceHandle;
+ index++;
+ }
+ }
+
+ if (CPA_ACC_SVC_TYPE_CRYPTO_ASYM == accelerationServiceType ||
+ CPA_ACC_SVC_TYPE_CRYPTO == accelerationServiceType) {
list_temp = base_addr->asym_services;
- else
- list_temp = base_addr->sym_services;
- while (NULL != list_temp) {
- if (index > (numInstances - 1))
- break;
+ while (NULL != list_temp) {
+ if (index > (numInstances - 1))
+ break;
+
+ instanceHandle = SalList_getObject(list_temp);
+ status = cpaCyInstanceGetInfo2(instanceHandle,
+ &info);
+ list_temp = SalList_next(list_temp);
+ if (CPA_STATUS_SUCCESS != status ||
+ CPA_TRUE != info.isPolled) {
+ continue;
+ }
+ pInstances[index] = instanceHandle;
+ index++;
+ }
+ }
- pInstances[index] = SalList_getObject(list_temp);
- list_temp = SalList_next(list_temp);
- index++;
+ if (CPA_ACC_SVC_TYPE_CRYPTO_SYM == accelerationServiceType ||
+ CPA_ACC_SVC_TYPE_CRYPTO == accelerationServiceType) {
+ list_temp = base_addr->sym_services;
+ while (NULL != list_temp) {
+ if (index > (numInstances - 1))
+ break;
+
+ instanceHandle = SalList_getObject(list_temp);
+ status = cpaCyInstanceGetInfo2(instanceHandle,
+ &info);
+ list_temp = SalList_next(list_temp);
+ if (CPA_STATUS_SUCCESS != status ||
+ CPA_TRUE != info.isPolled) {
+ continue;
+ }
+ pInstances[index] = instanceHandle;
+ index++;
+ }
}
}
free(pAdfInsts, M_QAT);
@@ -242,16 +342,24 @@
cpaGetNumInstances(const CpaAccelerationServiceType accelerationServiceType,
Cpa16U *pNumInstances)
{
+ LAC_CHECK_NULL_PARAM(pNumInstances);
+
switch (accelerationServiceType) {
case CPA_ACC_SVC_TYPE_CRYPTO_ASYM:
case CPA_ACC_SVC_TYPE_CRYPTO_SYM:
- return Lac_GetSingleCyNumInstances(accelerationServiceType,
- pNumInstances);
case CPA_ACC_SVC_TYPE_CRYPTO:
- return cpaCyGetNumInstances(pNumInstances);
+ return Lac_GetCyNumInstancesByType(accelerationServiceType,
+ pNumInstances);
+
case CPA_ACC_SVC_TYPE_DATA_COMPRESSION:
return cpaDcGetNumInstances(pNumInstances);
+ case CPA_ACC_SVC_TYPE_PATTERN_MATCH:
+ case CPA_ACC_SVC_TYPE_RAID:
+ case CPA_ACC_SVC_TYPE_XML:
+ QAT_UTILS_LOG("Unsupported service type\n");
+ return CPA_STATUS_UNSUPPORTED;
+
default:
QAT_UTILS_LOG("Invalid service type\n");
*pNumInstances = 0;
@@ -268,18 +376,25 @@
Cpa16U numInstances,
CpaInstanceHandle *pInstances)
{
+ LAC_CHECK_NULL_PARAM(pInstances);
+
switch (accelerationServiceType) {
case CPA_ACC_SVC_TYPE_CRYPTO_ASYM:
case CPA_ACC_SVC_TYPE_CRYPTO_SYM:
- return Lac_GetSingleCyInstances(accelerationServiceType,
+ case CPA_ACC_SVC_TYPE_CRYPTO:
+ return Lac_GetCyInstancesByType(accelerationServiceType,
numInstances,
pInstances);
- case CPA_ACC_SVC_TYPE_CRYPTO:
- return cpaCyGetInstances(numInstances, pInstances);
case CPA_ACC_SVC_TYPE_DATA_COMPRESSION:
return cpaDcGetInstances(numInstances, pInstances);
+ case CPA_ACC_SVC_TYPE_PATTERN_MATCH:
+ case CPA_ACC_SVC_TYPE_RAID:
+ case CPA_ACC_SVC_TYPE_XML:
+ QAT_UTILS_LOG("Unsupported service type\n");
+ return CPA_STATUS_UNSUPPORTED;
+
default:
QAT_UTILS_LOG("Invalid service type\n");
return CPA_STATUS_INVALID_PARAM;
diff --git a/sys/dev/qat/qat_api/common/include/lac_common.h b/sys/dev/qat/qat_api/common/include/lac_common.h
--- a/sys/dev/qat/qat_api/common/include/lac_common.h
+++ b/sys/dev/qat/qat_api/common/include/lac_common.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file lac_common.h Common macros
@@ -574,7 +574,6 @@
******************************************************************************/
#define LAC_QUADWORDS_TO_BYTES(x) ((x) << 3)
-
/******************************************************************************/
/*
diff --git a/sys/dev/qat/qat_api/common/include/lac_hooks.h b/sys/dev/qat/qat_api/common/include/lac_hooks.h
--- a/sys/dev/qat/qat_api/common/include/lac_hooks.h
+++ b/sys/dev/qat/qat_api/common/include/lac_hooks.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*******************************************************************************
* @file lac_hooks.h
@@ -9,7 +9,7 @@
* @ingroup LacCommon
*
* Component Init/Shutdown functions. These are:
- * - an init function which is called during the intialisation sequence,
+ * - an init function which is called during the initialisation sequence,
* - a shutdown function which is called by the overall shutdown function,
*
******************************************************************************/
diff --git a/sys/dev/qat/qat_api/common/include/lac_mem.h b/sys/dev/qat/qat_api/common/include/lac_mem.h
--- a/sys/dev/qat/qat_api/common/include/lac_mem.h
+++ b/sys/dev/qat/qat_api/common/include/lac_mem.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
* @file lac_mem.h
@@ -351,7 +351,7 @@
* results in following entry:
* static const unsigned int highest_bit_of_lac_mem_blk_t = 3
*
- * CAUTION!!
+ * CAUTION!
* Macro is prepared only for type names NOT-containing ANY
* special characters. Types as amongst others:
* - void *
@@ -481,7 +481,7 @@
* This is because pInternalMem describes the memory that will be sent to
* QAT.
*
- * The caller must keep the original buffer pointer. The alllocated buffer
+ * The caller must keep the original buffer pointer. The allocated buffer
*is
* freed (as necessary) using icp_LacBufferRestore().
*
diff --git a/sys/dev/qat/qat_api/common/include/lac_mem_pools.h b/sys/dev/qat/qat_api/common/include/lac_mem_pools.h
--- a/sys/dev/qat/qat_api/common/include/lac_mem_pools.h
+++ b/sys/dev/qat/qat_api/common/include/lac_mem_pools.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
* @file lac_mem_pools.h
@@ -15,20 +15,20 @@
* This component is designed as a set of utility functions for the
* creation of pre-allocated memory pools. Each pool will be created using OS
* memory with a user specified number of elements, element size and element
- * alignment(alignmnet is at byte granularity).
+ * alignment(alignment is at byte granularity).
* @lld_dependencies
* These utilities rely on QAT Utils for locking mechanisms and memory
- *allocation
+ * allocation
* @lld_initialisation
* Pool creation needs to be done by each component. There is no specific
* initialisation required for this feature.
* @lld_module_algorithms
- * The following is a diagram of how the memory is layed out for each block
+ * The following is a diagram of how the memory is laid out for each block
* in a pool. Each element must be aligned on the boundary requested for in the
* create call. In order to hide the management of the pools from the user,
* the memory block data is hidden prior to the
* data pointer. This way it can be accessed easily on a free call with pointer
- * arithmatic. The Padding at the start is simply there for alignment and is
+ * arithmetic. The Padding at the start is simply there for alignment and is
* unused in the pools.
*
* -------------------------------------------------------
@@ -73,7 +73,7 @@
CpaBoolean isInUse;
/**< indicates if the pool item is in use */
struct lac_mem_blk_s *pNext;
- /**< link to next blcok in the pool */
+ /**< link to next block in the pool */
struct lac_mem_pool_hdr_s *pPoolID;
/**< identifier of the pool that this block was allocated from */
} lac_mem_blk_t;
@@ -82,7 +82,7 @@
(((lac_mem_blk_t *)((LAC_ARCH_UINT)pVirtAddr - sizeof(lac_mem_blk_t))) \
->physDataPtr)
/**< @ingroup LacMemPool
- * macro for retreiving the physical address of the memory block. */
+ * macro for retrieving the physical address of the memory block. */
#define LAC_MEM_POOL_INIT_POOL_ID 0
/**< @ingroup LacMemPool
diff --git a/sys/dev/qat/qat_api/common/include/lac_sal.h b/sys/dev/qat/qat_api/common/include/lac_sal.h
--- a/sys/dev/qat/qat_api/common/include/lac_sal.h
+++ b/sys/dev/qat/qat_api/common/include/lac_sal.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file lac_sal.h
@@ -57,7 +57,7 @@
* @ingroup SalCtl
* @description
* This macro goes through the 'list' passed in as a parameter. For each
- * element found in the list, it peforms a cast to the type of the element
+ * element found in the list, it performs a cast to the type of the element
* given by the 'type' parameter. Finally, it calls the function given by
* the 'function' parameter, passing itself and the device as parameters.
*
@@ -114,7 +114,7 @@
* @ingroup SalCtl
* @description
* This macro goes through the 'list' passed in as a parameter. For each
- * element found in the list, it peforms a cast to the type of the element
+ * element found in the list, it performs a cast to the type of the element
* given by the 'type' parameter. Finally, it checks the state of the
* element and if it is in state 'state_check' then it calls the
* function given by the 'function' parameter, passing itself
@@ -212,7 +212,7 @@
* @ingroup SalCtrl
* @description
* This function is used to stop an instance of crypto service.
- * It checks for inflight messages to the FW. If no messages are pending
+ * It checks for in-flight messages to the FW. If no messages are pending
* it returns success. If messages are pending it returns retry.
*
* @context
@@ -340,7 +340,7 @@
* @ingroup SalCtrl
* @description
* This function is used to stop an instance of compression service.
- * It checks for inflight messages to the FW. If no messages are pending
+ * It checks for in-flight messages to the FW. If no messages are pending
* it returns success. If messages are pending it returns retry.
*
* @context
diff --git a/sys/dev/qat/qat_api/common/include/lac_sal_types.h b/sys/dev/qat/qat_api/common/include/lac_sal_types.h
--- a/sys/dev/qat/qat_api/common/include/lac_sal_types.h
+++ b/sys/dev/qat/qat_api/common/include/lac_sal_types.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
* @file lac_sal_types.h
@@ -195,8 +195,8 @@
* @param[in] pService pointer to service instance
* @param[in] service_type service type to check againstx.
*
- * @return CPA_STATUS_FAIL Parameter is incorrect type
- *
+ * @return CPA_STATUS_FAIL Parameter is incorrect type
+ *
******************************************************************************/
#define SAL_CHECK_INSTANCE_TYPE(pService, service_type) \
do { \
diff --git a/sys/dev/qat/qat_api/common/include/lac_sal_types_crypto.h b/sys/dev/qat/qat_api/common/include/lac_sal_types_crypto.h
--- a/sys/dev/qat/qat_api/common/include/lac_sal_types_crypto.h
+++ b/sys/dev/qat/qat_api/common/include/lac_sal_types_crypto.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
@@ -187,4 +187,25 @@
CpaInstanceHandle Lac_GetFirstHandle(sal_service_type_t svc_type);
+/**
+ ******************************************************************************
+ * @ingroup SalCtrl
+ * @description
+ * Get the total number of either sym, asym or cy instances
+ *****************************************************************************/
+CpaStatus Lac_GetCyNumInstancesByType(
+ const CpaAccelerationServiceType accelerationServiceType,
+ Cpa16U *pNumInstances);
+
+/**
+ ******************************************************************************
+ * @ingroup SalCtrl
+ * @description
+ * Get either sym, asym or cy instance
+ *****************************************************************************/
+CpaStatus Lac_GetCyInstancesByType(
+ const CpaAccelerationServiceType accelerationServiceType,
+ Cpa16U numInstances,
+ CpaInstanceHandle *pInstances);
+
#endif /*LAC_SAL_TYPES_CRYPTO_H_*/
diff --git a/sys/dev/qat/qat_api/common/include/sal_qat_cmn_msg.h b/sys/dev/qat/qat_api/common/include/sal_qat_cmn_msg.h
--- a/sys/dev/qat/qat_api/common/include/sal_qat_cmn_msg.h
+++ b/sys/dev/qat/qat_api/common/include/sal_qat_cmn_msg.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file sal_qat_cmn_msg.c
@@ -147,7 +147,7 @@
* section of the Request Msg.
*
* @param[in] pMsg Pointer to 128B Request Msg buffer.
- * @param[in] pContentDescInfo content descripter info.
+ * @param[in] pContentDescInfo content descriptor info.
*
* @return
* none
diff --git a/sys/dev/qat/qat_api/common/include/sal_types_compression.h b/sys/dev/qat/qat_api/common/include/sal_types_compression.h
--- a/sys/dev/qat/qat_api/common/include/sal_types_compression.h
+++ b/sys/dev/qat/qat_api/common/include/sal_types_compression.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
* @file sal_types_compression.h
@@ -24,6 +24,8 @@
#define DC_NUM_RX_RINGS (1)
#define DC_NUM_COMPRESSION_LEVELS (CPA_DC_L12)
+#define MAX_SGL_NUM 0x10000
+
/**
*****************************************************************************
* @ingroup SalCtrl
diff --git a/sys/dev/qat/qat_api/common/qat_comms/sal_qat_cmn_msg.c b/sys/dev/qat/qat_api/common/qat_comms/sal_qat_cmn_msg.c
--- a/sys/dev/qat/qat_api/common/qat_comms/sal_qat_cmn_msg.c
+++ b/sys/dev/qat/qat_api/common/qat_comms/sal_qat_cmn_msg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file sal_qat_cmn_msg.h
@@ -145,7 +145,7 @@
* icp_qat_fw_comn_req_hdr_cd_pars_t section of the Request Msg.
*
* @param[in] pMsg Pointer to 128B Request Msg buffer.
- * @param[in] pContentDescInfo content descripter info.
+ * @param[in] pContentDescInfo content descriptor info.
*
* @return
* none
diff --git a/sys/dev/qat/qat_api/common/utils/lac_buffer_desc.c b/sys/dev/qat/qat_api/common/utils/lac_buffer_desc.c
--- a/sys/dev/qat/qat_api/common/utils/lac_buffer_desc.c
+++ b/sys/dev/qat/qat_api/common/utils/lac_buffer_desc.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file lac_buffer_desc.c Utility functions for setting buffer descriptors
@@ -31,7 +31,7 @@
/* Invalid physical address value */
#define INVALID_PHYSICAL_ADDRESS 0
-/* Indicates what type of buffer writes need to be perfomed */
+/* Indicates what type of buffer writes need to be performed */
typedef enum lac_buff_write_op_e {
WRITE_NORMAL = 0,
WRITE_AND_GET_SIZE,
@@ -153,7 +153,7 @@
/* This function implements the buffer description writes for the traditional
* APIs Zero length buffers are allowed, should be used for CHA-CHA-POLY and
- * GCM aglorithms */
+ * GCM algorithms */
CpaStatus
LacBuffDesc_BufferListDescWriteAndAllowZeroBuffer(
const CpaBufferList *pUserBufferList,
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file icp_qat_fw.h
@@ -241,13 +241,12 @@
* field */
uint32_t src_length;
- /** < Length of source flat buffer incase src buffer
+ /** < Length of source flat buffer in case src buffer
* type is flat */
uint32_t dst_length;
- /** < Length of source flat buffer incase dst buffer
+ /** < Length of source flat buffer in case dst buffer
* type is flat */
-
} icp_qat_fw_comn_req_mid_t;
/**
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_comp.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_comp.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_comp.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_comp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file icp_qat_fw_comp.h
@@ -47,7 +47,6 @@
} icp_qat_fw_comp_cmd_id_t;
-
/*
* REQUEST FLAGS IN COMMON COMPRESSION
* In common message it is named as SERVICE SPECIFIC FLAGS.
@@ -65,7 +64,6 @@
* are don't care. i.e., these features are removed from QAT 2.0.
*/
-
/**< Flag usage */
#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
@@ -410,7 +408,6 @@
((crc & ICP_QAT_FW_COMP_CRC_MODE_MASK) \
<< ICP_QAT_FW_COMP_CRC_MODE_BITPOS))
-
/*
* REQUEST FLAGS IN REQUEST PARAMETERS COMPRESSION
*
@@ -423,7 +420,6 @@
* +=====+-----+----- + --- + ----+-----+ --- + ----- + --- + ---- + -- + -- +
*/
-
/**
*****************************************************************************
* @ingroup icp_qat_fw_comp
@@ -446,18 +442,17 @@
ICP_QAT_FW_COMP_20_CMD_LZ4S_DECOMPRESS = 6,
/*!< LZ4S Decompress Request */
- ICP_QAT_FW_COMP_20_CMD_XP10_COMPRESS = 7,
- /*!< XP10 Compress Request -- Placeholder */
+ ICP_QAT_FW_COMP_20_CMD_RESERVED_1 = 7,
+ /*!< Placeholder */
- ICP_QAT_FW_COMP_20_CMD_XP10_DECOMPRESS = 8,
- /*!< XP10 Decompress Request -- Placeholder */
+ ICP_QAT_FW_COMP_20_CMD_RESERVED_2 = 8,
+ /*!< Placeholder */
ICP_QAT_FW_COMP_20_CMD_DELIMITER
/**< Delimiter type */
} icp_qat_fw_comp_20_cmd_id_t;
-
/*
* REQUEST FLAGS IN REQUEST PARAMETERS COMPRESSION
*
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_la.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_la.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_la.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_la.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file icp_qat_fw_la.h
@@ -451,7 +451,7 @@
* the case of partial processing. See the HLD for further details
*
* + ====== + ------------------------- + ----------------------- +
- * | Parial | Prefix Addr | Hash State Sz |
+ * | Partial| Prefix Addr | Hash State Sz |
* | State | | |
* + ====== + ------------------------- + ----------------------- +
* | FULL | Points to the prefix data | Prefix size as below. |
@@ -509,7 +509,7 @@
* is required
* @param ciphIV Cipher IV field contents
* @param ciphcfg Cipher/Auth Config offset type
- * @param partial Inidicate if the packet is a partial part
+ * @param partial Indicate if the packet is a partial part
*
*****************************************************************************/
#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, \
@@ -1042,7 +1042,7 @@
/**< LW 27 */
uint8_t cipher_state_sz;
/**< State size in quad words of the cipher algorithm used in this
- * session. Set to zero if the algorithm doesnt provide any state */
+ * session. Set to zero if the algorithm doesn't provide any state */
uint8_t cipher_key_sz;
/**< Key size in quad words of the cipher algorithm used in this session
@@ -1179,7 +1179,7 @@
/**< LW 27 */
uint8_t cipher_state_sz;
/**< State size in quad words of the cipher algorithm used in this
- * session. Set to zero if the algorithm doesnt provide any state */
+ * session. Set to zero if the algorithm doesn't provide any state */
uint8_t cipher_key_sz;
/**< Key size in quad words of the cipher algorithm used in this session
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp.h
@@ -1,9 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/* --- (Automatically generated (build v. 2.7), do not modify manually) --- */
-
/**
* @file icp_qat_fw_mmp.h
* @defgroup icp_qat_fw_mmp ICP QAT FW MMP Processing Definitions
@@ -12,10 +11,9 @@
* @brief
* This file documents the external interfaces that the QAT FW running
* on the QAT Acceleration Engine provides to clients wanting to
- * accelerate crypto assymetric applications
+ * accelerate crypto asymmetric applications
*/
-
#ifndef __ICP_QAT_FW_MMP__
#define __ICP_QAT_FW_MMP__
@@ -33,12 +31,12 @@
* Local constants
**************************************************************************
*/
-#define ICP_QAT_FW_PKE_INPUT_COUNT_MAX 7
+#define ICP_QAT_FW_PKE_INPUT_COUNT_MAX 7
/**< @ingroup icp_qat_fw_pke
- * Maximum number of input paramaters in all PKE request */
-#define ICP_QAT_FW_PKE_OUTPUT_COUNT_MAX 5
+ * Maximum number of input parameters in all PKE request */
+#define ICP_QAT_FW_PKE_OUTPUT_COUNT_MAX 5
/**< @ingroup icp_qat_fw_pke
- * Maximum number of output paramaters in all PKE request */
+ * Maximum number of output parameters in all PKE request */
/**
* @ingroup icp_qat_fw_mmp
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp_ids.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp_ids.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp_ids.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_mmp_ids.h
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
-
+/* Copyright(c) 2007-2025 Intel Corporation */
/* --- (Automatically generated (relocation v. 1.3), do not modify manually) --- */
@@ -11,7 +10,7 @@
* @brief
* This file documents the external interfaces that the QAT FW running
* on the QAT Acceleration Engine provides to clients wanting to
- * accelerate crypto assymetric applications
+ * accelerate crypto asymmetric applications
*/
#ifndef __ICP_QAT_FW_MMP_IDS__
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_pke.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_pke.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_pke.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_fw_pke.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
* @file icp_qat_fw_pke.h
* @defgroup icp_qat_fw_pke ICP QAT FW PKE Processing Definitions
@@ -8,7 +8,7 @@
* @brief
* This file documents the external interfaces that the QAT FW running
* on the QAT Acceleration Engine provides to clients wanting to
- * accelerate crypto assymetric applications
+ * accelerate crypto asymmetric applications
*/
#ifndef _ICP_QAT_FW_PKE_
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_hw.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_hw.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_hw.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_hw.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file icp_qat_hw.h
@@ -163,7 +163,7 @@
#define QAT_AUTH_MODE_MASK 0xF
/**< @ingroup icp_qat_hw_defs
- * Four bit mask used for determing the Auth mode */
+ * Four bit mask used for determining the Auth mode */
#define QAT_AUTH_ALGO_BITPOS 0
/**< @ingroup icp_qat_hw_defs
@@ -1277,7 +1277,7 @@
#define QAT_TRNG_TEST_STATUS_MASK 0x1
/**< @ingroup icp_qat_hw_defs
- * Mask of one bit used to determine the TRNG Test staus */
+ * Mask of one bit used to determine the TRNG Test status */
#define QAT_TRNG_TEST_STATUS_BITPOS 1
/**< @ingroup icp_qat_hw_defs
diff --git a/sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h b/sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
--- a/sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
+++ b/sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
*****************************************************************************
* @file icp_qat_hw_2x_comp.h
@@ -17,7 +17,6 @@
#include "icp_qat_hw_20_comp_defs.h" /* For HW definitions */
#include "icp_qat_fw.h" /* For Set Field Macros. */
-
#define BYTE_SWAP_32 __builtin_bswap32
/**
diff --git a/sys/dev/qat/qat_api/include/cpa.h b/sys/dev/qat/qat_api/include/cpa.h
--- a/sys/dev/qat/qat_api/include/cpa.h
+++ b/sys/dev/qat/qat_api/include/cpa.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/cpa_dev.h b/sys/dev/qat/qat_api/include/cpa_dev.h
--- a/sys/dev/qat/qat_api/include/cpa_dev.h
+++ b/sys/dev/qat/qat_api/include/cpa_dev.h
@@ -1,14 +1,14 @@
-/****************************************************************************
+/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
@@ -101,9 +101,9 @@
CpaBoolean dcEnabled;
/**< Compression service enabled */
CpaBoolean cySymEnabled;
- /**< Symetric crypto service enabled */
+ /**< Symmetric crypto service enabled */
CpaBoolean cyAsymEnabled;
- /**< Asymetric crypto service enabled */
+ /**< Asymmetric crypto service enabled */
CpaBoolean inlineEnabled;
/**< Inline service enabled */
Cpa32U deviceMemorySizeAvailable;
diff --git a/sys/dev/qat/qat_api/include/cpa_types.h b/sys/dev/qat/qat_api/include/cpa_types.h
--- a/sys/dev/qat/qat_api/include/cpa_types.h
+++ b/sys/dev/qat/qat_api/include/cpa_types.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/dc/cpa_dc.h b/sys/dev/qat/qat_api/include/dc/cpa_dc.h
--- a/sys/dev/qat/qat_api/include/dc/cpa_dc.h
+++ b/sys/dev/qat/qat_api/include/dc/cpa_dc.h
@@ -1,14 +1,14 @@
-/****************************************************************************
+/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
@@ -135,6 +135,7 @@
(CPA_DC_API_VERSION_NUM_MAJOR == major && \
CPA_DC_API_VERSION_NUM_MINOR < minor))
+
/**
*****************************************************************************
* @ingroup cpaDc
@@ -999,7 +1000,7 @@
/**< CRC32 calculated on the input buffer during compression
* requests and on the output buffer during decompression requests. */
Cpa32U adler32;
- /**< ADLER32 calculated on the input buffer during compression
+ /**< Adler32 calculated on the input buffer during compression
* requests and on the output buffer during decompression requests. */
CpaIntegrityCrc integrityCrc;
/**< 32bit Integrity CRCs */
@@ -1289,7 +1290,7 @@
* This function will reset the internal xxHash state maintained within a
* session. This would be used in conjunction with the
* CpaDcSessionSetupData.accumulateXXHash flag being set to TRUE for this
- * session. It will enable reseting (reinitialising) just the xxHash
+ * session. It will enable resetting (reinitialising) just the xxHash
* calculation back to the state when the session was first initialised.
*
* @context
@@ -1761,7 +1762,7 @@
* session, the checksum passed to cpaDcCompressData should be set to the
* checksum value produced by the previous call to cpaDcCompressData().
* When the last block of input data is passed to cpaDcCompressData(), the
- * flush flag should be set to CP_DC_FLUSH_FINAL. This will cause the BFINAL
+ * flush flag should be set to CPA_DC_FLUSH_FINAL. This will cause the BFINAL
* bit to be set in a deflate stream. It is the responsibility of the calling
* application to maintain overall lengths across the stateless requests
* and to pass the checksum produced by one request into the next request.
@@ -2286,7 +2287,7 @@
* - Content size = 0
* - Dictionary ID = 0
* - Header checksum = 1 byte representing the second byte of the
- * XXH32 of the frame decriptor field.
+ * XXH32 of the frame descriptor field.
*
* The counter parameter will be set to the number of bytes added to the
* buffer. The pData will be not be changed.
diff --git a/sys/dev/qat/qat_api/include/dc/cpa_dc_bp.h b/sys/dev/qat/qat_api/include/dc/cpa_dc_bp.h
--- a/sys/dev/qat/qat_api/include/dc/cpa_dc_bp.h
+++ b/sys/dev/qat/qat_api/include/dc/cpa_dc_bp.h
@@ -1,14 +1,14 @@
-/****************************************************************************
+/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/dc/cpa_dc_chain.h b/sys/dev/qat/qat_api/include/dc/cpa_dc_chain.h
--- a/sys/dev/qat/qat_api/include/dc/cpa_dc_chain.h
+++ b/sys/dev/qat/qat_api/include/dc/cpa_dc_chain.h
@@ -1,8 +1,8 @@
-/****************************************************************************
+/***************************************************************************
*
* BSD LICENSE
*
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -77,21 +77,21 @@
*****************************************************************************/
typedef enum _CpaDcChainOperations
{
- CPA_DC_CHAIN_COMPRESS_THEN_HASH,
+ CPA_DC_CHAIN_COMPRESS_THEN_HASH = 0,
/**< 2 operations for chaining:
* 1st operation is to perform compression on plain text
* 2nd operation is to perform hash on compressed text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for compression setup data
* 2nd entry is for hash setup data*/
- CPA_DC_CHAIN_COMPRESS_THEN_ENCRYPT,
+ CPA_DC_CHAIN_COMPRESS_THEN_ENCRYPT = 1,
/**< 2 operations for chaining:
* 1st operation is to perform compression on plain text
* 2nd operation is to perform encryption on compressed text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for compression setup data
* 2nd entry is for encryption setup data*/
- CPA_DC_CHAIN_COMPRESS_THEN_HASH_ENCRYPT,
+ CPA_DC_CHAIN_COMPRESS_THEN_HASH_ENCRYPT = 2,
/**< 2 operations for chaining:
* 1st operation is to perform compression on plain text
* 2nd operation is to perform hash on compressed text and
@@ -99,7 +99,7 @@
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for compression setup data
* 2nd entry is for hash and encryption setup data*/
- CPA_DC_CHAIN_COMPRESS_THEN_ENCRYPT_HASH,
+ CPA_DC_CHAIN_COMPRESS_THEN_ENCRYPT_HASH = 3,
/**< 2 operations for chaining:
* 1st operation is to perform compression on plain text
* 2nd operation is to perform encryption on compressed text and
@@ -107,35 +107,35 @@
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for compression setup data
* 2nd entry is for encryption and hash setup data*/
- CPA_DC_CHAIN_COMPRESS_THEN_AEAD,
+ CPA_DC_CHAIN_COMPRESS_THEN_AEAD = 4,
/**< 2 operations for chaining:
* 1st operation is to perform compression on plain text
* 2nd operation is to perform AEAD encryption on compressed text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for compression setup data
* 2nd entry is for AEAD encryption setup data*/
- CPA_DC_CHAIN_HASH_THEN_COMPRESS,
+ CPA_DC_CHAIN_HASH_THEN_COMPRESS = 5,
/**< 2 operations for chaining:
* 1st operation is to perform hash on plain text
* 2nd operation is to perform compression on plain text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for hash setup data
* 2nd entry is for compression setup data*/
- CPA_DC_CHAIN_HASH_VERIFY_THEN_DECOMPRESS,
+ CPA_DC_CHAIN_HASH_VERIFY_THEN_DECOMPRESS = 6,
/**< 2 operations for chaining:
* 1st operation is to perform hash verify on compressed text
* 2nd operation is to perform decompression on compressed text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for hash setup data
* 2nd entry is for decompression setup data*/
- CPA_DC_CHAIN_DECRYPT_THEN_DECOMPRESS,
+ CPA_DC_CHAIN_DECRYPT_THEN_DECOMPRESS = 7,
/**< 2 operations for chaining:
* 1st operation is to perform decryption on compressed & encrypted text
* 2nd operation is to perform decompression on compressed text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for decryption setup data
* 2nd entry is for decompression setup data*/
- CPA_DC_CHAIN_HASH_VERIFY_DECRYPT_THEN_DECOMPRESS,
+ CPA_DC_CHAIN_HASH_VERIFY_DECRYPT_THEN_DECOMPRESS = 8,
/**< 2 operations for chaining:
* 1st operation is to perform hash verify on compressed & encrypted text
* and decryption on compressed & encrypted text
@@ -143,7 +143,7 @@
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for hash and decryption setup data
* 2nd entry is for decompression setup data*/
- CPA_DC_CHAIN_DECRYPT_HASH_VERIFY_THEN_DECOMPRESS,
+ CPA_DC_CHAIN_DECRYPT_HASH_VERIFY_THEN_DECOMPRESS = 9,
/**< 2 operations for chaining:
* 1st operation is to perform decryption on compressed & encrypted text
* and hash verify on compressed text
@@ -151,25 +151,25 @@
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for decryption and hash setup data
* 2nd entry is for decompression setup data*/
- CPA_DC_CHAIN_AEAD_THEN_DECOMPRESS,
+ CPA_DC_CHAIN_AEAD_THEN_DECOMPRESS = 10,
/**< 2 operations for chaining:
* 1st operation is to perform AEAD decryption on compressed & encrypted text
* 2nd operation is to perform decompression on compressed text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for AEAD decryption setup data
* 2nd entry is for decompression setup data*/
- CPA_DC_CHAIN_DECOMPRESS_THEN_HASH_VERIFY,
+ CPA_DC_CHAIN_DECOMPRESS_THEN_HASH_VERIFY = 11,
/**< 2 operations for chaining:
* 1st operation is to perform decompression on compressed text
* 2nd operation is to perform hash verify on plain text
**< 2 entries in CpaDcChainSessionSetupData array:
* 1st entry is for decompression setup data
* 2nd entry is for hash setup data*/
- CPA_DC_CHAIN_COMPRESS_THEN_AEAD_THEN_HASH,
+ CPA_DC_CHAIN_COMPRESS_THEN_AEAD_THEN_HASH = 12,
/**< 3 operations for chaining:
* 1st operation is to perform compression on plain text
- * 2nd operation is to perform AEAD encryption compressed text
- * 3rd operation is to perfom hash on compressed & encrypted text
+ * 2nd operation is to perform AEAD encryption on compressed text
+ * 3rd operation is to perform hash on compressed & encrypted text
**< 3 entries in CpaDcChainSessionSetupData array:
* 1st entry is for compression setup data
* 2nd entry is for AEAD encryption setup data
@@ -187,9 +187,9 @@
*****************************************************************************/
typedef enum _CpaDcChainSessionType
{
- CPA_DC_CHAIN_COMPRESS_DECOMPRESS,
+ CPA_DC_CHAIN_COMPRESS_DECOMPRESS = 0,
/**< Indicate the session is for compression or decompression */
- CPA_DC_CHAIN_SYMMETRIC_CRYPTO,
+ CPA_DC_CHAIN_SYMMETRIC_CRYPTO
/**< Indicate the session is for symmetric crypto */
} CpaDcChainSessionType;
@@ -210,7 +210,7 @@
CpaDcSessionSetupData *pDcSetupData;
/**< Pointer to compression session setup data */
CpaCySymSessionSetupData *pCySetupData;
- /**< Pointer to symmectric crypto session setup data */
+ /**< Pointer to symmetric crypto session setup data */
};
} CpaDcChainSessionSetupData;
@@ -230,7 +230,7 @@
CpaDcOpData *pDcOp;
/**< Pointer to compression operation data */
CpaCySymOpData *pCySymOp;
- /**< Pointer to symmectric crypto operation data */
+ /**< Pointer to symmetric crypto operation data */
};
} CpaDcChainOpData;
@@ -259,7 +259,7 @@
Cpa32U crc32;
/**< crc32 checksum produced by chaining operations */
Cpa32U adler32;
- /**< adler32 checksum produced by chaining operations */
+ /**< Adler32 checksum produced by chaining operations */
}CpaDcChainRqResults;
/**
@@ -366,8 +366,6 @@
* @retval CPA_STATUS_FAIL Function failed.
* @retval CPA_STATUS_INVALID_PARAM Invalid parameter passed in.
* @retval CPA_STATUS_RESOURCE Error related to system resources.
- * @retval CPA_STATUS_RESTARTING API implementation is restarting. Resubmit
- * the request.
* @retval CPA_STATUS_UNSUPPORTED Function is not supported.
*
* @pre
@@ -563,7 +561,7 @@
* @param[in] pChainOpData Pointer to an array of CpaDcChainOpData
* structures. There should be numOpDatas
* entries in the array.
- * @param[in,out] pResults Pointer to CpaDcChainRqResults structure.
+ * @param[in,out] pResults Pointer to CpaDcChainRqResults
* @param[in] callbackTag User supplied value to help correlate
* the callback with its associated request.
*
@@ -593,9 +591,9 @@
* -# The order of entries in pChainOpData[] must be consistent with the
* order of operations described for the chaining operation in
* CpaDcChainOperations.
- * As an example, for CPA_DC_CHAIN_COMPRESS_THEN_ENCRYPT, pChainOpData[0]
- * must contain the compression operation data and pChainOpData[1] must
- * contain the encryption operation data.
+ * As an example, for CPA_DC_CHAIN_HASH_THEN_COMPRESS, pChainOpData[0]
+ * must contain the hash operation data and pChainOpData[1] must
+ * contain the compress operation data.
*
* -# The numOpDatas for each chaining operation are specified in the
* comments for the operation in CpaDcChainOperations.
@@ -610,8 +608,6 @@
* CPA_DC_CHAIN_SYMMETRIC_CRYPTO and pChainOpData[]->pCySymOp should
* point to a CpaCySymOpData structure.
*
- * -# Stateful compression is not supported for chaining.
- *
* -# Partial packet processing is not supported.
*
* This function has identical buffer processing rules as
diff --git a/sys/dev/qat/qat_api/include/dc/cpa_dc_dp.h b/sys/dev/qat/qat_api/include/dc/cpa_dc_dp.h
--- a/sys/dev/qat/qat_api/include/dc/cpa_dc_dp.h
+++ b/sys/dev/qat/qat_api/include/dc/cpa_dc_dp.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/icp_buffer_desc.h b/sys/dev/qat/qat_api/include/icp_buffer_desc.h
--- a/sys/dev/qat/qat_api/include/icp_buffer_desc.h
+++ b/sys/dev/qat/qat_api/include/icp_buffer_desc.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
+
/**
*****************************************************************************
* @file icp_buffer_desc.h
@@ -20,7 +21,7 @@
typedef Cpa64U icp_qat_addr_width_t; // hi32 first, lo32 second
-// Alignement constraint of the buffer list.
+/* Alignment constraint of the buffer list. */
#define ICP_DESCRIPTOR_ALIGNMENT_BYTES 8
/**
@@ -31,7 +32,7 @@
*
* @description
* A QAT friendly buffer descriptor.
- * All buffer descriptor described in this structure are physcial
+ * All buffer descriptor described in this structure are physical
* and are 64 bit wide.
*
* Updates in the CpaFlatBuffer should be also reflected in this
@@ -55,7 +56,7 @@
*
* @description
* A QAT friendly buffer descriptor.
- * All buffer descriptor described in this structure are physcial
+ * All buffer descriptor described in this structure are physical
* and are 64 bit wide.
*
* Updates in the CpaBufferList should be also reflected in this structure
diff --git a/sys/dev/qat/qat_api/include/icp_sal_user.h b/sys/dev/qat/qat_api/include/icp_sal_user.h
--- a/sys/dev/qat/qat_api/include/icp_sal_user.h
+++ b/sys/dev/qat/qat_api/include/icp_sal_user.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
* @file icp_sal_user.h
@@ -75,7 +75,7 @@
*
* @param[in] limitDevAccess Specifies if the address space is limited
* to one device (true) or if it spans
- * accross multiple devices.
+ * across multiple devices.
*
* @retval CPA_STATUS_SUCCESS No error
* @retval CPA_STATUS_FAIL Operation failed. In this case user
@@ -478,7 +478,7 @@
* @assumptions
* None
* @sideEffects
- * In case a device has beed stoped or restarted the application
+ * In case a device has been stopped or restarted the application
* will get restarting/stop/shutdown events
* @reentrant
* No
diff --git a/sys/dev/qat/qat_api/include/icp_sal_versions.h b/sys/dev/qat/qat_api/include/icp_sal_versions.h
--- a/sys/dev/qat/qat_api/include/icp_sal_versions.h
+++ b/sys/dev/qat/qat_api/include/icp_sal_versions.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/**
***************************************************************************
* @file icp_sal_versions.h
@@ -26,7 +26,7 @@
/* Part name and number of the accelerator device */
#define SAL_INFO2_DRIVER_SW_VERSION_MAJ_NUMBER 3
-#define SAL_INFO2_DRIVER_SW_VERSION_MIN_NUMBER 14
+#define SAL_INFO2_DRIVER_SW_VERSION_MIN_NUMBER 15
#define SAL_INFO2_DRIVER_SW_VERSION_PATCH_NUMBER 0
/**
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_common.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_common.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_common.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_common.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_dh.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_dh.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_dh.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_dh.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_dsa.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_dsa.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_dsa.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_dsa.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_ec.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_ec.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_ec.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_ec.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
@@ -266,7 +266,7 @@
*
* @description
* This union allows for the characterisation of different curve types
- * encapsulted in one data type. The intention is that new curve types
+ * encapsulated in one data type. The intention is that new curve types
* will be added in the future.
*
* @note
@@ -451,7 +451,7 @@
*****************************************************************************
* @ingroup cpaCyEc
* EC Point Multiplication Operation Data for Edwards or
- * Montgomery curves as specificied in RFC#7748.
+ * Montgomery curves as specified in RFC#7748.
*
* @description
* This structure contains the operation data for the
@@ -486,11 +486,11 @@
/**< field type for the operation */
CpaBoolean generator;
/**< True if the operation is a generator multiplication (kG)
- * False if it is a variable point multiplcation (kP). */
+ * False if it is a variable point multiplication (kP). */
CpaFlatBuffer k;
/**< k scalar multiplier for the operation */
CpaFlatBuffer x;
- /**< x value. Used in scalar varable point multiplication operations.
+ /**< x value. Used in scalar variable point multiplication operations.
* Not required if the generator is True. Must be NULL if not required.
* The size of the buffer MUST be 32B for 25519 curves and 64B for 448
* curves */
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdh.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdh.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdh.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdh.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdsa.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdsa.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdsa.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_ecdsa.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_im.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_im.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_im.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_im.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_key.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_key.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_key.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_key.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_kpt.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_kpt.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_kpt.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_kpt.h
@@ -2,7 +2,7 @@
*
* BSD LICENSE
*
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -96,14 +96,14 @@
typedef enum CpaCyKptKeyManagementStatus_t
{
CPA_CY_KPT_SUCCESS = 0,
- /**< Generic success status for all KPT wrapping key handling functions*/
+ /**< Generic success status for all KPT wrapping key handling functions */
CPA_CY_KPT_LOADKEY_FAIL_QUOTA_EXCEEDED_PER_VFID,
- /**< SWK count exceeds the configured maxmium value per VFID*/
+ /**< SWK count exceeds the configured maximum value per VFID */
CPA_CY_KPT_LOADKEY_FAIL_QUOTA_EXCEEDED_PER_PASID,
- /**< SWK count exceeds the configured maxmium value per PASID*/
+ /**< SWK count exceeds the configured maximum value per PASID */
CPA_CY_KPT_LOADKEY_FAIL_QUOTA_EXCEEDED,
- /**< SWK count exceeds the configured maxmium value when not scoped to
- * VFID or PASID*/
+ /**< SWK count exceeds the configured maximum value when not scoped to
+ * VFID or PASID */
CPA_CY_KPT_SWK_FAIL_NOT_FOUND,
/**< Unable to find SWK entry by handle */
CPA_CY_KPT_FAILED,
@@ -277,7 +277,7 @@
* describing the RSA private key. The quintuple of p, q, dP, dQ, and qInv
* (explained below and in the spec) are required for the second
* representation. For KPT the parameters are Encrypted
- * with the assoicated SWK as follows:
+ * with the associated SWK as follows:
* Encrypt - AES-256-GCM (Key, AAD, Input)
* "||" - denotes concatenation
* Key = SWK
@@ -584,11 +584,11 @@
* enumerate type CpaCyKptKeyManagementStatus
* CPA_CY_KPT_SUCCESS Key Loaded successfully
* CPA_CY_KPT_LOADKEY_FAIL_QUOTA_EXCEEDED_PER_VFID
- * SWK count exceeds the configured maxmium value per VFID
+ * SWK count exceeds the configured maximum value per VFID
* CPA_CY_KPT_LOADKEY_FAIL_QUOTA_EXCEEDED_PER_PASID
- * SWK count exceeds the configured maxmium value per PASID
+ * SWK count exceeds the configured maximum value per PASID
* CPA_CY_KPT_LOADKEY_FAIL_QUOTA_EXCEEDED
- * SWK count exceeds the configured maxmium value when not scoped to
+ * SWK count exceeds the configured maximum value when not scoped to
* VFID or PASID
* CPA_CY_KPT_FAILED Operation failed due to unspecified reason
*
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_ln.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_ln.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_ln.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_ln.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_prime.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_prime.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_prime.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_prime.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_rsa.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_rsa.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_rsa.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_rsa.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_sym.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_sym.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_sym.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_sym.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
@@ -71,7 +71,7 @@
* is allocated by the client. The size of the memory that the client needs
* to allocate is determined by a call to the @ref
* cpaCySymSessionCtxGetSize or @ref cpaCySymSessionCtxGetDynamicSize
- * functions. The session context memory is initialized with a call to
+ * functions. The session context memory is initialized with a call to
* the @ref cpaCySymInitSession function.
* This memory MUST not be freed until a call to @ref
* cpaCySymRemoveSession has completed successfully.
@@ -253,7 +253,7 @@
* Symmetric Cipher Setup Data.
* @description
* This structure contains data relating to Cipher (Encryption and
- * Decryption) to set up a session.
+ * Decryption) to setup a session.
*
*****************************************************************************/
typedef struct _CpaCySymCipherSetupData {
@@ -272,7 +272,8 @@
* - Two keys must be provided and cipherKeyLenInBytes refers to total
* length of the two keys.
* - Each key can be either 128 bits (16 bytes) or 256 bits (32 bytes).
- * - Both keys must have the same size. */
+ * - Both keys must have the same size.
+ */
Cpa8U *pCipherKey;
/**< Cipher key
* For the CPA_CY_SYM_CIPHER_AES_F8 mode of operation, pCipherKey will
@@ -281,7 +282,9 @@
* bytes to match the length of the encryption key used.
* For AES-XTS mode of operation, two keys must be provided and pCipherKey
* must point to the two keys concatenated together (Key1 || Key2).
- * cipherKeyLenInBytes will contain the total size of both keys. */
+ * cipherKeyLenInBytes will contain the total size of both keys.
+ * These fields are set to NULL if key derivation will be used.
+ */
CpaCySymCipherDirection cipherDirection;
/**< This parameter determines if the cipher operation is an encrypt or
* a decrypt operation.
@@ -651,11 +654,11 @@
* setup a session.
*
****************************************************************************/
-typedef struct _CpaCySymSessionSetupData {
+typedef struct _CpaCySymSessionSetupData {
CpaCyPriority sessionPriority;
/**< Priority of this session */
CpaCySymOp symOperation;
- /**< Operation to perfom */
+ /**< Operation to perform */
CpaCySymCipherSetupData cipherSetupData;
/**< Cipher Setup Data for the session. This member is ignored for the
* CPA_CY_SYM_OP_HASH operation. */
@@ -665,7 +668,7 @@
CpaCySymAlgChainOrder algChainOrder;
/**< If this operation data structure relates to an algorithm chaining
* session then this parameter determines the order in which the chained
- * operations are performed. If this structure does not relate to an
+ * operations are performed. If this structure does not relate to an
* algorithm chaining session then this parameter will be ignored.
*
* @note In the case of authenticated ciphers (GCM and CCM), which are
@@ -674,7 +677,7 @@
* cases. */
CpaBoolean digestIsAppended;
/**< Flag indicating whether the digest is appended immediately following
- * the region over which the digest is computed. This is true for both
+ * the region over which the digest is computed. This is true for both
* IPsec packets and SSL/TLS records.
*
* If this flag is set, then the value of the pDigestResult field of
@@ -689,7 +692,7 @@
*/
CpaBoolean verifyDigest;
/**< This flag is relevant only for operations which generate a message
- * digest. If set to true, the computed digest will not be written back
+ * digest. If set to true, the computed digest will not be written back
* to the buffer location specified by other parameters, but instead will
* be verified (i.e. compared to the value passed in at that location).
* The number of bytes to be written or compared is indicated by the
@@ -697,7 +700,7 @@
* @note This option is only valid for full packets and for final
* partial packets when using partials without algorithm chaining.
* @note The value of this field is ignored for the authenticated ciphers
- * (AES_CCM and AES_GCM). Digest verification is always done for these
+ * (AES_CCM and AES_GCM). Digest verification is always done for these
* (when the direction is decrypt) and unless the DP API is used,
* the message buffer will be zeroed if verification fails. When using the
* DP API, it is the API clients responsibility to clear the message
@@ -938,6 +941,7 @@
* operation, this field is not used and should be set to 0. Instead
* the AAD data should be placed in the source buffer.
*/
+
} CpaCySymOpData;
/**
@@ -961,7 +965,7 @@
* @description
* This macro sets the additional authentication data in the
* appropriate location of the@ref CpaCySymOpData struct for the
- * authenticated encryptionalgorithm @ref CPA_CY_SYM_HASH_AES_CCM.
+ * authenticated encryption algorithm @ref CPA_CY_SYM_HASH_AES_CCM.
****************************************************************************/
#define CPA_CY_SYM_CCM_SET_AAD(pOpData, pAad, aadLen) do { \
memcpy(&pOpData->pAdditionalAuthData[18], pAad, aadLen); \
@@ -1122,10 +1126,10 @@
* implementations)
* (2) between different releases of the same API implementation.
*
- * The size returned by this function is the smallest size needed to
+ * The size returned by this function is the smallest size needed to
* support all possible combinations of setup data parameters. Some
- * setup data parameter combinations may fit within a smaller session
- * context size. The alternate cpaCySymSessionCtxGetDynamicSize()
+ * setup data parameter combinations may fit within a smaller session
+ * context size. The alternate cpaCySymSessionCtxGetDynamicSize()
* function will return the smallest size needed to fit the
* provided setup data parameters.
*
@@ -1183,17 +1187,17 @@
* Gets the minimum size required to store a session context.
*
* @description
- * This function is used by the client to determine the smallest size of
- * the memory it must allocate in order to store the session context.
- * This MUST be called before the client allocates the memory for the
- * session context and before the client calls the @ref cpaCySymInitSession
+ * This function is used by the client to determine the smallest size of
+ * the memory it must allocate in order to store the session context.
+ * This MUST be called before the client allocates the memory for the
+ * session context and before the client calls the @ref cpaCySymInitSession
* function.
*
* This function is an alternate to cpaCySymSessionGetSize().
- * cpaCySymSessionCtxGetSize() will return a fixed size which is the
- * minimum memory size needed to support all possible setup data parameter
- * combinations. cpaCySymSessionCtxGetDynamicSize() will return the
- * minimum memory size needed to support the specific session setup
+ * cpaCySymSessionCtxGetSize() will return a fixed size which is the
+ * minimum memory size needed to support all possible setup data parameter
+ * combinations. cpaCySymSessionCtxGetDynamicSize() will return the
+ * minimum memory size needed to support the specific session setup
* data parameters provided. This size may be different for different setup
* data parameters.
*
@@ -1564,7 +1568,7 @@
* a multiple of the relevant block size.
* i.e. padding WILL NOT be applied to the data.
* For optimum performance, the buffer should
- * only contain the data region that the
+ * only contain the data region that the
* cryptographic operation(s) must be performed on.
* Any additional data in the source buffer may be
* copied to the destination buffer and this copy
diff --git a/sys/dev/qat/qat_api/include/lac/cpa_cy_sym_dp.h b/sys/dev/qat/qat_api/include/lac/cpa_cy_sym_dp.h
--- a/sys/dev/qat/qat_api/include/lac/cpa_cy_sym_dp.h
+++ b/sys/dev/qat/qat_api/include/lac/cpa_cy_sym_dp.h
@@ -1,14 +1,14 @@
/***************************************************************************
*
* BSD LICENSE
- *
- * Copyright(c) 2007-2023 Intel Corporation. All rights reserved.
+ *
+ * Copyright(c) 2007-2025 Intel Corporation. All rights reserved.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -30,7 +30,7 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
*
***************************************************************************/
@@ -376,7 +376,7 @@
* @description
* This is the callback function prototype. The callback function is
* registered by the application using the @ref cpaCySymDpRegCbFunc
- * function call, and called back on completion of asycnhronous
+ * function call, and called back on completion of asynchronous
* requests made via calls to @ref cpaCySymDpEnqueueOp or @ref
* cpaCySymDpEnqueueOpBatch.
*
@@ -428,7 +428,7 @@
* @description
* This function allows a completion callback function to be registered.
* The registered callback function is invoked on completion of
- * asycnhronous requests made via calls to @ref cpaCySymDpEnqueueOp
+ * asynchronous requests made via calls to @ref cpaCySymDpEnqueueOp
* or @ref cpaCySymDpEnqueueOpBatch.
*
* If a callback function was previously registered, it is overwritten.
diff --git a/sys/dev/qat/qat_api/qat_direct/include/icp_accel_devices.h b/sys/dev/qat/qat_api/qat_direct/include/icp_accel_devices.h
--- a/sys/dev/qat/qat_api/qat_direct/include/icp_accel_devices.h
+++ b/sys/dev/qat/qat_api/qat_direct/include/icp_accel_devices.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/*****************************************************************************
* @file icp_accel_devices.h
*
@@ -126,7 +126,7 @@
QatUtilsAtomic usageCounter; /* Usage counter. Prevents
shutting down the dev if not 0*/
Cpa32U deviceMemAvail; /* Device memory for intermediate buffers */
- /* Component specific fields - cast to relevent layer */
+ /* Component specific fields - cast to relevant layer */
void *pRingInflight; /* For offload optimization */
void *pSalHandle; /* For SAL*/
void *pQatStats; /* For QATAL/SAL stats */
diff --git a/sys/dev/qat/qat_api/qat_direct/include/icp_adf_init.h b/sys/dev/qat/qat_api/qat_direct/include/icp_adf_init.h
--- a/sys/dev/qat/qat_api/qat_direct/include/icp_adf_init.h
+++ b/sys/dev/qat/qat_api/qat_direct/include/icp_adf_init.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
/*****************************************************************************
* @file icp_adf_init.h
*
@@ -40,7 +40,7 @@
} icp_adf_ringInfoOperation_t;
/*
- * Ring generic serivce info private data
+ * Ring generic service info private data
*/
typedef enum icp_adf_ringInfoService_e {
ICP_ADF_RING_SERVICE_0 = 0,
diff --git a/sys/dev/qat/qat_api/qat_kernel/src/lac_adf_interface_freebsd.c b/sys/dev/qat/qat_api/qat_kernel/src/lac_adf_interface_freebsd.c
--- a/sys/dev/qat/qat_api/qat_kernel/src/lac_adf_interface_freebsd.c
+++ b/sys/dev/qat/qat_api/qat_kernel/src/lac_adf_interface_freebsd.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_cfg.h"
#include "cpa.h"
#include "icp_accel_devices.h"
@@ -288,8 +288,8 @@
/*
* icp_amgr_getAllAccelDevByEachCapabilities
- * Returns table of accel devices that are started and implement
- * each of the capabilities specified in capabilitiesMask.
+ * Returns table of accel devices that are started and that implement
+ * at least one of the capabilities specified in capabilitiesMask.
*/
CpaStatus
icp_amgr_getAllAccelDevByEachCapability(Cpa32U capabilitiesMask,
diff --git a/sys/dev/qat/qat_api/qat_utils/include/qat_utils.h b/sys/dev/qat/qat_api/qat_utils/include/qat_utils.h
--- a/sys/dev/qat/qat_api/qat_utils/include/qat_utils.h
+++ b/sys/dev/qat/qat_api/qat_utils/include/qat_utils.h
@@ -1,9 +1,8 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef QAT_UTILS_H
#define QAT_UTILS_H
-
#include <sys/param.h>
#include <sys/ctype.h>
#include <sys/endian.h>
@@ -830,7 +829,7 @@
*
* @brief Single block AES encrypt
*
- * @param key - pointer to symetric key.
+ * @param key - pointer to symmetric key.
* keyLenInBytes - key length
* in - pointer to data to encrypt
* out - pointer to output buffer for encrypted text
@@ -853,7 +852,7 @@
*
* @brief Converts AES forward key to reverse key
*
- * @param key - pointer to symetric key.
+ * @param key - pointer to symmetric key.
* keyLenInBytes - key length
* out - pointer to output buffer for reversed key
* The in and out buffers need to be at least AES block size long
diff --git a/sys/dev/qat/qat_api/qat_utils/src/QatUtilsServices.c b/sys/dev/qat/qat_api/qat_utils/src/QatUtilsServices.c
--- a/sys/dev/qat/qat_api/qat_utils/src/QatUtilsServices.c
+++ b/sys/dev/qat/qat_api/qat_utils/src/QatUtilsServices.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_utils.h"
#include <sys/param.h>
@@ -20,7 +20,7 @@
*
* Data struct to store the information on the
* memory allocated. This structure is stored at the beginning of
- * the allocated chunck of memory
+ * the allocated chunk of memory
* size is the no of byte passed to the memory allocation functions
* mSize is the real size of the memory required to the OS
*
diff --git a/sys/dev/qat/qat_common/adf_aer.c b/sys/dev/qat/qat_common/adf_aer.c
--- a/sys/dev/qat/qat_common/adf_aer.c
+++ b/sys/dev/qat/qat_common/adf_aer.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -276,6 +276,15 @@
struct adf_fatal_error_data *wq_data =
container_of(work, struct adf_fatal_error_data, work);
struct adf_accel_dev *accel_dev = wq_data->accel_dev;
+ struct adf_hw_device_data *hw_device = accel_dev->hw_device;
+
+ if (adf_dev_in_use(accel_dev)) {
+ if (hw_device->pre_reset) {
+ device_printf(GET_DEV(accel_dev),
+ "Performing pre reset save\n");
+ hw_device->pre_reset(accel_dev);
+ }
+ }
adf_error_notifier((uintptr_t)accel_dev);
if (!accel_dev->is_vf) {
diff --git a/sys/dev/qat/qat_common/adf_cfg.c b/sys/dev/qat/qat_common/adf_cfg.c
--- a/sys/dev/qat/qat_common/adf_cfg.c
+++ b/sys/dev/qat/qat_common/adf_cfg.c
@@ -1,15 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_accel_devices.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
-#include "adf_cfg_dev_dbg.h"
#include "adf_cfg_device.h"
#include "adf_cfg_sysctl.h"
-#include "adf_heartbeat_dbg.h"
-#include "adf_ver_dbg.h"
-#include "adf_fw_counters.h"
-#include "adf_cnvnr_freq_counters.h"
/**
* adf_cfg_dev_add() - Create an acceleration device configuration table.
@@ -73,31 +68,13 @@
ADF_CFG_MAX_VAL);
}
- if (adf_cfg_sysctl_add(accel_dev))
- goto err;
-
- if (adf_cfg_dev_dbg_add(accel_dev))
- goto err;
-
- if (!accel_dev->is_vf) {
- if (adf_heartbeat_dbg_add(accel_dev))
- goto err;
-
- if (adf_ver_dbg_add(accel_dev))
- goto err;
-
- if (adf_fw_counters_add(accel_dev))
- goto err;
-
- if (adf_cnvnr_freq_counters_add(accel_dev))
- goto err;
+ if (adf_cfg_sysctl_add(accel_dev)) {
+ free(dev_cfg_data, M_QAT);
+ accel_dev->cfg = NULL;
+ return EFAULT;
}
- return 0;
-err:
- free(dev_cfg_data, M_QAT);
- accel_dev->cfg = NULL;
- return EFAULT;
+ return 0;
}
static void adf_cfg_section_del_all(struct list_head *head);
@@ -142,13 +119,6 @@
sx_xunlock(&dev_cfg_data->lock);
adf_cfg_sysctl_remove(accel_dev);
- adf_cfg_dev_dbg_remove(accel_dev);
- if (!accel_dev->is_vf) {
- adf_ver_dbg_del(accel_dev);
- adf_heartbeat_dbg_del(accel_dev);
- adf_fw_counters_remove(accel_dev);
- adf_cnvnr_freq_counters_remove(accel_dev);
- }
free(dev_cfg_data, M_QAT);
accel_dev->cfg = NULL;
diff --git a/sys/dev/qat/qat_common/adf_cfg_device.c b/sys/dev/qat/qat_common/adf_cfg_device.c
--- a/sys/dev/qat/qat_common/adf_cfg_device.c
+++ b/sys/dev/qat/qat_common/adf_cfg_device.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_cfg_instance.h"
#include "adf_cfg_section.h"
#include "adf_cfg_device.h"
@@ -677,6 +677,18 @@
device->instances = NULL;
}
+void
+adf_cfg_device_clear_all(struct adf_accel_dev *accel_dev)
+{
+ sx_xlock(&accel_dev->cfg->lock);
+ if (accel_dev->cfg->dev) {
+ adf_cfg_device_clear(accel_dev->cfg->dev, accel_dev);
+ free (accel_dev->cfg->dev, M_QAT);
+ accel_dev->cfg->dev = NULL;
+ }
+ sx_xunlock(&accel_dev->cfg->lock);
+}
+
/*
* Static configuration for userspace
*/
diff --git a/sys/dev/qat/qat_common/adf_cfg_sysctl.c b/sys/dev/qat/qat_common/adf_cfg_sysctl.c
--- a/sys/dev/qat/qat_common/adf_cfg_sysctl.c
+++ b/sys/dev/qat/qat_common/adf_cfg_sysctl.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <sys/types.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
@@ -10,6 +10,7 @@
#include "adf_common_drv.h"
#include <sys/mutex.h>
#include <sys/sbuf.h>
+#include <sys/priv.h>
#define ADF_CFG_SYSCTL_BUF_SZ ADF_CFG_MAX_VAL
#define ADF_CFG_UP_STR "up"
@@ -105,6 +106,9 @@
int ret = 0;
int i = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
accel_dev = arg1;
if (!accel_dev)
return ENXIO;
@@ -156,6 +160,9 @@
int ret = 0;
int i = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
accel_dev = arg1;
if (!accel_dev)
return ENXIO;
@@ -204,6 +211,9 @@
unsigned int len;
int ret = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
accel_dev = arg1;
if (!accel_dev)
return ENXIO;
@@ -245,6 +255,9 @@
uint32_t num_user_processes = 0;
int ret = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
accel_dev = arg1;
if (!accel_dev)
return ENXIO;
diff --git a/sys/dev/qat/qat_common/adf_clock.c b/sys/dev/qat/qat_common/adf_clock.c
--- a/sys/dev/qat/qat_common/adf_clock.c
+++ b/sys/dev/qat/qat_common/adf_clock.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_accel_devices.h"
#include "adf_common_drv.h"
#include <linux/delay.h>
+#include <sys/priv.h>
#define MEASURE_CLOCK_RETRIES 10
#define MEASURE_CLOCK_DELTA_THRESHOLD 100
@@ -21,11 +22,30 @@
} \
} while (0)
+static int adf_clock_read_frequency(SYSCTL_HANDLER_ARGS)
+{
+ struct adf_accel_dev *accel_dev = arg1;
+ struct adf_hw_device_data *hw_data;
+ int error = EFAULT;
+
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
+ if (accel_dev == NULL)
+ return EINVAL;
+
+ hw_data = accel_dev->hw_device;
+
+ error = sysctl_handle_int(oidp, &hw_data->clock_frequency, 0, req);
+ if (error || !req->newptr)
+ return error;
+
+ return (0);
+}
+
int
adf_clock_debugfs_add(struct adf_accel_dev *accel_dev)
{
- struct adf_hw_device_data *hw_data = accel_dev->hw_device;
-
struct sysctl_ctx_list *qat_sysctl_ctx;
struct sysctl_oid *qat_sysctl_tree;
struct sysctl_oid *rc = 0;
@@ -35,13 +55,15 @@
qat_sysctl_tree =
device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev);
- rc = SYSCTL_ADD_UINT(qat_sysctl_ctx,
+ rc = SYSCTL_ADD_PROC(qat_sysctl_ctx,
SYSCTL_CHILDREN(qat_sysctl_tree),
OID_AUTO,
CLK_DBGFS_FILE,
- CTLFLAG_RD,
- &hw_data->clock_frequency,
+ CTLTYPE_INT | CTLFLAG_RD,
+ accel_dev,
0,
+ adf_clock_read_frequency,
+ "IU",
"clock frequency");
HB_SYSCTL_ERR(rc);
return 0;
diff --git a/sys/dev/qat/qat_common/adf_freebsd_cfg_dev_dbg.c b/sys/dev/qat/qat_common/adf_freebsd_cfg_dev_dbg.c
--- a/sys/dev/qat/qat_common/adf_freebsd_cfg_dev_dbg.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_cfg_dev_dbg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_common_drv.h"
#include "adf_cfg_device.h"
@@ -12,6 +12,7 @@
#include <sys/sx.h>
#include <sys/systm.h>
#include <sys/malloc.h>
+#include <sys/priv.h>
static int qat_dev_cfg_show(SYSCTL_HANDLER_ARGS)
{
@@ -21,6 +22,9 @@
struct sbuf sb;
int error;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
sbuf_new_for_sysctl(&sb, NULL, 128, req);
dev_cfg = arg1;
sx_slock(&dev_cfg->lock);
diff --git a/sys/dev/qat/qat_common/adf_freebsd_cnvnr_ctrs_dbg.c b/sys/dev/qat/qat_common/adf_freebsd_cnvnr_ctrs_dbg.c
--- a/sys/dev/qat/qat_common/adf_freebsd_cnvnr_ctrs_dbg.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_cnvnr_ctrs_dbg.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <sys/types.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
+#include <sys/priv.h>
#include "adf_cnvnr_freq_counters.h"
#include "adf_common_drv.h"
#include "adf_cfg.h"
@@ -45,6 +46,9 @@
char report[MAX_REPORT_SIZE];
char *report_ptr = report;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
/* Defensive check */
if (!accel_dev || accel_dev->accel_id > ADF_MAX_DEVICES)
return EINVAL;
@@ -89,6 +93,7 @@
/* Extracting number of Acceleration Engines */
num_aes = hw_device->get_num_aes(hw_device);
+ explicit_bzero(&request, sizeof(struct icp_qat_fw_init_admin_req));
for (ae = 0; ae < num_aes; ae++) {
if (accel_dev->au_info && !test_bit(ae, &dc_ae_msk))
continue;
@@ -123,10 +128,12 @@
cnvnr_err_str[error_type],
latest_error);
if (bytes_written <= 0) {
- printf("ERROR: No space left in CnV ctrs line buffer\n"
- "\tAcceleration ID: %d, Engine: %d\n",
- accel_dev->accel_id,
- ae);
+ device_printf(
+ GET_DEV(accel_dev),
+ "ERROR: No space left in CnV ctrs line buffer\n"
+ "\tAcceleration ID: %d, Engine: %d\n",
+ accel_dev->accel_id,
+ ae);
break;
}
report_ptr += bytes_written;
@@ -141,7 +148,6 @@
{
struct sysctl_ctx_list *qat_sysctl_ctx;
struct sysctl_oid *qat_cnvnr_ctrs_sysctl_tree;
- struct sysctl_oid *oid_rc;
/* Defensive checks */
if (!accel_dev)
@@ -154,19 +160,22 @@
device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev);
/* Create "cnv_error" string type leaf - with callback */
- oid_rc = SYSCTL_ADD_PROC(qat_sysctl_ctx,
- SYSCTL_CHILDREN(qat_cnvnr_ctrs_sysctl_tree),
- OID_AUTO,
- "cnv_error",
- CTLTYPE_STRING | CTLFLAG_RD,
- accel_dev,
- 0,
- qat_cnvnr_ctrs_dbg_read,
- "IU",
- "QAT CnVnR status");
-
- if (!oid_rc) {
- printf("ERROR: Memory allocation failed\n");
+ accel_dev->cnv_error_oid =
+ SYSCTL_ADD_PROC(qat_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_cnvnr_ctrs_sysctl_tree),
+ OID_AUTO,
+ "cnv_error",
+ CTLTYPE_STRING | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ qat_cnvnr_ctrs_dbg_read,
+ "IU",
+ "QAT CnVnR status");
+
+ if (!accel_dev->cnv_error_oid) {
+ device_printf(
+ GET_DEV(accel_dev),
+ "Failed to create qat cnvnr freq counters sysctl entry.\n");
return ENOMEM;
}
return 0;
@@ -175,4 +184,17 @@
void
adf_cnvnr_freq_counters_remove(struct adf_accel_dev *accel_dev)
{
+ struct sysctl_ctx_list *qat_sysctl_ctx;
+
+ if (!accel_dev)
+ return;
+
+ qat_sysctl_ctx =
+ device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
+
+ if (accel_dev->cnv_error_oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx, accel_dev->cnv_error_oid);
+ sysctl_remove_oid(accel_dev->cnv_error_oid, 1, 1);
+ accel_dev->cnv_error_oid = NULL;
+ }
}
diff --git a/sys/dev/qat/qat_common/adf_freebsd_dbgfs.c b/sys/dev/qat/qat_common/adf_freebsd_dbgfs.c
new file mode 100644
--- /dev/null
+++ b/sys/dev/qat/qat_common/adf_freebsd_dbgfs.c
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
+
+#include "adf_accel_devices.h"
+#include "adf_cfg_dev_dbg.h"
+#include "adf_cnvnr_freq_counters.h"
+#include "adf_common_drv.h"
+#include "adf_dbgfs.h"
+#include "adf_fw_counters.h"
+#include "adf_freebsd_pfvf_ctrs_dbg.h"
+#include "adf_heartbeat_dbg.h"
+#include "adf_ver_dbg.h"
+
+/**
+ * adf_dbgfs_init() - add persistent debugfs entries
+ * @accel_dev: Pointer to acceleration device.
+ *
+ * This function creates debugfs entries that are persistent through a device
+ * state change (from up to down or vice versa).
+ */
+void
+adf_dbgfs_init(struct adf_accel_dev *accel_dev)
+{
+ adf_cfg_dev_dbg_add(accel_dev);
+}
+EXPORT_SYMBOL_GPL(adf_dbgfs_init);
+
+/**
+ * adf_dbgfs_exit() - remove persistent debugfs entries
+ * @accel_dev: Pointer to acceleration device.
+ */
+void
+adf_dbgfs_exit(struct adf_accel_dev *accel_dev)
+{
+ adf_cfg_dev_dbg_remove(accel_dev);
+}
+EXPORT_SYMBOL_GPL(adf_dbgfs_exit);
+
+/**
+ * adf_dbgfs_add() - add non-persistent debugfs entries
+ * @accel_dev: Pointer to acceleration device.
+ *
+ * This function creates debugfs entries that are not persistent through
+ * a device state change (from up to down or vice versa).
+ */
+void
+adf_dbgfs_add(struct adf_accel_dev *accel_dev)
+{
+ if (!accel_dev->is_vf) {
+ adf_heartbeat_dbg_add(accel_dev);
+ adf_ver_dbg_add(accel_dev);
+ adf_fw_counters_add(accel_dev);
+ adf_cnvnr_freq_counters_add(accel_dev);
+ }
+}
+
+/**
+ * adf_dbgfs_rm() - remove non-persistent debugfs entries
+ * @accel_dev: Pointer to acceleration device.
+ */
+void
+adf_dbgfs_rm(struct adf_accel_dev *accel_dev)
+{
+ if (!accel_dev->is_vf) {
+ adf_cnvnr_freq_counters_remove(accel_dev);
+ adf_fw_counters_remove(accel_dev);
+ adf_ver_dbg_del(accel_dev);
+ adf_heartbeat_dbg_del(accel_dev);
+ }
+}
diff --git a/sys/dev/qat/qat_common/adf_freebsd_dev_processes.c b/sys/dev/qat/qat_common/adf_freebsd_dev_processes.c
--- a/sys/dev/qat/qat_common/adf_freebsd_dev_processes.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_dev_processes.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
-
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -85,7 +84,7 @@
.d_name = ADF_DEV_STATE_NAME,
};
-static const struct filterops adf_state_read_filterops = {
+static struct filterops adf_state_read_filterops = {
.f_isfd = 1,
.f_attach = NULL,
.f_detach = adf_state_kqread_detach,
@@ -410,17 +409,6 @@
state->state.dev_state = event;
state->state.dev_id = dev;
STAILQ_INSERT_TAIL(head, state, entries_state);
- if (event == ADF_EVENT_STOP) {
- state = NULL;
- state = malloc(sizeof(struct entry_state),
- M_QAT,
- M_NOWAIT | M_ZERO);
- if (!state)
- continue;
- state->state.dev_state = ADF_EVENT_SHUTDOWN;
- state->state.dev_id = dev;
- STAILQ_INSERT_TAIL(head, state, entries_state);
- }
}
mtx_unlock(&mtx);
callout_schedule(&callout, ADF_STATE_CALLOUT_TIME);
@@ -451,7 +439,7 @@
case ADF_EVENT_START:
return ret;
case ADF_EVENT_STOP:
- break;
+ return ret;
case ADF_EVENT_ERROR:
break;
#if defined(QAT_UIO) && defined(QAT_DBG)
@@ -548,6 +536,7 @@
struct entry_proc_events *proc_events = NULL;
adf_service_unregister(&adf_state_hndl);
+ destroy_dev(adf_state_dev);
mtx_lock(&callout_mtx);
callout_stop(&callout);
mtx_unlock(&callout_mtx);
@@ -560,7 +549,6 @@
}
mtx_unlock(&mtx);
mtx_destroy(&mtx);
- destroy_dev(adf_state_dev);
}
static int
diff --git a/sys/dev/qat/qat_common/adf_freebsd_heartbeat_dbg.c b/sys/dev/qat/qat_common/adf_freebsd_heartbeat_dbg.c
--- a/sys/dev/qat/qat_common/adf_freebsd_heartbeat_dbg.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_heartbeat_dbg.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <sys/types.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
+#include <sys/priv.h>
#include "adf_heartbeat_dbg.h"
#include "adf_common_drv.h"
#include "adf_cfg.h"
@@ -17,6 +18,49 @@
} \
} while (0)
+
+static int qat_dev_hb_read_sent(SYSCTL_HANDLER_ARGS)
+{
+ struct adf_accel_dev *accel_dev = arg1;
+ struct adf_heartbeat *hb;
+ int error = EFAULT;
+
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
+ if (accel_dev == NULL)
+ return EINVAL;
+
+ hb = accel_dev->heartbeat;
+
+ error = sysctl_handle_int(oidp, &hb->hb_sent_counter, 0, req);
+ if (error || !req->newptr)
+ return error;
+
+ return (0);
+}
+
+static int qat_dev_hb_read_failed(SYSCTL_HANDLER_ARGS)
+{
+ struct adf_accel_dev *accel_dev = arg1;
+ struct adf_heartbeat *hb;
+ int error = EFAULT;
+
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
+ if (accel_dev == NULL)
+ return EINVAL;
+
+ hb = accel_dev->heartbeat;
+
+ error = sysctl_handle_int(oidp, &hb->hb_failed_counter, 0, req);
+ if (error || !req->newptr)
+ return error;
+
+ return (0);
+}
+
/* Handler for HB status check */
static int qat_dev_hb_read(SYSCTL_HANDLER_ARGS)
{
@@ -24,6 +68,10 @@
struct adf_accel_dev *accel_dev = arg1;
struct adf_heartbeat *hb;
int ret = 0;
+
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (accel_dev == NULL) {
return EINVAL;
}
@@ -48,7 +96,6 @@
struct sysctl_ctx_list *qat_hb_sysctl_ctx;
struct sysctl_oid *qat_hb_sysctl_tree;
struct adf_heartbeat *hb;
- struct sysctl_oid *rc = 0;
if (accel_dev == NULL) {
return EINVAL;
@@ -63,43 +110,80 @@
qat_hb_sysctl_tree =
device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev);
- rc = SYSCTL_ADD_UINT(qat_hb_sysctl_ctx,
- SYSCTL_CHILDREN(qat_hb_sysctl_tree),
- OID_AUTO,
- "heartbeat_sent",
- CTLFLAG_RD,
- &hb->hb_sent_counter,
- 0,
- "HB sent count");
- HB_SYSCTL_ERR(rc);
-
- rc = SYSCTL_ADD_UINT(qat_hb_sysctl_ctx,
- SYSCTL_CHILDREN(qat_hb_sysctl_tree),
- OID_AUTO,
- "heartbeat_failed",
- CTLFLAG_RD,
- &hb->hb_failed_counter,
- 0,
- "HB failed count");
- HB_SYSCTL_ERR(rc);
-
- rc = SYSCTL_ADD_PROC(qat_hb_sysctl_ctx,
- SYSCTL_CHILDREN(qat_hb_sysctl_tree),
- OID_AUTO,
- "heartbeat",
- CTLTYPE_INT | CTLFLAG_RD,
- accel_dev,
- 0,
- qat_dev_hb_read,
- "IU",
- "QAT device status");
- HB_SYSCTL_ERR(rc);
+ hb->heartbeat_sent.oid =
+ SYSCTL_ADD_PROC(qat_hb_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_hb_sysctl_tree),
+ OID_AUTO,
+ "heartbeat_sent",
+ CTLTYPE_INT | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ qat_dev_hb_read_sent,
+ "IU",
+ "HB failed count");
+ HB_SYSCTL_ERR(hb->heartbeat_sent.oid);
+
+ hb->heartbeat_failed.oid =
+ SYSCTL_ADD_PROC(qat_hb_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_hb_sysctl_tree),
+ OID_AUTO,
+ "heartbeat_failed",
+ CTLTYPE_INT | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ qat_dev_hb_read_failed,
+ "IU",
+ "HB failed count");
+ HB_SYSCTL_ERR(hb->heartbeat_failed.oid);
+
+ hb->heartbeat.oid = SYSCTL_ADD_PROC(qat_hb_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_hb_sysctl_tree),
+ OID_AUTO,
+ "heartbeat",
+ CTLTYPE_INT | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ qat_dev_hb_read,
+ "IU",
+ "QAT device status");
+ HB_SYSCTL_ERR(hb->heartbeat.oid);
return 0;
}
int
adf_heartbeat_dbg_del(struct adf_accel_dev *accel_dev)
{
+ struct sysctl_ctx_list *qat_sysctl_ctx;
+ struct adf_heartbeat *hb;
+
+ if (!accel_dev) {
+ return EINVAL;
+ }
+
+ hb = accel_dev->heartbeat;
+
+ qat_sysctl_ctx =
+ device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
+
+ if (hb->heartbeat.oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx, hb->heartbeat.oid);
+ sysctl_remove_oid(hb->heartbeat.oid, 1, 1);
+ hb->heartbeat.oid = NULL;
+ }
+
+ if (hb->heartbeat_failed.oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx, hb->heartbeat_failed.oid);
+ sysctl_remove_oid(hb->heartbeat_failed.oid, 1, 1);
+ hb->heartbeat_failed.oid = NULL;
+ }
+
+ if (hb->heartbeat_sent.oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx, hb->heartbeat_sent.oid);
+ sysctl_remove_oid(hb->heartbeat_sent.oid, 1, 1);
+ hb->heartbeat_sent.oid = NULL;
+ }
+
adf_heartbeat_clean(accel_dev);
+
return 0;
}
diff --git a/sys/dev/qat/qat_common/adf_freebsd_pfvf_ctrs_dbg.c b/sys/dev/qat/qat_common/adf_freebsd_pfvf_ctrs_dbg.c
--- a/sys/dev/qat/qat_common/adf_freebsd_pfvf_ctrs_dbg.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_pfvf_ctrs_dbg.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_accel_devices.h"
#include "adf_common_drv.h"
#include "adf_dev_err.h"
#include "adf_freebsd_pfvf_ctrs_dbg.h"
+#include <sys/priv.h>
#define MAX_REPORT_LINES (14)
#define MAX_REPORT_LINE_LEN (64)
@@ -92,6 +93,9 @@
struct pfvf_stats *pfvf_counters = arg1;
char report[MAX_REPORT_SIZE];
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (!pfvf_counters)
return EINVAL;
diff --git a/sys/dev/qat/qat_common/adf_freebsd_transport_debug.c b/sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
--- a/sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -14,6 +14,7 @@
#include <sys/sbuf.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
+#include <sys/priv.h>
static int adf_ring_show(SYSCTL_HANDLER_ARGS)
{
@@ -25,6 +26,9 @@
int error, word;
uint32_t *wp, *end;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
sbuf_new_for_sysctl(&sb, NULL, 128, req);
{
int head, tail, empty;
@@ -125,6 +129,9 @@
struct sbuf sb;
int error, ring_id;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
sbuf_new_for_sysctl(&sb, NULL, 128, req);
bank = arg1;
accel_dev = bank->accel_dev;
diff --git a/sys/dev/qat/qat_common/adf_freebsd_ver_dbg.c b/sys/dev/qat/qat_common/adf_freebsd_ver_dbg.c
--- a/sys/dev/qat/qat_common/adf_freebsd_ver_dbg.c
+++ b/sys/dev/qat/qat_common/adf_freebsd_ver_dbg.c
@@ -1,16 +1,20 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
#include "adf_accel_devices.h"
#include "adf_ver_dbg.h"
+#include <sys/priv.h>
static int adf_sysctl_read_fw_versions(SYSCTL_HANDLER_ARGS)
{
struct adf_accel_dev *accel_dev = arg1;
char fw_version[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (!accel_dev)
return -EINVAL;
@@ -34,6 +38,9 @@
struct adf_accel_dev *accel_dev = arg1;
char hw_version[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (!accel_dev)
return -EINVAL;
@@ -55,6 +62,9 @@
struct adf_accel_dev *accel_dev = arg1;
char mmp_version[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (!accel_dev)
return -EINVAL;
@@ -86,7 +96,6 @@
{
struct sysctl_ctx_list *qat_sysctl_ctx;
struct sysctl_oid *qat_sysctl_tree;
- struct sysctl_oid *rc = 0;
if (!accel_dev)
return -EINVAL;
@@ -96,43 +105,46 @@
qat_sysctl_tree =
device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev);
- rc = SYSCTL_ADD_OID(qat_sysctl_ctx,
- SYSCTL_CHILDREN(qat_sysctl_tree),
- OID_AUTO,
- "fw_version",
- CTLTYPE_STRING | CTLFLAG_RD,
- accel_dev,
- 0,
- adf_sysctl_read_fw_versions,
- "A",
- "QAT FW version");
- if (!rc)
+ accel_dev->fw_version_oid =
+ SYSCTL_ADD_OID(qat_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_sysctl_tree),
+ OID_AUTO,
+ "fw_version",
+ CTLTYPE_STRING | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ adf_sysctl_read_fw_versions,
+ "A",
+ "QAT FW version");
+ if (!accel_dev->fw_version_oid)
goto err;
- rc = SYSCTL_ADD_OID(qat_sysctl_ctx,
- SYSCTL_CHILDREN(qat_sysctl_tree),
- OID_AUTO,
- "hw_version",
- CTLTYPE_STRING | CTLFLAG_RD,
- accel_dev,
- 0,
- adf_sysctl_read_hw_versions,
- "A",
- "QAT HW version");
- if (!rc)
+ accel_dev->hw_version_oid =
+ SYSCTL_ADD_OID(qat_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_sysctl_tree),
+ OID_AUTO,
+ "hw_version",
+ CTLTYPE_STRING | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ adf_sysctl_read_hw_versions,
+ "A",
+ "QAT HW version");
+ if (!accel_dev->hw_version_oid)
goto err;
- rc = SYSCTL_ADD_OID(qat_sysctl_ctx,
- SYSCTL_CHILDREN(qat_sysctl_tree),
- OID_AUTO,
- "mmp_version",
- CTLTYPE_STRING | CTLFLAG_RD,
- accel_dev,
- 0,
- adf_sysctl_read_mmp_versions,
- "A",
- "QAT MMP version");
- if (!rc)
+ accel_dev->mmp_version_oid =
+ SYSCTL_ADD_OID(qat_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_sysctl_tree),
+ OID_AUTO,
+ "mmp_version",
+ CTLTYPE_STRING | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ adf_sysctl_read_mmp_versions,
+ "A",
+ "QAT MMP version");
+ if (!accel_dev->mmp_version_oid)
goto err;
return 0;
@@ -145,4 +157,30 @@
void
adf_ver_dbg_del(struct adf_accel_dev *accel_dev)
{
+ struct sysctl_ctx_list *qat_sysctl_ctx;
+
+ if (!accel_dev)
+ return;
+
+ qat_sysctl_ctx =
+ device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
+
+ if (accel_dev->mmp_version_oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx,
+ accel_dev->mmp_version_oid);
+ sysctl_remove_oid(accel_dev->mmp_version_oid, 1, 1);
+ accel_dev->mmp_version_oid = NULL;
+ }
+
+ if (accel_dev->hw_version_oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx, accel_dev->hw_version_oid);
+ sysctl_remove_oid(accel_dev->hw_version_oid, 1, 1);
+ accel_dev->hw_version_oid = NULL;
+ }
+
+ if (accel_dev->fw_version_oid) {
+ sysctl_ctx_entry_del(qat_sysctl_ctx, accel_dev->fw_version_oid);
+ sysctl_remove_oid(accel_dev->fw_version_oid, 1, 1);
+ accel_dev->fw_version_oid = NULL;
+ }
}
diff --git a/sys/dev/qat/qat_common/adf_fw_counters.c b/sys/dev/qat/qat_common/adf_fw_counters.c
--- a/sys/dev/qat/qat_common/adf_fw_counters.c
+++ b/sys/dev/qat/qat_common/adf_fw_counters.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <sys/types.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
@@ -9,6 +9,7 @@
#include "icp_qat_fw_init_admin.h"
#include <sys/mutex.h>
#include <sys/sbuf.h>
+#include <sys/priv.h>
#define ADF_FW_COUNTERS_BUF_SZ 4096
#define ADF_RAS_EVENT_STR "RAS events"
@@ -126,6 +127,9 @@
struct sbuf *sbuf = NULL;
char *cbuf = NULL;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (accel_dev == NULL) {
return EINVAL;
}
@@ -211,7 +215,6 @@
struct adf_fw_counters_data *fw_counters_data;
struct sysctl_ctx_list *qat_sysctl_ctx;
struct sysctl_oid *qat_sysctl_tree;
- struct sysctl_oid *rc = 0;
fw_counters_data =
malloc(sizeof(*fw_counters_data), M_QAT, M_WAITOK | M_ZERO);
@@ -225,20 +228,24 @@
device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
qat_sysctl_tree =
device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev);
- rc = SYSCTL_ADD_OID(qat_sysctl_ctx,
- SYSCTL_CHILDREN(qat_sysctl_tree),
- OID_AUTO,
- "fw_counters",
- CTLTYPE_STRING | CTLFLAG_RD,
- accel_dev,
- 0,
- adf_read_fw_counters,
- "A",
- "QAT FW counters");
- if (!rc)
+ fw_counters_data->debug =
+ SYSCTL_ADD_OID(qat_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_sysctl_tree),
+ OID_AUTO,
+ "fw_counters",
+ CTLTYPE_STRING | CTLFLAG_RD,
+ accel_dev,
+ 0,
+ adf_read_fw_counters,
+ "A",
+ "QAT FW counters");
+ if (!fw_counters_data->debug) {
+ free(fw_counters_data, M_QAT);
+ accel_dev->fw_counters_data = NULL;
return ENOMEM;
- else
- return 0;
+ }
+
+ return 0;
}
static void
@@ -396,12 +403,21 @@
void
adf_fw_counters_remove(struct adf_accel_dev *accel_dev)
{
+ struct sysctl_ctx_list *qat_sysctl_ctx;
struct adf_fw_counters_data *fw_counters_data =
accel_dev->fw_counters_data;
if (!fw_counters_data)
return;
+ if (fw_counters_data->debug) {
+ qat_sysctl_ctx =
+ device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
+ sysctl_ctx_entry_del(qat_sysctl_ctx, fw_counters_data->debug);
+ sysctl_remove_oid(fw_counters_data->debug, 1, 1);
+ fw_counters_data->debug = NULL;
+ }
+
down_write(&fw_counters_data->lock);
adf_fw_counters_section_del_all(&fw_counters_data->ae_sec_list);
up_write(&fw_counters_data->lock);
diff --git a/sys/dev/qat/qat_common/adf_gen2_hw_data.c b/sys/dev/qat/qat_common/adf_gen2_hw_data.c
--- a/sys/dev/qat/qat_common/adf_gen2_hw_data.c
+++ b/sys/dev/qat/qat_common/adf_gen2_hw_data.c
@@ -1,5 +1,5 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2021 Intel Corporation */
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_gen2_hw_data.h"
#include "icp_qat_hw.h"
@@ -54,7 +54,7 @@
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
}
-static dma_addr_t
+static bus_addr_t
read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring)
{
return READ_CSR_RING_BASE(csr_base_addr, bank, ring);
diff --git a/sys/dev/qat/qat_common/adf_gen4_pfvf.c b/sys/dev/qat/qat_common/adf_gen4_pfvf.c
--- a/sys/dev/qat/qat_common/adf_gen4_pfvf.c
+++ b/sys/dev/qat/qat_common/adf_gen4_pfvf.c
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <linux/iopoll.h>
-#include <linux/mutex.h>
#include <linux/types.h>
#include "adf_accel_devices.h"
#include "adf_common_drv.h"
diff --git a/sys/dev/qat/qat_common/adf_gen4vf_hw_csr_data.c b/sys/dev/qat/qat_common/adf_gen4vf_hw_csr_data.c
--- a/sys/dev/qat/qat_common/adf_gen4vf_hw_csr_data.c
+++ b/sys/dev/qat/qat_common/adf_gen4vf_hw_csr_data.c
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_accel_devices.h"
#include "adf_gen4vf_hw_csr_data.h"
static u64
-build_csr_ring_base_addr(dma_addr_t addr, u32 size)
+build_csr_ring_base_addr(bus_addr_t addr, u32 size)
{
return BUILD_RING_BASE_ADDR_GEN4(addr, size);
}
@@ -54,7 +54,7 @@
WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value);
}
-static dma_addr_t
+static bus_addr_t
read_csr_ring_base(struct resource *csr_base_addr, u32 bank, u32 ring)
{
return READ_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring);
@@ -64,7 +64,7 @@
write_csr_ring_base(struct resource *csr_base_addr,
u32 bank,
u32 ring,
- dma_addr_t addr)
+ bus_addr_t addr)
{
WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, addr);
}
diff --git a/sys/dev/qat/qat_common/adf_init.c b/sys/dev/qat/qat_common/adf_init.c
--- a/sys/dev/qat/qat_common/adf_init.c
+++ b/sys/dev/qat/qat_common/adf_init.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
+#include "adf_dbgfs.h"
#include "adf_accel_devices.h"
#include "icp_qat_uclo.h"
#include "icp_qat_fw.h"
@@ -19,6 +20,10 @@
#include "adf_common_drv.h"
#include "icp_qat_fw.h"
+#if defined(QAT_UIO)
+#include "adf_cfg_device.h"
+#endif /* QAT_UIO*/
+
/* Mask used to check the CompressAndVerify capability bit */
#define DC_CNV_EXTENDED_CAPABILITY (0x01)
@@ -28,6 +33,11 @@
static LIST_HEAD(service_table);
static DEFINE_MUTEX(service_lock);
+static int adf_dev_init_locked(struct adf_accel_dev *accel_dev);
+static int adf_dev_start_locked(struct adf_accel_dev *accel_dev);
+static int adf_dev_stop_locked(struct adf_accel_dev *accel_dev);
+static void adf_dev_shutdown_locked(struct adf_accel_dev *accel_dev);
+
static void
adf_service_add(struct service_hndl *service)
{
@@ -260,6 +270,18 @@
*/
int
adf_dev_init(struct adf_accel_dev *accel_dev)
+{
+ int ret = 0;
+
+ mutex_lock(&accel_dev->lock);
+ ret = adf_dev_init_locked(accel_dev);
+ mutex_unlock(&accel_dev->lock);
+
+ return ret;
+}
+
+static int
+adf_dev_init_locked(struct adf_accel_dev *accel_dev)
{
struct service_hndl *service;
struct list_head *list_itr;
@@ -409,18 +431,24 @@
*/
int
adf_dev_start(struct adf_accel_dev *accel_dev)
+{
+ int ret = 0;
+
+ mutex_lock(&accel_dev->lock);
+ ret = adf_dev_start_locked(accel_dev);
+ mutex_unlock(&accel_dev->lock);
+
+ return ret;
+}
+
+static int
+adf_dev_start_locked(struct adf_accel_dev *accel_dev)
{
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
struct service_hndl *service;
struct list_head *list_itr;
set_bit(ADF_STATUS_STARTING, &accel_dev->status);
- if (adf_devmgr_verify_id(&accel_dev->accel_id)) {
- device_printf(GET_DEV(accel_dev),
- "QAT: Device %d not found\n",
- accel_dev->accel_id);
- return ENODEV;
- }
if (adf_ae_start(accel_dev)) {
device_printf(GET_DEV(accel_dev), "AE Start Failed\n");
return EFAULT;
@@ -489,6 +517,8 @@
clear_bit(ADF_STATUS_STARTING, &accel_dev->status);
set_bit(ADF_STATUS_STARTED, &accel_dev->status);
+ adf_dbgfs_add(accel_dev);
+
return 0;
}
@@ -504,16 +534,25 @@
*/
int
adf_dev_stop(struct adf_accel_dev *accel_dev)
+{
+ int ret = 0;
+
+ mutex_lock(&accel_dev->lock);
+ ret = adf_dev_stop_locked(accel_dev);
+ mutex_unlock(&accel_dev->lock);
+
+ return ret;
+}
+
+static int
+adf_dev_stop_locked(struct adf_accel_dev *accel_dev)
{
struct service_hndl *service;
struct list_head *list_itr;
- if (adf_devmgr_verify_id(&accel_dev->accel_id)) {
- device_printf(GET_DEV(accel_dev),
- "QAT: Device %d not found\n",
- accel_dev->accel_id);
- return ENODEV;
- }
+ if (!test_bit(ADF_STATUS_CONFIGURED, &accel_dev->status))
+ return 0;
+
if (!adf_dev_started(accel_dev) &&
!test_bit(ADF_STATUS_STARTING, &accel_dev->status)) {
return 0;
@@ -526,6 +565,8 @@
return EBUSY;
}
+ adf_dbgfs_rm(accel_dev);
+
clear_bit(ADF_STATUS_STARTING, &accel_dev->status);
clear_bit(ADF_STATUS_STARTED, &accel_dev->status);
@@ -565,11 +606,22 @@
*/
void
adf_dev_shutdown(struct adf_accel_dev *accel_dev)
+{
+ mutex_lock(&accel_dev->lock);
+ adf_dev_shutdown_locked(accel_dev);
+ mutex_unlock(&accel_dev->lock);
+}
+
+static void
+adf_dev_shutdown_locked(struct adf_accel_dev *accel_dev)
{
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
struct service_hndl *service;
struct list_head *list_itr;
+ if (!test_bit(ADF_STATUS_CONFIGURED, &accel_dev->status))
+ return;
+
if (test_bit(ADF_STATUS_SYSCTL_CTX_INITIALISED, &accel_dev->status)) {
sysctl_ctx_free(&accel_dev->sysctl_ctx);
clear_bit(ADF_STATUS_SYSCTL_CTX_INITIALISED,
@@ -618,8 +670,12 @@
}
/* Delete configuration only if not restarting */
- if (!test_bit(ADF_STATUS_RESTARTING, &accel_dev->status))
+ if (!test_bit(ADF_STATUS_RESTARTING, &accel_dev->status)) {
adf_cfg_del_all(accel_dev);
+#ifdef QAT_UIO
+ adf_cfg_device_clear_all(accel_dev);
+#endif
+ }
if (hw_data->remove_pke_stats)
hw_data->remove_pke_stats(accel_dev);
diff --git a/sys/dev/qat/qat_common/adf_pfvf_vf_msg.c b/sys/dev/qat/qat_common/adf_pfvf_vf_msg.c
--- a/sys/dev/qat/qat_common/adf_pfvf_vf_msg.c
+++ b/sys/dev/qat/qat_common/adf_pfvf_vf_msg.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <linux/bitfield.h>
#include "adf_accel_devices.h"
#include "adf_common_drv.h"
@@ -98,6 +98,22 @@
return 0;
}
+void
+adf_vf2pf_restarting_complete(struct adf_accel_dev *accel_dev)
+{
+ struct pfvf_message msg = { .type =
+ ADF_VF2PF_MSGTYPE_RESTARTING_COMPLETE };
+
+ if (accel_dev->u1.vf.pf_compat_ver < ADF_PFVF_COMPAT_FALLBACK)
+ return;
+
+ if (adf_send_vf2pf_msg(accel_dev, msg)) {
+ device_printf(
+ GET_DEV(accel_dev),
+ "Failed to send Restarting complete event to PF\n");
+ }
+}
+
int
adf_vf2pf_get_capabilities(struct adf_accel_dev *accel_dev)
{
@@ -180,5 +196,7 @@
/* Only v1 at present */
accel_dev->hw_device->ring_to_svc_map = rts_map_msg.map;
+ accel_dev->hw_device->get_ring_to_svc_done = true;
+
return 0;
}
diff --git a/sys/dev/qat/qat_common/adf_pfvf_vf_proto.c b/sys/dev/qat/qat_common/adf_pfvf_vf_proto.c
--- a/sys/dev/qat/qat_common/adf_pfvf_vf_proto.c
+++ b/sys/dev/qat/qat_common/adf_pfvf_vf_proto.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <linux/kernel.h>
#include "adf_accel_devices.h"
#include "adf_common_drv.h"
@@ -89,9 +89,15 @@
}
/* Wait for response, if it times out retry */
- ret =
- wait_for_completion_timeout(&accel_dev->u1.vf.msg_received,
- timeout);
+ if (!cold) {
+ ret = wait_for_completion_timeout(
+ &accel_dev->u1.vf.msg_received, timeout);
+ } else {
+ /* In cold start timers may not be initialized yet */
+ DELAY(ADF_PFVF_MSG_RESP_TIMEOUT * 1000);
+ ret = try_wait_for_completion(
+ &accel_dev->u1.vf.msg_received);
+ }
if (ret) {
if (likely(resp))
*resp = accel_dev->u1.vf.response;
@@ -346,6 +352,9 @@
case ADF_PF2VF_MSGTYPE_RP_RESET_RESP:
adf_pf2vf_handle_pf_rp_reset(accel_dev, msg);
return true;
+ case ADF_PF2VF_MSGTYPE_FATAL_ERROR:
+ adf_pf2vf_handle_pf_error(accel_dev);
+ return true;
case ADF_PF2VF_MSGTYPE_VERSION_RESP:
case ADF_PF2VF_MSGTYPE_BLKMSG_RESP:
accel_dev->u1.vf.response = msg;
diff --git a/sys/dev/qat/qat_common/adf_vf_isr.c b/sys/dev/qat/qat_common/adf_vf_isr.c
--- a/sys/dev/qat/qat_common/adf_vf_isr.c
+++ b/sys/dev/qat/qat_common/adf_vf_isr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include <sys/kernel.h>
#include <sys/systm.h>
@@ -17,6 +17,7 @@
#include "adf_transport_access_macros.h"
#include "adf_transport_internal.h"
#include "adf_pfvf_utils.h"
+#include "adf_pfvf_vf_msg.h"
static TASKQUEUE_DEFINE_THREAD(qat_vf);
static TASKQUEUE_DEFINE_THREAD(qat_bank_handler);
@@ -65,6 +66,7 @@
/* Re-enable PF2VF interrupts */
hw_data->enable_pf2vf_interrupt(accel_dev);
+ adf_vf2pf_restarting_complete(accel_dev);
kfree(stop_data);
}
@@ -123,6 +125,17 @@
return 0;
}
+int
+adf_pf2vf_handle_pf_error(struct adf_accel_dev *accel_dev)
+{
+ device_printf(GET_DEV(accel_dev), "Fatal error received from PF\n");
+
+ if (adf_notify_fatal_error(accel_dev))
+ device_printf(GET_DEV(accel_dev), "Couldn't notify fatal error\n");
+
+ return 0;
+}
+
static void
adf_pf2vf_bh_handler(void *data, int pending)
{
diff --git a/sys/dev/qat/qat_common/qat_hal.c b/sys/dev/qat/qat_common/qat_hal.c
--- a/sys/dev/qat/qat_common/qat_hal.c
+++ b/sys/dev/qat/qat_common/qat_hal.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -1052,8 +1052,7 @@
handle->hal_cap_ae_xfer_csr_addr_v = ae_offset;
handle->hal_ep_csr_addr_v = ep_offset;
handle->hal_cap_ae_local_csr_addr_v =
- ((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v +
- LOCAL_TO_XFER_REG_OFFSET);
+ ((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v + LOCAL_TO_XFER_REG_OFFSET);
handle->fw_auth = (pci_get_device(GET_DEV(handle->accel_dev)) ==
ADF_DH895XCC_PCI_DEVICE_ID) ?
false :
@@ -1283,7 +1282,7 @@
unsigned int max_cycle,
unsigned int *endpc)
{
- uint64_t savuwords[MAX_EXEC_INST];
+ u64 *savuwords = NULL;
unsigned int ind_lm_addr0, ind_lm_addr1;
unsigned int ind_lm_addr2, ind_lm_addr3;
unsigned int ind_lm_addr_byte0, ind_lm_addr_byte1;
@@ -1300,6 +1299,11 @@
pr_err("QAT: invalid instruction num %d\n", inst_num);
return EINVAL;
}
+
+ savuwords = kzalloc(sizeof(u64) * MAX_EXEC_INST, GFP_KERNEL);
+ if (!savuwords)
+ return ENOMEM;
+
/* save current context */
qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT, &ind_lm_addr0);
qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT, &ind_lm_addr1);
@@ -1360,8 +1364,10 @@
qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);
qat_hal_enable_ctx(handle, ae, (1 << ctx));
/* wait for micro codes to finish */
- if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0)
+ if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0) {
+ kfree(savuwords);
return EFAULT;
+ }
if (endpc) {
unsigned int ctx_status;
@@ -1429,6 +1435,7 @@
handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, ind_sig);
qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig);
qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);
+ kfree(savuwords);
return 0;
}
diff --git a/sys/dev/qat/qat_common/qat_uclo.c b/sys/dev/qat/qat_common/qat_uclo.c
--- a/sys/dev/qat/qat_common/qat_uclo.c
+++ b/sys/dev/qat/qat_common/qat_uclo.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -1618,11 +1618,17 @@
unsigned int length, simg_offset = sizeof(*auth_chunk);
unsigned int device_id = pci_get_device(GET_DEV(handle->accel_dev));
+ if (size <= ICP_QAT_AE_IMG_OFFSET(device_id)) {
+ pr_err("QAT: error, input image size too small %d\n", size);
+ return EINVAL;
+ }
+
if (size >
(ICP_QAT_AE_IMG_OFFSET(device_id) + ICP_QAT_CSS_MAX_IMAGE_LEN)) {
pr_err("QAT: error, input image size overflow %d\n", size);
return EINVAL;
}
+
length = (css_hdr->fw_type == CSS_AE_FIRMWARE) ?
ICP_QAT_CSS_AE_SIMG_LEN(device_id) + simg_offset :
size + ICP_QAT_CSS_FWSK_PAD_LEN(device_id) + simg_offset;
@@ -1824,11 +1830,6 @@
GET_DEV(handle->accel_dev)));
return status;
}
- if (pci_get_device(GET_DEV(handle->accel_dev)) ==
- ADF_C3XXX_PCI_DEVICE_ID) {
- pr_err("QAT: C3XXX doesn't support unsigned MMP\n");
- return EINVAL;
- }
status = qat_uclo_wr_sram_by_words(handle,
handle->hal_sram_offset,
addr_ptr,
diff --git a/sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.h b/sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.h
--- a/sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.h
+++ b/sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.h
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_200XX_HW_DATA_H_
#define ADF_200XX_HW_DATA_H_
/* PCIe configuration space */
-#define ADF_200XX_PMISC_BAR 0
-#define ADF_200XX_ETR_BAR 1
+#define ADF_200XX_PMISC_BAR 1
+#define ADF_200XX_ETR_BAR 2
#define ADF_200XX_RX_RINGS_OFFSET 8
#define ADF_200XX_TX_RINGS_MASK 0xFF
#define ADF_200XX_MAX_ACCELERATORS 3
diff --git a/sys/dev/qat/qat_hw/qat_200xx/adf_drv.c b/sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_200xx/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -7,13 +7,12 @@
#include "adf_200xx_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <machine/bus_dma.h>
#include <dev/pci/pcireg.h>
-#include "adf_heartbeat_dbg.h"
-#include "adf_cnvnr_freq_counters.h"
static MALLOC_DEFINE(M_QAT_200XX, "qat_200xx", "qat_200xx");
@@ -73,6 +72,7 @@
free(accel_dev->hw_device, M_QAT_200XX);
accel_dev->hw_device = NULL;
}
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
adf_devmgr_rm_dev(accel_dev, NULL);
}
@@ -84,7 +84,7 @@
struct adf_accel_pci *accel_pci_dev;
struct adf_hw_device_data *hw_data;
unsigned int i = 0, bar_nr = 0, reg_val = 0;
- int ret, rid;
+ int ret = 0, rid;
struct adf_cfg_device *cfg_dev = NULL;
/* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
@@ -96,6 +96,7 @@
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
INIT_LIST_HEAD(&accel_dev->crypto_list);
accel_pci_dev = &accel_dev->accel_pci_dev;
accel_pci_dev->pci_dev = dev;
@@ -108,9 +109,10 @@
/* Add accel device to accel table.
* This should be called before adf_cleanup_accel is called
*/
- if (adf_devmgr_add_dev(accel_dev, NULL)) {
+ ret = adf_devmgr_add_dev(accel_dev, NULL);
+ if (ret) {
device_printf(dev, "Failed to add new accelerator device.\n");
- return ENXIO;
+ goto out_err_lock;
}
/* Allocate and configure device configuration structure */
@@ -215,6 +217,8 @@
}
pci_enable_busmaster(dev);
+ adf_dbgfs_init(accel_dev);
+
if (!accel_dev->hw_device->config_device) {
ret = EFAULT;
goto out_err;
@@ -243,6 +247,9 @@
adf_dev_shutdown(accel_dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -259,6 +266,7 @@
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
return 0;
}
diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
--- a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
+++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007 - 2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_4XXX_HW_DATA_H_
#define ADF_4XXX_HW_DATA_H_
@@ -105,7 +105,7 @@
ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3),
ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4),
ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5),
- ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6),
+ ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(7),
};
void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id);
diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
--- a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
+++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <linux/iopoll.h>
#include <adf_accel_devices.h>
#include <adf_cfg.h>
@@ -212,57 +212,77 @@
{
device_t pdev = accel_dev->accel_pci_dev.pci_dev;
u32 fusectl1;
- u32 capabilities;
+ u32 capabilities_sym, capabilities_sym_cipher, capabilities_sym_auth,
+ capabilities_asym, capabilities_dc, capabilities_other;
+
+ capabilities_other = ICP_ACCEL_CAPABILITIES_RL;
/* Read accelerator capabilities mask */
fusectl1 = pci_read_config(pdev, ADF_4XXX_FUSECTL1_OFFSET, 4);
- capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
- ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
- ICP_ACCEL_CAPABILITIES_CIPHER |
- ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
- ICP_ACCEL_CAPABILITIES_COMPRESSION |
- ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
- ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
- ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_HKDF |
- ICP_ACCEL_CAPABILITIES_SHA3_EXT | ICP_ACCEL_CAPABILITIES_SM3 |
+
+ capabilities_sym_cipher = ICP_ACCEL_CAPABILITIES_HKDF |
ICP_ACCEL_CAPABILITIES_SM4 | ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
- ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2 |
- ICP_ACCEL_CAPABILITIES_RL | ICP_ACCEL_CAPABILITIES_ECEDMONT |
- ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+ ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2;
+ capabilities_sym_auth = ICP_ACCEL_CAPABILITIES_SM3 |
+ ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_SHA3_EXT;
+ /* A set bit in fusectl1 means the feature is OFF in this SKU */
if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_HKDF;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
- }
- if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_HKDF;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
}
- if (fusectl1 & ICP_ACCEL_MASK_PKE_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
}
- if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
}
+
if (fusectl1 & ICP_ACCEL_4XXX_MASK_SMX_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SM3;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SM4;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
}
- if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ if (capabilities_sym_cipher)
+ capabilities_sym_cipher |= ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ if (capabilities_sym_auth)
+ capabilities_sym_auth |= ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+
+ capabilities_sym = capabilities_sym_cipher | capabilities_sym_auth;
+
+ if (capabilities_sym)
+ capabilities_sym |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
+
+ capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_SM2 | ICP_ACCEL_CAPABILITIES_ECEDMONT;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
+ }
+
+ capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
}
- return capabilities;
+ return capabilities_sym | capabilities_dc | capabilities_asym |
+ capabilities_other;
}
static u32
@@ -709,6 +729,10 @@
memset(&req, 0, sizeof(req));
memset(&resp, 0, sizeof(resp));
req.cmd_id = ICP_QAT_FW_INIT_ME;
+#ifdef QAT_DISABLE_SAFE_DC_MODE
+ if (accel_dev->disable_safe_dc_mode)
+ req.fw_flags = ICP_QAT_FW_INIT_DISABLE_SAFE_DC_MODE_FLAG;
+#endif /* QAT_DISABLE_SAFE_DC_MODE */
if (adf_send_admin(accel_dev, &req, &resp, ae_mask)) {
device_printf(GET_DEV(accel_dev),
"Error sending init message\n");
@@ -989,6 +1013,9 @@
hw_data->get_hb_clock = get_hb_clock;
hw_data->int_timer_init = adf_int_timer_init;
hw_data->int_timer_exit = adf_int_timer_exit;
+ hw_data->pre_reset = adf_dev_pre_reset;
+ hw_data->post_reset = adf_dev_post_reset;
+ hw_data->disable_arb = adf_disable_arb;
hw_data->get_heartbeat_status = adf_get_heartbeat_status;
hw_data->get_ae_clock = get_ae_clock;
hw_data->measure_clock = measure_clock;
diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_drv.c b/sys/dev/qat/qat_hw/qat_4xxx/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_4xxx/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007 - 2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -8,13 +8,12 @@
#include "adf_gen4_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <machine/bus_dma.h>
#include <dev/pci/pcireg.h>
-#include "adf_heartbeat_dbg.h"
-#include "adf_cnvnr_freq_counters.h"
static MALLOC_DEFINE(M_QAT_4XXX, "qat_4xxx", "qat_4xxx");
@@ -47,6 +46,74 @@
return ENXIO;
}
+#ifdef QAT_DISABLE_SAFE_DC_MODE
+static int adf_4xxx_sysctl_disable_safe_dc_mode(SYSCTL_HANDLER_ARGS)
+{
+ struct adf_accel_dev *accel_dev = arg1;
+ int error, value = accel_dev->disable_safe_dc_mode;
+
+ error = sysctl_handle_int(oidp, &value, 0, req);
+ if (error || !req->newptr)
+ return error;
+
+ if (value != 1 && value != 0)
+ return EINVAL;
+
+ if (adf_dev_started(accel_dev)) {
+ device_printf(
+ GET_DEV(accel_dev),
+ "QAT: configuration can only be changed in \"down\" device state\n");
+ return EBUSY;
+ }
+
+ accel_dev->disable_safe_dc_mode = (u8)value;
+
+ return 0;
+}
+
+static void
+adf_4xxx_disable_safe_dc_sysctl_add(struct adf_accel_dev *accel_dev)
+{
+ struct sysctl_ctx_list *qat_sysctl_ctx;
+ struct sysctl_oid *qat_sysctl_tree;
+
+ qat_sysctl_ctx =
+ device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
+ qat_sysctl_tree =
+ device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev);
+ accel_dev->safe_dc_mode =
+ SYSCTL_ADD_OID(qat_sysctl_ctx,
+ SYSCTL_CHILDREN(qat_sysctl_tree),
+ OID_AUTO,
+ "disable_safe_dc_mode",
+ CTLTYPE_INT | CTLFLAG_WR | CTLFLAG_TUN |
+ CTLFLAG_SKIP,
+ accel_dev,
+ 0,
+ adf_4xxx_sysctl_disable_safe_dc_mode,
+ "LU",
+ "Disable QAT safe data compression mode");
+}
+
+static void
+adf_4xxx_disable_safe_dc_sysctl_remove(struct adf_accel_dev *accel_dev)
+{
+ int ret;
+ struct sysctl_ctx_list *qat_sysctl_ctx =
+ device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev);
+
+ ret = sysctl_ctx_entry_del(qat_sysctl_ctx, accel_dev->safe_dc_mode);
+ if (ret) {
+ device_printf(GET_DEV(accel_dev), "Failed to delete entry\n");
+ } else {
+ ret = sysctl_remove_oid(accel_dev->safe_dc_mode, 1, 1);
+ if (ret)
+ device_printf(GET_DEV(accel_dev),
+ "Failed to delete oid\n");
+ }
+}
+#endif /* QAT_DISABLE_SAFE_DC_MODE */
+
static void
adf_cleanup_accel(struct adf_accel_dev *accel_dev)
{
@@ -76,6 +143,10 @@
free(accel_dev->hw_device, M_QAT_4XXX);
accel_dev->hw_device = NULL;
}
+#ifdef QAT_DISABLE_SAFE_DC_MODE
+ adf_4xxx_disable_safe_dc_sysctl_remove(accel_dev);
+#endif /* QAT_DISABLE_SAFE_DC_MODE */
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
adf_devmgr_rm_dev(accel_dev, NULL);
}
@@ -87,7 +158,7 @@
struct adf_accel_pci *accel_pci_dev;
struct adf_hw_device_data *hw_data;
unsigned int bar_nr;
- int ret, rid;
+ int ret = 0, rid;
struct adf_cfg_device *cfg_dev = NULL;
/* Set pci MaxPayLoad to 512. Implemented to avoid the issue of
@@ -99,6 +170,7 @@
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
INIT_LIST_HEAD(&accel_dev->crypto_list);
accel_pci_dev = &accel_dev->accel_pci_dev;
accel_pci_dev->pci_dev = dev;
@@ -109,9 +181,10 @@
/* Add accel device to accel table.
* This should be called before adf_cleanup_accel is called
*/
- if (adf_devmgr_add_dev(accel_dev, NULL)) {
+ ret = adf_devmgr_add_dev(accel_dev, NULL);
+ if (ret) {
device_printf(dev, "Failed to add new accelerator device.\n");
- return ENXIO;
+ goto out_err_lock;
}
/* Allocate and configure device configuration structure */
@@ -121,11 +194,6 @@
adf_init_hw_data_4xxx(accel_dev->hw_device, pci_get_device(dev));
accel_pci_dev->revid = pci_get_revid(dev);
hw_data->fuses = pci_read_config(dev, ADF_4XXX_FUSECTL4_OFFSET, 4);
- if (accel_pci_dev->revid == 0x00) {
- device_printf(dev, "A0 stepping is not supported.\n");
- ret = ENODEV;
- goto out_err;
- }
/* Get PPAERUCM values and store */
ret = adf_aer_store_ppaerucm_reg(dev, hw_data);
@@ -153,6 +221,10 @@
if (ret)
goto out_err;
+#ifdef QAT_DISABLE_SAFE_DC_MODE
+ adf_4xxx_disable_safe_dc_sysctl_add(accel_dev);
+#endif /* QAT_DISABLE_SAFE_DC_MODE */
+
pci_set_max_read_req(dev, 4096);
ret = bus_dma_tag_create(bus_get_dma_tag(dev),
@@ -205,6 +277,8 @@
}
pci_enable_busmaster(dev);
+ adf_dbgfs_init(accel_dev);
+
if (!accel_dev->hw_device->config_device) {
ret = EFAULT;
goto out_err;
@@ -233,6 +307,9 @@
adf_dev_shutdown(accel_dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -249,6 +326,7 @@
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
return 0;
}
diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
--- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
+++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_4XXXVF_HW_DATA_H_
#define ADF_4XXXVF_HW_DATA_H_
@@ -27,6 +27,18 @@
#define ADF_4XXXIOV_VFFUSECTL4_OFFSET (0x1C4)
#define ADF_4XXXIOV_VFFUSECTL5_OFFSET (0x1C8)
+/*qat_4xxxvf fuse bits are same as qat_4xxx*/
+enum icp_qat_4xxxvf_slice_mask {
+ ICP_ACCEL_4XXXVF_MASK_CIPHER_SLICE = 0x01,
+ ICP_ACCEL_4XXXVF_MASK_AUTH_SLICE = 0x02,
+ ICP_ACCEL_4XXXVF_MASK_PKE_SLICE = 0x04,
+ ICP_ACCEL_4XXXVF_MASK_COMPRESS_SLICE = 0x08,
+ ICP_ACCEL_4XXXVF_MASK_UCS_SLICE = 0x10,
+ ICP_ACCEL_4XXXVF_MASK_EIA3_SLICE = 0x20,
+ /*SM3&SM4 are indicated by same bit*/
+ ICP_ACCEL_4XXXVF_MASK_SMX_SLICE = 0x80,
+};
+
void adf_init_hw_data_4xxxiov(struct adf_hw_device_data *hw_data);
void adf_clean_hw_data_4xxxiov(struct adf_hw_device_data *hw_data);
u32 adf_4xxxvf_get_hw_cap(struct adf_accel_dev *accel_dev);
diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
--- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
+++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <adf_accel_devices.h>
#include <adf_cfg.h>
#include <adf_common_drv.h>
@@ -133,45 +133,74 @@
{
device_t pdev = accel_dev->accel_pci_dev.pci_dev;
u32 vffusectl1;
- u32 capabilities;
-
- capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC +
- ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC +
- ICP_ACCEL_CAPABILITIES_CIPHER +
- ICP_ACCEL_CAPABILITIES_AUTHENTICATION +
- ICP_ACCEL_CAPABILITIES_COMPRESSION +
- ICP_ACCEL_CAPABILITIES_SHA3_EXT + ICP_ACCEL_CAPABILITIES_SM2 +
- ICP_ACCEL_CAPABILITIES_SM3 + ICP_ACCEL_CAPABILITIES_SM4 +
- ICP_ACCEL_CAPABILITIES_CHACHA_POLY +
- ICP_ACCEL_CAPABILITIES_AESGCM_SPC +
- ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 +
- ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION +
- ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+ u32 capabilities_sym, capabilities_sym_cipher, capabilities_sym_auth,
+ capabilities_asym, capabilities_dc;
/* Get fused capabilities */
vffusectl1 = pci_read_config(pdev, ADF_4XXXIOV_VFFUSECTL1_OFFSET, 4);
- if (vffusectl1 & BIT(7)) {
- capabilities &=
- ~(ICP_ACCEL_CAPABILITIES_SM3 + ICP_ACCEL_CAPABILITIES_SM4);
+ capabilities_sym_cipher = ICP_ACCEL_CAPABILITIES_HKDF |
+ ICP_ACCEL_CAPABILITIES_SM4 | ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
+ ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2;
+ capabilities_sym_auth = ICP_ACCEL_CAPABILITIES_SM3 |
+ ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_SHA3_EXT;
+
+ /* A set bit in vffusectl1 means the feature is OFF in this SKU */
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_CIPHER_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_HKDF;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
}
- if (vffusectl1 & BIT(6)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SM3;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_UCS_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
}
- if (vffusectl1 & BIT(3)) {
- capabilities &= ~(ICP_ACCEL_CAPABILITIES_COMPRESSION +
- ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64);
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_AUTH_SLICE) {
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
}
- if (vffusectl1 & BIT(2)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_SMX_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
}
- if (vffusectl1 & BIT(1)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+
+ if (capabilities_sym_cipher)
+ capabilities_sym_cipher |= ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ if (capabilities_sym_auth)
+ capabilities_sym_auth |= ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+
+ capabilities_sym = capabilities_sym_cipher | capabilities_sym_auth;
+
+ if (capabilities_sym)
+ capabilities_sym |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
+
+ capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_SM2 | ICP_ACCEL_CAPABILITIES_ECEDMONT;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_PKE_SLICE) {
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
}
- if (vffusectl1 & BIT(0)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_COMPRESS_SLICE) {
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
}
- return capabilities;
+
+ return capabilities_sym | capabilities_dc | capabilities_asym;
}
static void
@@ -265,6 +294,9 @@
char val[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
u32 i = 0;
+ if (accel_dev->hw_device->get_ring_to_svc_done)
+ return 0;
+
/* Get the services enabled by user if provided.
* The function itself will also be called during the driver probe
* procedure where no ServicesEnable is provided. Then the device
diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_drv.c b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include <adf_accel_devices.h>
#include <adf_common_drv.h>
@@ -8,6 +8,7 @@
#include "adf_gen4_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
@@ -83,6 +84,7 @@
free(accel_dev->hw_device, M_QAT_4XXXVF);
accel_dev->hw_device = NULL;
}
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
}
@@ -99,6 +101,7 @@
struct adf_cfg_device *cfg_dev = NULL;
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
accel_dev->is_vf = true;
pf = adf_devmgr_pci_to_accel_dev(pci_find_pf(dev));
@@ -110,11 +113,13 @@
accel_pci_dev->node = 0;
/* Add accel device to accel table */
- if (adf_devmgr_add_dev(accel_dev, pf)) {
+ ret = adf_devmgr_add_dev(accel_dev, pf);
+ if (ret) {
device_printf(GET_DEV(accel_dev),
"Failed to add new accelerator device.\n");
- return -EFAULT;
+ goto out_err_lock;
}
+
/* Allocate and configure device configuration structure */
hw_data = malloc(sizeof(*hw_data), M_QAT_4XXXVF, M_WAITOK | M_ZERO);
accel_dev->hw_device = hw_data;
@@ -150,6 +155,8 @@
NULL,
NULL,
&accel_dev->dma_tag);
+ if (ret)
+ goto out_err;
hw_data->accel_capabilities_mask = adf_4xxxvf_get_hw_cap(accel_dev);
@@ -178,7 +185,11 @@
bar->base_addr = rman_get_start(bar->virt_addr);
bar->size = rman_get_size(bar->virt_addr);
}
- pci_enable_busmaster(dev);
+ ret = pci_enable_busmaster(dev);
+ if (ret)
+ goto out_err;
+
+ adf_dbgfs_init(accel_dev);
/* Completion for VF2PF request/response message exchange */
init_completion(&accel_dev->u1.vf.msg_received);
@@ -186,7 +197,7 @@
ret = hw_data->config_device(accel_dev);
if (ret)
- goto out_err;
+ goto out_err_disable;
ret = adf_dev_init(accel_dev);
if (!ret)
@@ -208,8 +219,13 @@
return ret;
+out_err_disable:
+ pci_disable_busmaster(dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -228,6 +244,7 @@
adf_dev_stop(accel_dev);
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
return 0;
}
diff --git a/sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.h b/sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.h
--- a/sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.h
+++ b/sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.h
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_C3XXX_HW_DATA_H_
#define ADF_C3XXX_HW_DATA_H_
/* PCIe configuration space */
-#define ADF_C3XXX_PMISC_BAR 0
-#define ADF_C3XXX_ETR_BAR 1
+#define ADF_C3XXX_PMISC_BAR 1
+#define ADF_C3XXX_ETR_BAR 2
#define ADF_C3XXX_RX_RINGS_OFFSET 8
#define ADF_C3XXX_TX_RINGS_MASK 0xFF
#define ADF_C3XXX_MAX_ACCELERATORS 3
diff --git a/sys/dev/qat/qat_hw/qat_c3xxx/adf_drv.c b/sys/dev/qat/qat_hw/qat_c3xxx/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_c3xxx/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_c3xxx/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -7,13 +7,12 @@
#include "adf_c3xxx_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <machine/bus_dma.h>
#include <dev/pci/pcireg.h>
-#include "adf_heartbeat_dbg.h"
-#include "adf_cnvnr_freq_counters.h"
static MALLOC_DEFINE(M_QAT_C3XXX, "qat_c3xxx", "qat_c3xxx");
@@ -73,6 +72,7 @@
free(accel_dev->hw_device, M_QAT_C3XXX);
accel_dev->hw_device = NULL;
}
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
adf_devmgr_rm_dev(accel_dev, NULL);
}
@@ -84,7 +84,7 @@
struct adf_accel_pci *accel_pci_dev;
struct adf_hw_device_data *hw_data;
unsigned int i, bar_nr;
- int ret, rid;
+ int ret = 0, rid;
struct adf_cfg_device *cfg_dev = NULL;
/* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
@@ -95,6 +95,7 @@
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
INIT_LIST_HEAD(&accel_dev->crypto_list);
accel_pci_dev = &accel_dev->accel_pci_dev;
accel_pci_dev->pci_dev = dev;
@@ -106,9 +107,10 @@
/* Add accel device to accel table.
* This should be called before adf_cleanup_accel is called */
- if (adf_devmgr_add_dev(accel_dev, NULL)) {
+ ret = adf_devmgr_add_dev(accel_dev, NULL);
+ if (ret) {
device_printf(dev, "Failed to add new accelerator device.\n");
- return ENXIO;
+ goto out_err_lock;
}
/* Allocate and configure device configuration structure */
@@ -204,6 +206,8 @@
}
pci_enable_busmaster(dev);
+ adf_dbgfs_init(accel_dev);
+
if (!accel_dev->hw_device->config_device) {
ret = EFAULT;
goto out_err;
@@ -232,6 +236,9 @@
adf_dev_shutdown(accel_dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -248,6 +255,7 @@
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
return 0;
}
diff --git a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ae_config.c b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ae_config.c
--- a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ae_config.c
+++ b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ae_config.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_c4xxx_hw_data.h"
#include <linux/kernel.h>
#include <linux/types.h>
@@ -9,6 +9,7 @@
#include <linux/io.h>
#include <sys/sbuf.h>
#include <sys/sysctl.h>
+#include <sys/priv.h>
#include <adf_accel_devices.h>
#include <adf_common_drv.h>
#include <adf_cfg.h>
@@ -59,6 +60,10 @@
u8 ae_index;
u8 num_aes;
int ret = 0;
+
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
u32 num_au = hw_data->get_num_accel_units(hw_data);
sbuf_new_for_sysctl(&sb, NULL, 2048, req);
diff --git a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
--- a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
+++ b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <linux/atomic.h>
#include <linux/compiler.h>
#include <adf_accel_devices.h>
@@ -858,10 +858,10 @@
if (!au_info->asym_ae_msk)
disabled_caps = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
- ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
-
+ ICP_ACCEL_CAPABILITIES_ECEDMONT;
if (!au_info->sym_ae_msk)
disabled_caps |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
ICP_ACCEL_CAPABILITIES_CIPHER | ICP_ACCEL_CAPABILITIES_ZUC |
ICP_ACCEL_CAPABILITIES_SHA3_EXT |
ICP_ACCEL_CAPABILITIES_SM3 | ICP_ACCEL_CAPABILITIES_SM4 |
diff --git a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_misc_error_stats.c b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_misc_error_stats.c
--- a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_misc_error_stats.c
+++ b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_misc_error_stats.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_c4xxx_hw_data.h"
#include "adf_c4xxx_misc_error_stats.h"
#include "adf_common_drv.h"
#include "adf_cfg_common.h"
#include <sys/sbuf.h>
#include <sys/sysctl.h>
+#include <sys/priv.h>
#define MISC_ERROR_DBG_FILE "misc_error_stats"
#define LINE \
@@ -23,6 +24,9 @@
{
struct sbuf sb;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
sbuf_new_for_sysctl(&sb, NULL, 256, req);
sbuf_printf(&sb, "\n");
sbuf_printf(&sb, LINE);
diff --git a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_pke_replay_stats.c b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_pke_replay_stats.c
--- a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_pke_replay_stats.c
+++ b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_pke_replay_stats.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_c4xxx_hw_data.h"
#include "adf_c4xxx_pke_replay_stats.h"
#include "adf_common_drv.h"
#include "icp_qat_fw_init_admin.h"
#include <sys/sbuf.h>
#include <sys/sysctl.h>
+#include <sys/priv.h>
#define PKE_REPLAY_DBG_FILE "pke_replay_stats"
#define LINE \
@@ -21,6 +22,9 @@
u64 suc_counter = 0;
u64 unsuc_counter = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
sbuf_new_for_sysctl(&sb, NULL, 256, req);
sbuf_printf(&sb, "\n");
diff --git a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
--- a/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
+++ b/sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_ras.c
@@ -1,10 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "adf_c4xxx_ras.h"
#include "adf_accel_devices.h"
#include "adf_c4xxx_hw_data.h"
#include <adf_dev_err.h>
#include "adf_c4xxx_inline.h"
+#include <sys/priv.h>
#define ADF_RAS_STR_LEN 64
@@ -13,6 +14,9 @@
struct adf_accel_dev *accel_dev = arg1;
unsigned long counter = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (accel_dev->ras_counters)
counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_CORR]);
@@ -24,6 +28,9 @@
struct adf_accel_dev *accel_dev = arg1;
unsigned long counter = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (accel_dev->ras_counters)
counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_UNCORR]);
@@ -35,6 +42,9 @@
struct adf_accel_dev *accel_dev = arg1;
unsigned long counter = 0;
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (accel_dev->ras_counters)
counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_FATAL]);
@@ -47,6 +57,9 @@
int value = 0;
int ret = SYSCTL_IN(req, &value, sizeof(value));
+ if (priv_check(curthread, PRIV_DRIVER) != 0)
+ return EPERM;
+
if (!ret && value != 0 && accel_dev->ras_counters) {
}
diff --git a/sys/dev/qat/qat_hw/qat_c4xxx/adf_drv.c b/sys/dev/qat/qat_hw/qat_c4xxx/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_c4xxx/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_c4xxx/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -7,13 +7,12 @@
#include "adf_c4xxx_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <machine/bus_dma.h>
#include <dev/pci/pcireg.h>
-#include "adf_heartbeat_dbg.h"
-#include "adf_cnvnr_freq_counters.h"
static MALLOC_DEFINE(M_QAT_C4XXX, "qat_c4xx", "qat_c4xx");
@@ -73,6 +72,7 @@
free(accel_dev->hw_device, M_QAT_C4XXX);
accel_dev->hw_device = NULL;
}
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
adf_devmgr_rm_dev(accel_dev, NULL);
}
@@ -84,7 +84,7 @@
struct adf_accel_pci *accel_pci_dev;
struct adf_hw_device_data *hw_data;
unsigned int i, bar_nr;
- int ret, rid;
+ int ret = 0, rid;
struct adf_cfg_device *cfg_dev = NULL;
/* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
@@ -96,6 +96,7 @@
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
INIT_LIST_HEAD(&accel_dev->crypto_list);
accel_pci_dev = &accel_dev->accel_pci_dev;
accel_pci_dev->pci_dev = dev;
@@ -108,9 +109,10 @@
/* Add accel device to accel table.
* This should be called before adf_cleanup_accel is called
*/
- if (adf_devmgr_add_dev(accel_dev, NULL)) {
+ ret = adf_devmgr_add_dev(accel_dev, NULL);
+ if (ret) {
device_printf(dev, "Failed to add new accelerator device.\n");
- return ENXIO;
+ goto out_err_lock;
}
/* Allocate and configure device configuration structure */
@@ -203,6 +205,8 @@
}
pci_enable_busmaster(dev);
+ adf_dbgfs_init(accel_dev);
+
if (!accel_dev->hw_device->config_device) {
ret = EFAULT;
goto out_err;
@@ -231,6 +235,9 @@
adf_dev_shutdown(accel_dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -247,6 +254,7 @@
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
return 0;
}
diff --git a/sys/dev/qat/qat_hw/qat_c62x/adf_drv.c b/sys/dev/qat/qat_hw/qat_c62x/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_c62x/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_c62x/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -7,13 +7,12 @@
#include "adf_c62x_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <machine/bus_dma.h>
#include <dev/pci/pcireg.h>
-#include "adf_heartbeat_dbg.h"
-#include "adf_cnvnr_freq_counters.h"
static MALLOC_DEFINE(M_QAT_C62X, "qat_c62x", "qat_c62x");
@@ -73,6 +72,7 @@
free(accel_dev->hw_device, M_QAT_C62X);
accel_dev->hw_device = NULL;
}
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
adf_devmgr_rm_dev(accel_dev, NULL);
}
@@ -84,7 +84,7 @@
struct adf_accel_pci *accel_pci_dev;
struct adf_hw_device_data *hw_data;
unsigned int i, bar_nr;
- int ret, rid;
+ int ret = 0, rid;
struct adf_cfg_device *cfg_dev = NULL;
/* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
@@ -95,6 +95,7 @@
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
INIT_LIST_HEAD(&accel_dev->crypto_list);
accel_pci_dev = &accel_dev->accel_pci_dev;
accel_pci_dev->pci_dev = dev;
@@ -106,9 +107,10 @@
/* Add accel device to accel table.
* This should be called before adf_cleanup_accel is called */
- if (adf_devmgr_add_dev(accel_dev, NULL)) {
+ ret = adf_devmgr_add_dev(accel_dev, NULL);
+ if (ret) {
device_printf(dev, "Failed to add new accelerator device.\n");
- return ENXIO;
+ goto out_err_lock;
}
/* Allocate and configure device configuration structure */
@@ -205,6 +207,8 @@
}
pci_enable_busmaster(dev);
+ adf_dbgfs_init(accel_dev);
+
if (!accel_dev->hw_device->config_device) {
ret = EFAULT;
goto out_err;
@@ -233,6 +237,9 @@
adf_dev_shutdown(accel_dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -249,6 +256,7 @@
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
return 0;
}
diff --git a/sys/dev/qat/qat_hw/qat_dh895xcc/adf_drv.c b/sys/dev/qat/qat_hw/qat_dh895xcc/adf_drv.c
--- a/sys/dev/qat/qat_hw/qat_dh895xcc/adf_drv.c
+++ b/sys/dev/qat/qat_hw/qat_dh895xcc/adf_drv.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include "qat_freebsd.h"
#include "adf_cfg.h"
#include "adf_common_drv.h"
@@ -7,13 +7,12 @@
#include "adf_dh895xcc_hw_data.h"
#include "adf_fw_counters.h"
#include "adf_cfg_device.h"
+#include "adf_dbgfs.h"
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <machine/bus_dma.h>
#include <dev/pci/pcireg.h>
-#include "adf_heartbeat_dbg.h"
-#include "adf_cnvnr_freq_counters.h"
static MALLOC_DEFINE(M_QAT_DH895XCC, "qat_dh895xcc", "qat_dh895xcc");
@@ -73,6 +72,7 @@
free(accel_dev->hw_device, M_QAT_DH895XCC);
accel_dev->hw_device = NULL;
}
+ adf_dbgfs_exit(accel_dev);
adf_cfg_dev_remove(accel_dev);
adf_devmgr_rm_dev(accel_dev, NULL);
}
@@ -84,7 +84,7 @@
struct adf_accel_pci *accel_pci_dev;
struct adf_hw_device_data *hw_data;
unsigned int i, bar_nr;
- int ret, rid;
+ int ret = 0, rid;
struct adf_cfg_device *cfg_dev = NULL;
/* Set pci MaxPayLoad to 256. Implemented to avoid the issue of
@@ -95,6 +95,7 @@
accel_dev = device_get_softc(dev);
+ mutex_init(&accel_dev->lock);
INIT_LIST_HEAD(&accel_dev->crypto_list);
accel_pci_dev = &accel_dev->accel_pci_dev;
accel_pci_dev->pci_dev = dev;
@@ -104,9 +105,10 @@
/* Add accel device to accel table.
* This should be called before adf_cleanup_accel is called */
- if (adf_devmgr_add_dev(accel_dev, NULL)) {
+ ret = adf_devmgr_add_dev(accel_dev, NULL);
+ if (ret) {
device_printf(dev, "Failed to add new accelerator device.\n");
- return ENXIO;
+ goto out_err_lock;
}
/* Allocate and configure device configuration structure */
@@ -193,6 +195,8 @@
}
pci_enable_busmaster(dev);
+ adf_dbgfs_init(accel_dev);
+
if (!accel_dev->hw_device->config_device) {
ret = EFAULT;
goto out_err;
@@ -221,6 +225,9 @@
adf_dev_shutdown(accel_dev);
out_err:
adf_cleanup_accel(accel_dev);
+out_err_lock:
+ mutex_destroy(&accel_dev->lock);
+
return ret;
}
@@ -237,6 +244,8 @@
adf_dev_shutdown(accel_dev);
adf_cleanup_accel(accel_dev);
+ mutex_destroy(&accel_dev->lock);
+
return 0;
}
diff --git a/sys/modules/qat/qat/Makefile b/sys/modules/qat/qat/Makefile
--- a/sys/modules/qat/qat/Makefile
+++ b/sys/modules/qat/qat/Makefile
@@ -4,7 +4,7 @@
KMOD= qat
SRCS+= qat_ocf.c qat_ocf_mem_pool.c qat_ocf_utils.c
-SRCS+= device_if.h bus_if.h vnode_if.h pci_if.h cryptodev_if.h
+SRCS+= device_if.h bus_if.h vnode_if.h pci_if.h cryptodev_if.h opt_qat.h
CFLAGS+= ${LINUXKPI_INCLUDES}
CFLAGS+= -I${SRCTOP}/sys/dev/qat/include
@@ -17,6 +17,17 @@
CFLAGS+= -I${SRCTOP}/sys/dev/qat/qat_api/firmware/include
CFLAGS+= -I${SRCTOP}/sys/dev/qat/qat_api/common/crypto/sym/include
+.if !defined(KERNBUILDDIR)
+CFLAGS+= -include opt_qat.h
+MKDEP= -include opt_qat.h
+
+opt_qat.h:
+ :> ${.TARGET}
+.if defined(QAT_DISABLE_SAFE_DC_MODE) && ${QAT_DISABLE_SAFE_DC_MODE} == "1"
+ @echo "#define QAT_DISABLE_SAFE_DC_MODE 1" > ${.TARGET}
+.endif
+.endif
+
.include <bsd.kmod.mk>
.if ${COMPILER_TYPE} == "clang"
diff --git a/sys/modules/qat/qat_api/Makefile b/sys/modules/qat/qat_api/Makefile
--- a/sys/modules/qat/qat_api/Makefile
+++ b/sys/modules/qat/qat_api/Makefile
@@ -60,7 +60,7 @@
SRCS+= qat_utils/src/QatUtilsSpinLock.c
SRCS+= qat_utils/src/QatUtilsAtomic.c
SRCS+= qat_utils/src/QatUtilsCrypto.c
-SRCS+= bus_if.h cryptodev_if.h device_if.h pci_if.h vnode_if.h
+SRCS+= bus_if.h cryptodev_if.h device_if.h pci_if.h vnode_if.h opt_qat.h
CFLAGS+= -I${SRCTOP}/sys/dev/qat/qat_api/include
CFLAGS+= -I${SRCTOP}/sys/dev/qat/qat_api/include/lac
@@ -74,6 +74,17 @@
CFLAGS+= -I${SRCTOP}/sys/dev/qat/include/common
CFLAGS+= ${LINUXKPI_INCLUDES}
+.if !defined(KERNBUILDDIR)
+CFLAGS+= -include opt_qat.h
+MKDEP= -include opt_qat.h
+
+opt_qat.h:
+ :> ${.TARGET}
+.if defined(QAT_DISABLE_SAFE_DC_MODE) && ${QAT_DISABLE_SAFE_DC_MODE} == "1"
+ @echo "#define QAT_DISABLE_SAFE_DC_MODE 1" > ${.TARGET}
+.endif
+.endif
+
.include <bsd.kmod.mk>
CWARNFLAGS+= -Wno-cast-qual
diff --git a/sys/modules/qat/qat_common/Makefile b/sys/modules/qat/qat_common/Makefile
--- a/sys/modules/qat/qat_common/Makefile
+++ b/sys/modules/qat/qat_common/Makefile
@@ -22,11 +22,23 @@
SRCS+= adf_gen4vf_hw_csr_data.c
SRCS+= adf_freebsd_transport_debug.c adf_clock.c
SRCS+= adf_freebsd_cnvnr_ctrs_dbg.c
+SRCS+= adf_freebsd_dbgfs.c
SRCS+= adf_freebsd_pfvf_ctrs_dbg.c
-SRCS+= bus_if.h device_if.h pci_if.h vnode_if.h
+SRCS+= bus_if.h device_if.h pci_if.h vnode_if.h opt_qat.h
CFLAGS+= -I${SRCTOP}/sys/dev/qat/include
CFLAGS+= -I${SRCTOP}/sys/dev/qat/include/common
CFLAGS+= ${LINUXKPI_INCLUDES}
+.if !defined(KERNBUILDDIR)
+CFLAGS+= -include opt_qat.h
+MKDEP= -include opt_qat.h
+
+opt_qat.h:
+ :> ${.TARGET}
+.if defined(QAT_DISABLE_SAFE_DC_MODE) && ${QAT_DISABLE_SAFE_DC_MODE} == "1"
+ @echo "#define QAT_DISABLE_SAFE_DC_MODE 1" > ${.TARGET}
+.endif
+.endif
+
.include <bsd.kmod.mk>
diff --git a/sys/modules/qat/qat_hw/Makefile b/sys/modules/qat/qat_hw/Makefile
--- a/sys/modules/qat/qat_hw/Makefile
+++ b/sys/modules/qat/qat_hw/Makefile
@@ -12,7 +12,7 @@
SRCS+= qat_c4xxx/adf_c4xxx_hw_data.c qat_c4xxx/adf_drv.c qat_c4xxx/adf_c4xxx_ae_config.c qat_c4xxx/adf_c4xxx_misc_error_stats.c
SRCS+= qat_c4xxx/adf_c4xxx_pke_replay_stats.c qat_c4xxx/adf_c4xxx_ras.c qat_c4xxx/adf_c4xxx_res_part.c
SRCS+= qat_c4xxx/adf_c4xxx_reset.c
-SRCS+= device_if.h bus_if.h vnode_if.h pci_if.h cryptodev_if.h
+SRCS+= device_if.h bus_if.h vnode_if.h pci_if.h cryptodev_if.h opt_qat.h
CFLAGS+= ${LINUXKPI_INCLUDES}
CFLAGS+= -I${SRCTOP}/sys/dev/qat/include
@@ -25,4 +25,15 @@
CFLAGS+= -I${SRCTOP}/sys/dev/qat/qat_api/firmware/include
CFLAGS+= -I${SRCTOP}/sys/dev/qat/qat_api/common/crypto/sym/include
+.if !defined(KERNBUILDDIR)
+CFLAGS+= -include opt_qat.h
+MKDEP= -include opt_qat.h
+
+opt_qat.h:
+ :> ${.TARGET}
+.if defined(QAT_DISABLE_SAFE_DC_MODE) && ${QAT_DISABLE_SAFE_DC_MODE} == "1"
+ @echo "#define QAT_DISABLE_SAFE_DC_MODE 1" > ${.TARGET}
+.endif
+.endif
+
.include <bsd.kmod.mk>

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