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diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc
--- a/ObsoleteFiles.inc
+++ b/ObsoleteFiles.inc
@@ -52,6 +52,9 @@
# xargs -n1 | sort | uniq -d;
# done
+# 20230801: pmc.k7(3) removed
+OLD_FILES+=usr/share/man/man3/pmc.k7.3.gz
+
# 20230726: Removal of support for the VTOC8 partitioning scheme
OLD_FILES+=usr/include/sys/disk/vtoc.h
OLD_FILES+=usr/include/sys/vtoc.h
diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile
--- a/lib/libpmc/Makefile
+++ b/lib/libpmc/Makefile
@@ -77,7 +77,6 @@
MAN+= pmc.iaf.3
MAN+= pmc.ivybridge.3
MAN+= pmc.ivybridgexeon.3
-MAN+= pmc.k7.3
MAN+= pmc.k8.3
MAN+= pmc.sandybridge.3
MAN+= pmc.sandybridgeuc.3
diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3
--- a/lib/libpmc/pmc.haswell.3
+++ b/lib/libpmc/pmc.haswell.3
@@ -919,7 +919,6 @@
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridge 3 ,
.Xr pmc.ivybridgexeon 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.haswelluc.3 b/lib/libpmc/pmc.haswelluc.3
--- a/lib/libpmc/pmc.haswelluc.3
+++ b/lib/libpmc/pmc.haswelluc.3
@@ -203,7 +203,6 @@
.Xr pmc.corei7uc 3 ,
.Xr pmc.haswell 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.haswellxeon.3 b/lib/libpmc/pmc.haswellxeon.3
--- a/lib/libpmc/pmc.haswellxeon.3
+++ b/lib/libpmc/pmc.haswellxeon.3
@@ -933,7 +933,6 @@
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridge 3 ,
.Xr pmc.ivybridgexeon 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3
--- a/lib/libpmc/pmc.3
+++ b/lib/libpmc/pmc.3
@@ -23,7 +23,7 @@
.\"
.\" $FreeBSD$
.\"
-.Dd June 16, 2023
+.Dd June 23, 2023
.Dt PMC 3
.Os
.Sh NAME
@@ -132,9 +132,6 @@
Supported CPUs include:
.Pp
.Bl -tag -width "Li PMC_CPU_ARMV7_CORTEX_A15" -compact
-.It Li PMC_CPU_AMD_K7
-.Tn "AMD Athlon"
-CPUs.
.It Li PMC_CPU_AMD_K8
.Tn "AMD Athlon64"
CPUs.
@@ -229,10 +226,6 @@
Programmable hardware counters present in CPUs conforming to the
.Tn Intel
performance measurement architecture version 1 and later.
-.It Li PMC_CLASS_K7
-Programmable hardware counters present in
-.Tn "AMD Athlon"
-CPUs.
.It Li PMC_CLASS_K8
Programmable hardware counters present in
.Tn "AMD Athlon64"
@@ -500,7 +493,6 @@
.It Em "PMC Class" Ta Em "Manual Page"
.It Li PMC_CLASS_IAF Ta Xr pmc.iaf 3
.It Li PMC_CLASS_IAP Ta Xr pmc.atom 3 , Xr pmc.core 3 , Xr pmc.core2 3
-.It Li PMC_CLASS_K7 Ta Xr pmc.k7 3
.It Li PMC_CLASS_K8 Ta Xr pmc.k8 3
.It Li PMC_CLASS_TSC Ta Xr pmc.tsc 3
.El
@@ -553,7 +545,6 @@
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridge 3 ,
.Xr pmc.ivybridgexeon 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.atom.3 b/lib/libpmc/pmc.atom.3
--- a/lib/libpmc/pmc.atom.3
+++ b/lib/libpmc/pmc.atom.3
@@ -1172,7 +1172,6 @@
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.atomsilvermont.3 b/lib/libpmc/pmc.atomsilvermont.3
--- a/lib/libpmc/pmc.atomsilvermont.3
+++ b/lib/libpmc/pmc.atomsilvermont.3
@@ -510,7 +510,6 @@
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.cmn-600.3 b/lib/libpmc/pmc.cmn-600.3
--- a/lib/libpmc/pmc.cmn-600.3
+++ b/lib/libpmc/pmc.cmn-600.3
@@ -562,7 +562,6 @@
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.core.3 b/lib/libpmc/pmc.core.3
--- a/lib/libpmc/pmc.core.3
+++ b/lib/libpmc/pmc.core.3
@@ -787,7 +787,6 @@
.Xr pmc.atom 3 ,
.Xr pmc.core2 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.core2.3 b/lib/libpmc/pmc.core2.3
--- a/lib/libpmc/pmc.core2.3
+++ b/lib/libpmc/pmc.core2.3
@@ -1102,7 +1102,6 @@
.Xr pmc.atom 3 ,
.Xr pmc.core 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.corei7.3 b/lib/libpmc/pmc.corei7.3
--- a/lib/libpmc/pmc.corei7.3
+++ b/lib/libpmc/pmc.corei7.3
@@ -1581,7 +1581,6 @@
.Xr pmc.core 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.corei7uc.3 b/lib/libpmc/pmc.corei7uc.3
--- a/lib/libpmc/pmc.corei7uc.3
+++ b/lib/libpmc/pmc.corei7uc.3
@@ -884,7 +884,6 @@
.Xr pmc.core 3 ,
.Xr pmc.corei7 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.dmc-620.3 b/lib/libpmc/pmc.dmc-620.3
--- a/lib/libpmc/pmc.dmc-620.3
+++ b/lib/libpmc/pmc.dmc-620.3
@@ -130,7 +130,6 @@
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.iaf.3 b/lib/libpmc/pmc.iaf.3
--- a/lib/libpmc/pmc.iaf.3
+++ b/lib/libpmc/pmc.iaf.3
@@ -126,7 +126,6 @@
.Xr pmc.atom 3 ,
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3
--- a/lib/libpmc/pmc.ivybridge.3
+++ b/lib/libpmc/pmc.ivybridge.3
@@ -831,7 +831,6 @@
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridgexeon 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.ivybridgexeon.3 b/lib/libpmc/pmc.ivybridgexeon.3
--- a/lib/libpmc/pmc.ivybridgexeon.3
+++ b/lib/libpmc/pmc.ivybridgexeon.3
@@ -864,7 +864,6 @@
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridge 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.k7.3 b/lib/libpmc/pmc.k7.3
deleted file mode 100644
--- a/lib/libpmc/pmc.k7.3
+++ /dev/null
@@ -1,262 +0,0 @@
-.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\" notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\" notice, this list of conditions and the following disclaimer in the
-.\" documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.\" $FreeBSD$
-.\"
-.Dd October 4, 2008
-.Dt PMC.K7 3
-.Os
-.Sh NAME
-.Nm pmc.k7
-.Nd measurement events for
-.Tn AMD
-.Tn Athlon
-(K7 family) CPUs
-.Sh LIBRARY
-.Lb libpmc
-.Sh SYNOPSIS
-.In pmc.h
-.Sh DESCRIPTION
-AMD K7 PMCs are present in the
-.Tn "AMD Athlon"
-series of CPUs and are documented in:
-.Rs
-.%B "AMD Athlon Processor x86 Code Optimization Guide"
-.%N "Publication No. 22007"
-.%D "February 2002"
-.%Q "Advanced Micro Devices, Inc."
-.Re
-.Ss PMC Features
-AMD K7 PMCs are 48 bits wide.
-Each K7 CPU contains 4 PMCs with the following capabilities:
-.Bl -column "PMC_CAP_INTERRUPT" "Support"
-.It Em Capability Ta Em Support
-.It PMC_CAP_CASCADE Ta \&No
-.It PMC_CAP_EDGE Ta Yes
-.It PMC_CAP_INTERRUPT Ta Yes
-.It PMC_CAP_INVERT Ta Yes
-.It PMC_CAP_READ Ta Yes
-.It PMC_CAP_PRECISE Ta \&No
-.It PMC_CAP_SYSTEM Ta Yes
-.It PMC_CAP_TAGGING Ta \&No
-.It PMC_CAP_THRESHOLD Ta Yes
-.It PMC_CAP_USER Ta Yes
-.It PMC_CAP_WRITE Ta Yes
-.El
-.Ss Event Qualifiers
-Event specifiers for AMD K7 PMCs can have the following optional
-qualifiers:
-.Bl -tag -width indent
-.It Li count= Ns Ar value
-Configure the counter to increment only if the number of configured
-events measured in a cycle is greater than or equal to
-.Ar value .
-.It Li edge
-Configure the counter to only count negated-to-asserted transitions
-of the conditions expressed by the other qualifiers.
-In other words, the counter will increment only once whenever a given
-condition becomes true, irrespective of the number of clocks during
-which the condition remains true.
-.It Li inv
-Invert the sense of comparison when the
-.Dq Li count
-qualifier is present, making the counter to increment when the
-number of events per cycle is less than the value specified by
-the
-.Dq Li count
-qualifier.
-.It Li os
-Configure the PMC to count events happening at privilege level 0.
-.It Li unitmask= Ns Ar mask
-This qualifier is used to further qualify a select few events,
-.Dq Li k7-dc-refills-from-l2 ,
-.Dq Li k7-dc-refills-from-system
-and
-.Dq Li k7-dc-writebacks .
-Here
-.Ar mask
-is a string of the following characters optionally separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li m
-Count operations for lines in the
-.Dq Modified
-state.
-.It Li o
-Count operations for lines in the
-.Dq Owner
-state.
-.It Li e
-Count operations for lines in the
-.Dq Exclusive
-state.
-.It Li s
-Count operations for lines in the
-.Dq Shared
-state.
-.It Li i
-Count operations for lines in the
-.Dq Invalid
-state.
-.El
-.Pp
-If no
-.Dq Li unitmask
-qualifier is specified, the default is to count events for caches
-lines in any of the above states.
-.It Li usr
-Configure the PMC to count events occurring at privilege levels 1, 2
-or 3.
-.El
-.Pp
-If neither of the
-.Dq Li os
-or
-.Dq Li usr
-qualifiers were specified, the default is to enable both.
-.Ss AMD K7 Event Specifiers
-The event specifiers supported on AMD K7 PMCs are:
-.Bl -tag -width indent
-.It Li k7-dc-accesses
-.Pq Event 40H
-Count data cache accesses.
-.It Li k7-dc-misses
-.Pq Event 41H
-Count data cache misses.
-.It Li k7-dc-refills-from-l2 Op Li ,unitmask= Ns Ar mask
-.Pq Event 42H
-Count data cache refills from L2 cache.
-This event may be further qualified using the
-.Dq Li unitmask
-qualifier.
-.It Li k7-dc-refills-from-system Op Li ,unitmask= Ns Ar mask
-.Pq Event 43H
-Count data cache refills from system memory.
-This event may be further qualified using the
-.Dq Li unitmask
-qualifier.
-.It Li k7-dc-writebacks Op Li ,unitmask= Ns Ar mask
-.Pq Event 44H
-Count data cache writebacks.
-This event may be further qualified using the
-.Dq Li unitmask
-qualifier.
-.It Li k7-hardware-interrupts
-.Pq Event CFH
-Count the number of taken hardware interrupts.
-.It Li k7-ic-fetches
-.Pq Event 80H
-Count instruction cache fetches.
-.It Li k7-ic-misses
-.Pq Event 81H
-Count instruction cache misses.
-.It Li k7-interrupts-masked-cycles
-.Pq Event CDH
-Count the number of cycles when the processor's
-.Va IF
-flag was zero.
-.It Li k7-interrupts-masked-while-pending-cycles
-.Pq Event CEH
-Count the number of cycles interrupts were masked while pending due
-to the processor's
-.Va IF
-flag being zero.
-.It Li k7-l1-and-l2-dtlb-misses
-.Pq Event 46H
-Count L1 and L2 DTLB misses.
-.It Li k7-l1-dtlb-miss-and-l2-dtlb-hits
-.Pq Event 45H
-Count L1 DTLB misses and L2 DTLB hits.
-.It Li k7-l1-itlb-misses
-.Pq Event 84H
-Count L1 ITLB misses that are L2 ITLB hits.
-.It Li k7-l1-l2-itlb-misses
-.Pq Event 85H
-Count L1 (and L2) ITLB misses.
-.It Li k7-misaligned-references
-.Pq Event 47H
-Count misaligned data references.
-.It Li k7-retired-branches
-.Pq Event C2H
-Count all retired branches (conditional, unconditional, exceptions
-and interrupts).
-.It Li k7-retired-branches-mispredicted
-.Pq Event C3H
-Count all mispredicted retired branches.
-.It Li k7-retired-far-control-transfers
-.Pq Event C6H
-Count retired far control transfers.
-.It Li k7-retired-instructions
-.Pq Event C0H
-Count all retired instructions.
-.It Li k7-retired-ops
-.Pq Event C1H
-Count retired ops.
-.It Li k7-retired-resync-branches
-.Pq Event C7H
-Count retired resync branches (non control transfer branches).
-.It Li k7-retired-taken-branches
-.Pq Event C4H
-Count retired taken branches.
-.It Li k7-retired-taken-branches-mispredicted
-.Pq Event C5H
-Count mispredicted taken branches that were retired.
-.El
-.Ss Event Name Aliases
-The following table shows the mapping between the PMC-independent
-aliases supported by
-.Lb libpmc
-and the underlying hardware events used.
-.Bl -column "branch-mispredicts" "Description"
-.It Em Alias Ta Em Event
-.It Li branches Ta Li k7-retired-branches
-.It Li branch-mispredicts Ta Li k7-retired-branches-mispredicted
-.It Li dc-misses Ta Li k7-dc-misses
-.It Li ic-misses Ta Li k7-ic-misses
-.It Li instructions Ta Li k7-retired-instructions
-.It Li interrupts Ta Li k7-hardware-interrupts
-.It Li unhalted-cycles Ta (unsupported)
-.El
-.Sh SEE ALSO
-.Xr pmc 3 ,
-.Xr pmc.atom 3 ,
-.Xr pmc.core 3 ,
-.Xr pmc.core2 3 ,
-.Xr pmc.iaf 3 ,
-.Xr pmc.k8 3 ,
-.Xr pmc.soft 3 ,
-.Xr pmc.tsc 3 ,
-.Xr pmclog 3 ,
-.Xr hwpmc 4
-.Sh HISTORY
-The
-.Nm pmc
-library first appeared in
-.Fx 6.0 .
-.Sh AUTHORS
-The
-.Lb libpmc
-library was written by
-.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
diff --git a/lib/libpmc/pmc.k8.3 b/lib/libpmc/pmc.k8.3
--- a/lib/libpmc/pmc.k8.3
+++ b/lib/libpmc/pmc.k8.3
@@ -778,7 +778,6 @@
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
.Xr pmclog 3 ,
diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3
--- a/lib/libpmc/pmc.sandybridge.3
+++ b/lib/libpmc/pmc.sandybridge.3
@@ -911,7 +911,6 @@
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridge 3 ,
.Xr pmc.ivybridgexeon 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridgeuc 3 ,
.Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.sandybridgeuc.3 b/lib/libpmc/pmc.sandybridgeuc.3
--- a/lib/libpmc/pmc.sandybridgeuc.3
+++ b/lib/libpmc/pmc.sandybridgeuc.3
@@ -202,7 +202,6 @@
.Xr pmc.corei7 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.sandybridgexeon.3 b/lib/libpmc/pmc.sandybridgexeon.3
--- a/lib/libpmc/pmc.sandybridgexeon.3
+++ b/lib/libpmc/pmc.sandybridgexeon.3
@@ -988,7 +988,6 @@
.Xr pmc.iaf 3 ,
.Xr pmc.ivybridge 3 ,
.Xr pmc.ivybridgexeon 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
diff --git a/lib/libpmc/pmc.soft.3 b/lib/libpmc/pmc.soft.3
--- a/lib/libpmc/pmc.soft.3
+++ b/lib/libpmc/pmc.soft.3
@@ -91,7 +91,6 @@
.Xr pmc.corei7 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.tsc 3 ,
.Xr pmc.ucf 3 ,
diff --git a/lib/libpmc/pmc.tsc.3 b/lib/libpmc/pmc.tsc.3
--- a/lib/libpmc/pmc.tsc.3
+++ b/lib/libpmc/pmc.tsc.3
@@ -63,7 +63,6 @@
.Xr pmc.core 3 ,
.Xr pmc.core2 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmclog 3 ,
diff --git a/lib/libpmc/pmc.ucf.3 b/lib/libpmc/pmc.ucf.3
--- a/lib/libpmc/pmc.ucf.3
+++ b/lib/libpmc/pmc.ucf.3
@@ -89,7 +89,6 @@
.Xr pmc.corei7 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.westmere.3 b/lib/libpmc/pmc.westmere.3
--- a/lib/libpmc/pmc.westmere.3
+++ b/lib/libpmc/pmc.westmere.3
@@ -1374,7 +1374,6 @@
.Xr pmc.corei7 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/lib/libpmc/pmc.westmereuc.3 b/lib/libpmc/pmc.westmereuc.3
--- a/lib/libpmc/pmc.westmereuc.3
+++ b/lib/libpmc/pmc.westmereuc.3
@@ -1078,7 +1078,6 @@
.Xr pmc.corei7 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h
--- a/sys/dev/hwpmc/pmc_events.h
+++ b/sys/dev/hwpmc/pmc_events.h
@@ -64,39 +64,6 @@
#define PMC_EV_SOFT_FIRST 0x20000
#define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1)
-/*
- * AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code
- * Optimization Guide" [Doc#22007K, Feb 2002]
- */
-
-#define __PMC_EV_K7() \
-__PMC_EV(K7, DC_ACCESSES) \
-__PMC_EV(K7, DC_MISSES) \
-__PMC_EV(K7, DC_REFILLS_FROM_L2) \
-__PMC_EV(K7, DC_REFILLS_FROM_SYSTEM) \
-__PMC_EV(K7, DC_WRITEBACKS) \
-__PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS) \
-__PMC_EV(K7, L1_AND_L2_DTLB_MISSES) \
-__PMC_EV(K7, MISALIGNED_REFERENCES) \
-__PMC_EV(K7, IC_FETCHES) \
-__PMC_EV(K7, IC_MISSES) \
-__PMC_EV(K7, L1_ITLB_MISSES) \
-__PMC_EV(K7, L1_L2_ITLB_MISSES) \
-__PMC_EV(K7, RETIRED_INSTRUCTIONS) \
-__PMC_EV(K7, RETIRED_OPS) \
-__PMC_EV(K7, RETIRED_BRANCHES) \
-__PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED) \
-__PMC_EV(K7, RETIRED_TAKEN_BRANCHES) \
-__PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED) \
-__PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS) \
-__PMC_EV(K7, RETIRED_RESYNC_BRANCHES) \
-__PMC_EV(K7, INTERRUPTS_MASKED_CYCLES) \
-__PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \
-__PMC_EV(K7, HARDWARE_INTERRUPTS)
-
-#define PMC_EV_K7_FIRST PMC_EV_K7_DC_ACCESSES
-#define PMC_EV_K7_LAST PMC_EV_K7_HARDWARE_INTERRUPTS
-
/* AMD K8 PMCs */
#define __PMC_EV_K8() \
@@ -2433,7 +2400,7 @@
* START #EVENTS DESCRIPTION
* 0 0x1000 Reserved
* 0x1000 0x0001 TSC
- * 0x2000 0x0080 AMD K7 events
+ * 0x2000 0x0080 free (was AMD K7 events)
* 0x2080 0x0100 AMD K8 events
* 0x10000 0x0080 INTEL architectural fixed-function events
* 0x10080 0x0F80 free (was INTEL architectural programmable events)
@@ -2459,8 +2426,6 @@
#define __PMC_EVENTS() \
__PMC_EV_BLOCK(TSC, 0x01000) \
__PMC_EV_TSC() \
- __PMC_EV_BLOCK(K7, 0x02000) \
- __PMC_EV_K7() \
__PMC_EV_BLOCK(K8, 0x02080) \
__PMC_EV_K8() \
__PMC_EV_BLOCK(IAF, 0x10000) \
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -83,7 +83,6 @@
* Please keep the pmc(3) manual page in sync with this list.
*/
#define __PMC_CPUS() \
- __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
__PMC_CPU(AMD_K8, 0x01, "AMD K8") \
__PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
__PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
@@ -132,7 +131,7 @@
__PMC_CPUS()
};
-#define PMC_CPU_FIRST PMC_CPU_AMD_K7
+#define PMC_CPU_FIRST PMC_CPU_AMD_K8
#define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76
/*
@@ -140,7 +139,6 @@
*/
#define __PMC_CLASSES() \
__PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
- __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \
__PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
__PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
__PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
diff --git a/tools/build/mk/OptionalObsoleteFiles.inc b/tools/build/mk/OptionalObsoleteFiles.inc
--- a/tools/build/mk/OptionalObsoleteFiles.inc
+++ b/tools/build/mk/OptionalObsoleteFiles.inc
@@ -6807,7 +6807,6 @@
OLD_FILES+=usr/share/man/man3/pmc.iaf.3.gz
OLD_FILES+=usr/share/man/man3/pmc.ivybridge.3.gz
OLD_FILES+=usr/share/man/man3/pmc.ivybridgexeon.3.gz
-OLD_FILES+=usr/share/man/man3/pmc.k7.3.gz
OLD_FILES+=usr/share/man/man3/pmc.k8.3.gz
OLD_FILES+=usr/share/man/man3/pmc.sandybridge.3.gz
OLD_FILES+=usr/share/man/man3/pmc.sandybridgeuc.3.gz

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