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diff --git a/sys/dev/nvme/nvme_ctrlr.c b/sys/dev/nvme/nvme_ctrlr.c
--- a/sys/dev/nvme/nvme_ctrlr.c
+++ b/sys/dev/nvme/nvme_ctrlr.c
@@ -173,6 +173,10 @@
num_entries = min(num_entries, mqes + 1);
num_entries = min(num_entries, max_entries);
+ /* SHARED_CID_SPACE: IO CIDs must fit within the shared CID table. */
+ if (ctrlr->quirks & QUIRK_APPLE_SHARED_CID_SPACE)
+ num_entries = min(num_entries, NVME_ADMIN_ENTRIES);
+
num_trackers = NVME_IO_TRACKERS;
TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers);
@@ -185,6 +189,10 @@
*/
num_trackers = min(num_trackers, (num_entries-1));
+ if (ctrlr->quirks & QUIRK_APPLE_SHARED_CID_SPACE)
+ num_trackers = min(num_trackers,
+ NVME_ADMIN_ENTRIES - ctrlr->adminq.num_trackers);
+
/*
* Our best estimate for the maximum number of I/Os that we should
* normally have in flight at one time. This should be viewed as a hint,
@@ -749,6 +757,11 @@
struct nvme_async_event_request *aer;
uint32_t i;
+ if (ctrlr->quirks & QUIRK_APPLE_NO_ASYNC_EVENT) {
+ ctrlr->num_aers = 0;
+ return;
+ }
+
ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE |
NVME_CRIT_WARN_ST_DEVICE_RELIABILITY |
NVME_CRIT_WARN_ST_READ_ONLY |
@@ -1112,12 +1125,16 @@
nvme_qpair_reset(&ctrlr->adminq);
nvme_admin_qpair_enable(&ctrlr->adminq);
- if (nvme_ctrlr_identify(ctrlr) == 0 &&
- nvme_ctrlr_set_num_qpairs(ctrlr) == 0 &&
+ if (nvme_ctrlr_identify(ctrlr) != 0) {
+ nvme_ctrlr_fail(ctrlr, false);
+ goto out;
+ }
+ if (nvme_ctrlr_set_num_qpairs(ctrlr) == 0 &&
nvme_ctrlr_construct_io_qpairs(ctrlr) == 0)
nvme_ctrlr_start(ctrlr, false);
else
nvme_ctrlr_fail(ctrlr, false);
+out:
nvme_sysctl_initialize_ctrlr(ctrlr);
config_intrhook_disestablish(&ctrlr->config_hook);
diff --git a/sys/dev/nvme/nvme_pci.c b/sys/dev/nvme/nvme_pci.c
--- a/sys/dev/nvme/nvme_pci.c
+++ b/sys/dev/nvme/nvme_pci.c
@@ -93,6 +93,9 @@
{ 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
{ 0x07f015ad, 0, 0, "VMware NVMe Controller" },
{ 0x2003106b, 0, 0, "Apple S3X NVMe Controller" },
+ { 0x2005106b, 0, 0, "Apple ANS2 NVMe Controller (T2)",
+ QUIRK_APPLE_IDENTIFY_CNS_BROKEN | QUIRK_APPLE_SHARED_CID_SPACE |
+ QUIRK_APPLE_NO_ASYNC_EVENT | QUIRK_APPLE_SINGLE_VECTOR },
{ 0x00000000, 0, 0, NULL }
};
@@ -131,6 +134,9 @@
if (ep->devid)
ctrlr->quirks = ep->quirks;
+ if (ctrlr->quirks & QUIRK_APPLE_IDENTIFY_CNS_BROKEN)
+ ctrlr->max_identify_cns = 1;
+
if (ep->desc) {
device_set_desc(device, ep->desc);
return (BUS_PROBE_DEFAULT);
@@ -323,6 +329,15 @@
if (force_intx)
return (nvme_ctrlr_setup_shared(ctrlr, 0));
+ if (ctrlr->quirks & QUIRK_APPLE_SINGLE_VECTOR) {
+ int n = 1;
+ if (pci_alloc_msi(dev, &n) == 0) {
+ ctrlr->msi_count = n;
+ return (nvme_ctrlr_setup_shared(ctrlr, 1));
+ }
+ return (nvme_ctrlr_setup_shared(ctrlr, 0));
+ }
+
if (pci_msix_count(dev) == 0)
goto msi;
diff --git a/sys/dev/nvme/nvme_private.h b/sys/dev/nvme/nvme_private.h
--- a/sys/dev/nvme/nvme_private.h
+++ b/sys/dev/nvme/nvme_private.h
@@ -165,6 +165,8 @@
uint32_t num_entries;
uint32_t num_trackers;
+ uint32_t sqe_size; /* SQE size multiplier: 1 = 64 bytes, 2 = 128 bytes */
+ uint16_t cid_base; /* CID offset for SHARED_TAGS IO queues */
uint32_t sq_tdbl_off;
uint32_t cq_hdbl_off;
@@ -220,10 +222,15 @@
int domain;
uint32_t ready_timeout_in_ms;
uint32_t quirks;
+ uint8_t max_identify_cns; /* max CNS value for IDENTIFY (0 = no limit) */
#define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */
#define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */
#define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */
#define QUIRK_AHCI 8 /* Attached via AHCI redirect */
+#define QUIRK_APPLE_IDENTIFY_CNS_BROKEN 0x10 /* Reject IDENTIFY with CNS >= max_identify_cns */
+#define QUIRK_APPLE_SHARED_CID_SPACE 0x20 /* Admin/IO share a single CID table */
+#define QUIRK_APPLE_NO_ASYNC_EVENT 0x40 /* Skip NVMe async event requests */
+#define QUIRK_APPLE_SINGLE_VECTOR 0x80 /* Single MSI vector, one IO queue */
int resource_id;
struct resource *resource;
@@ -322,6 +329,8 @@
counter_u64_t alignment_splits;
};
+#define NVME_SQE(qpair, idx) (&(qpair)->cmd[(idx) * (qpair)->sqe_size])
+
#define nvme_mmio_offsetof(reg) \
offsetof(struct nvme_registers, reg)
diff --git a/sys/dev/nvme/nvme_qpair.c b/sys/dev/nvme/nvme_qpair.c
--- a/sys/dev/nvme/nvme_qpair.c
+++ b/sys/dev/nvme/nvme_qpair.c
@@ -231,7 +231,7 @@
nvme_qpair_print_completion(qpair, cpl);
}
- qpair->act_tr[cpl->cid] = NULL;
+ qpair->act_tr[cpl->cid - qpair->cid_base] = NULL;
KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n"));
@@ -305,7 +305,7 @@
memset(&cpl, 0, sizeof(cpl));
cpl.sqid = qpair->id;
- cpl.cid = tr->cid;
+ cpl.cid = qpair->cid_base + tr->cid;
cpl.status = nvme_qpair_make_status(sct, sc, dnr);
nvme_qpair_complete_tracker(tr, &cpl, print_on_error);
}
@@ -433,8 +433,9 @@
NVME_STATUS_GET_P(status) == NVME_STATUS_GET_P(cpl.status),
("Phase unexpectedly inconsistent"));
- if (cpl.cid < qpair->num_trackers)
- tr = qpair->act_tr[cpl.cid];
+ if (cpl.cid >= qpair->cid_base &&
+ cpl.cid < qpair->cid_base + qpair->num_trackers)
+ tr = qpair->act_tr[cpl.cid - qpair->cid_base];
else
tr = NULL;
@@ -530,6 +531,18 @@
qpair->num_trackers = num_trackers;
qpair->ctrlr = ctrlr;
+ /* sqes[7:4]: max SQE size exponent; admin always 64 bytes per spec. */
+ if (qpair->id != 0) {
+ uint8_t sqes_max = (ctrlr->cdata.sqes >> 4) & 0xf;
+ qpair->sqe_size = (sqes_max > 6) ? (1 << (sqes_max - 6)) : 1;
+ } else {
+ qpair->sqe_size = 1;
+ }
+ if ((ctrlr->quirks & QUIRK_APPLE_SHARED_CID_SPACE) && qpair->id != 0)
+ qpair->cid_base = ctrlr->adminq.num_trackers;
+ else
+ qpair->cid_base = 0;
+
mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF);
mtx_init(&qpair->recovery, "nvme qpair recovery", NULL, MTX_DEF);
@@ -553,7 +566,7 @@
* Each component must be page aligned, and individual PRP lists
* cannot cross a page boundary.
*/
- cmdsz = qpair->num_entries * sizeof(struct nvme_command);
+ cmdsz = qpair->num_entries * qpair->sqe_size * sizeof(struct nvme_command);
cmdsz = roundup2(cmdsz, ctrlr->page_size);
cplsz = qpair->num_entries * sizeof(struct nvme_completion);
cplsz = roundup2(cplsz, ctrlr->page_size);
@@ -987,7 +1000,8 @@
* queue which will reset the card if it
* times out.
*/
- nvme_ctrlr_cmd_abort(ctrlr, tr->cid, qpair->id,
+ nvme_ctrlr_cmd_abort(ctrlr,
+ qpair->cid_base + tr->cid, qpair->id,
nvme_abort_complete, tr);
} else {
/*
@@ -1040,7 +1054,7 @@
mtx_assert(&qpair->lock, MA_OWNED);
req = tr->req;
- req->cmd.cid = tr->cid;
+ req->cmd.cid = qpair->cid_base + tr->cid;
qpair->act_tr[tr->cid] = tr;
ctrlr = qpair->ctrlr;
@@ -1061,7 +1075,7 @@
tr->deadline = SBT_MAX;
/* Copy the command from the tracker to the submission queue. */
- memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd));
+ memcpy(NVME_SQE(qpair, qpair->sq_tail), &req->cmd, sizeof(req->cmd));
if (++qpair->sq_tail == qpair->num_entries)
qpair->sq_tail = 0;
@@ -1235,7 +1249,7 @@
qpair->phase = 1;
memset(qpair->cmd, 0,
- qpair->num_entries * sizeof(struct nvme_command));
+ qpair->num_entries * qpair->sqe_size * sizeof(struct nvme_command));
memset(qpair->cpl, 0,
qpair->num_entries * sizeof(struct nvme_completion));
}
diff --git a/sys/dev/nvme/nvme_sim.c b/sys/dev/nvme/nvme_sim.c
--- a/sys/dev/nvme/nvme_sim.c
+++ b/sys/dev/nvme/nvme_sim.c
@@ -96,6 +96,15 @@
struct nvme_controller *ctrlr;
ctrlr = sim2ctrlr(sim);
+
+ if (ctrlr->max_identify_cns != 0 &&
+ nvmeio->cmd.opc == NVME_OPC_IDENTIFY &&
+ (le32toh(nvmeio->cmd.cdw10) & 0xff) > ctrlr->max_identify_cns) {
+ nvmeio->ccb_h.status = CAM_REQ_INVALID;
+ xpt_done(ccb);
+ return;
+ }
+
payload = nvmeio->data_ptr;
size = nvmeio->dxfer_len;
/* SG LIST ??? */
diff --git a/sys/dev/nvme/nvme_sysctl.c b/sys/dev/nvme/nvme_sysctl.c
--- a/sys/dev/nvme/nvme_sysctl.c
+++ b/sys/dev/nvme/nvme_sysctl.c
@@ -69,7 +69,7 @@
printf("Submission queue:\n");
for (i = 0; i < qpair->num_entries; i++) {
- cmd = &qpair->cmd[i];
+ cmd = NVME_SQE(qpair, i);
printf("%05d: ", i);
nvme_qpair_print_command(qpair, cmd);
}

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