D56923.diff
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	diff --git a/sys/riscv/include/cpu.h b/sys/riscv/include/cpu.h
	--- a/sys/riscv/include/cpu.h
	+++ b/sys/riscv/include/cpu.h
	@@ -55,6 +55,7 @@
	#define MVENDORID_UNIMPL 0x0
	#define MVENDORID_SIFIVE 0x489
	#define MVENDORID_THEAD 0x5b7
	+#define MVENDORID_SPACEMIT 0x710

	/*
	* Micro-architecture ID register, marchid.
	@@ -82,6 +83,9 @@
	#define MARCHID_SIFIVE_U7 MARCHID_COMMERCIAL(7)
	#define MARCHID_SIFIVE_P5 MARCHID_COMMERCIAL(8)

	+/* SpacemiT marchid values */
	+#define MARCHID_SPACEMIT_K1 MARCHID_COMMERCIAL(0x58000001)
	+
	/*
	* MMU virtual-addressing modes. Support for each level implies the previous,
	* so Sv48-enabled systems MUST support Sv39, etc.
	diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
	--- a/sys/riscv/riscv/identcpu.c
	+++ b/sys/riscv/riscv/identcpu.c
	@@ -130,6 +130,11 @@
	MARCHID_END
	};

	+static const struct marchid_entry spacemit_marchids[] = {
	+ { MARCHID_SPACEMIT_K1, "SpacemiT(R) X60" },
	+ MARCHID_END
	+};
	+
	/*
	* Known CPU vendor/manufacturer table.
	*/
	@@ -141,6 +146,7 @@
	{ MVENDORID_UNIMPL, "Unspecified", NULL },
	{ MVENDORID_SIFIVE, "SiFive", sifive_marchids },
	{ MVENDORID_THEAD, "T-Head", NULL },
	+ { MVENDORID_SPACEMIT, "SpacemiT", spacemit_marchids },
	};

	/*