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diff --git a/cad/silice/Makefile b/cad/silice/Makefile
--- a/cad/silice/Makefile
+++ b/cad/silice/Makefile
@@ -1,7 +1,6 @@
PORTNAME= silice
-DISTVERSION= g20221229
-PORTREVISION= 2
-CATEGORIES= cad
+DISTVERSION= g20260322
+CATEGORIES= cad java
MAINTAINER= yuri@FreeBSD.org
COMMENT= Language that simplifies prototyping and writing algorithms for FPGAs
@@ -15,15 +14,15 @@
USES= cmake:noninja java python shebangfix
-JAVA_VERSION= 17
-
USE_GITHUB= yes
GH_ACCOUNT= sylefeb
GH_PROJECT= Silice
-GH_TAGNAME= 6a2beda
-GH_TUPLE= sylefeb:LibSL-small:b1942d5:LibSL_small/src/libs/LibSL-small \
- sylefeb:tinygpus:e6429ac:tinygpus/projects/tinygpus \
- ultraembedded:fat_io_lib:0ef5c2b:fat_io_lib/learn-silice/classroom/soc_wave_player/firmware/fat_io_lib
+GH_TAGNAME= 73bebc45
+GH_TUPLE= ultraembedded:fat_io_lib:0ef5c2bb:fat_io_lib/learn-silice/classroom/soc_wave_player/firmware/fat_io_lib \
+ sylefeb:tinygpus:498be1b8:tinygpus/projects/tinygpus \
+ sylefeb:LibSL-small:b1942d5:libslsmall/projects/tinygpus/demos/q5k/qrepack/LibSL-small \
+ pybind:pybind11:2dd52544:pybind11/python/pybind11 \
+ sylefeb:LibSL-small:b1942d59:libslsmall/src/libs/LibSL-small
SHEBANG_GLOB= *.sh *.py
diff --git a/cad/silice/distinfo b/cad/silice/distinfo
--- a/cad/silice/distinfo
+++ b/cad/silice/distinfo
@@ -1,9 +1,11 @@
-TIMESTAMP = 1673143292
-SHA256 (sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz) = 5577d91ccac7e26204a034d262faa6107bbf06fdefe7107b3a5670364384f59c
-SIZE (sylefeb-Silice-g20221229-6a2beda_GH0.tar.gz) = 42949179
-SHA256 (sylefeb-LibSL-small-b1942d5_GH0.tar.gz) = dbea9ba30c4e40e3e9e6da840e90eb9e0a91b0355dc3ae0e72602d70d718d8fd
-SIZE (sylefeb-LibSL-small-b1942d5_GH0.tar.gz) = 72760
-SHA256 (sylefeb-tinygpus-e6429ac_GH0.tar.gz) = 5e1cdfae1b81402acbeb118f350537599fd74cb8e2bc486ea6cb753ffe8f0d05
-SIZE (sylefeb-tinygpus-e6429ac_GH0.tar.gz) = 1435993
-SHA256 (ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz) = a88b5a3b0707931e7b2689d8f886b7dac53c9c4262aa9b3938d91a065c114079
-SIZE (ultraembedded-fat_io_lib-0ef5c2b_GH0.tar.gz) = 52464
+TIMESTAMP = 1774197181
+SHA256 (sylefeb-Silice-g20260322-73bebc45_GH0.tar.gz) = 0722318ac1f4024d9cfb84e0360ac4a603e605833ce2ff4bd7a462c943f1a5db
+SIZE (sylefeb-Silice-g20260322-73bebc45_GH0.tar.gz) = 36233853
+SHA256 (ultraembedded-fat_io_lib-0ef5c2bb_GH0.tar.gz) = 06dbb0ce01f9db7244e398e39dece539ae790f3ab219a8154de16a648cf6f58e
+SIZE (ultraembedded-fat_io_lib-0ef5c2bb_GH0.tar.gz) = 52463
+SHA256 (sylefeb-tinygpus-498be1b8_GH0.tar.gz) = 7781639bde0e6df3e50dea0ae637ae2c3a83134921d3a67ed5f395ef316e5598
+SIZE (sylefeb-tinygpus-498be1b8_GH0.tar.gz) = 1436158
+SHA256 (sylefeb-LibSL-small-b1942d59_GH0.tar.gz) = 68b7ae5b4a83018bbb7960d334ebccd07eed4ad6a8f0bc97842d8b1066b73262
+SIZE (sylefeb-LibSL-small-b1942d59_GH0.tar.gz) = 72748
+SHA256 (pybind-pybind11-2dd52544_GH0.tar.gz) = 5bed60133551e749c83c0da6d10993dd3f698bee18c5bb9273e2fff718b27fb4
+SIZE (pybind-pybind11-2dd52544_GH0.tar.gz) = 701049
diff --git a/cad/silice/pkg-descr b/cad/silice/pkg-descr
--- a/cad/silice/pkg-descr
+++ b/cad/silice/pkg-descr
@@ -1,3 +1,23 @@
-Yosys is a framework for Verilog RTL synthesis. It currently has
-extensive Verilog-2005 support and provides a basic set of synthesis
-algorithms for various application domains.
+Silice is an easy-to-learn, powerful hardware description language, that allows
+both to prototype ideas quickly and then refine designs to be compact and
+efficient.
+
+Silice achieves this by offering a few, carefully designed high level design
+primitives atop a low level description language. In particular, Silice allows
+to write and combine algorithms, pipelines and per-cycle logic in a coherent,
+unified way. It features a powerful instantiation-time pre-processor, making it
+easy to describe parametric designs.
+
+Silice offers a ready-to-go design environment, supporting many FPGA boards,
+both open-source and proprietary. It natively supports simulation and formal
+verification.
+
+Silice syntax is simple, explicit and easy to read, and should feel familiar to
+C programmers and Verilog designers alike. Silice comes with a ton of examples.
+
+The build system already supports many popular boards such as the IceBreaker,
+de10-nano, ULX3S, Fomu and IceStick. Silice works great with the open-source
+FPGA toolchain (yosys/nextpnr/icestorm), see our Ice40 and ECP5 examples.
+
+You do not need an FPGA to start with Silice: designs and their outputs
+(e.g. VGA signals) can be simulated and visualized.
diff --git a/cad/silice/pkg-plist b/cad/silice/pkg-plist
--- a/cad/silice/pkg-plist
+++ b/cad/silice/pkg-plist
@@ -1,10 +1,17 @@
bin/silice
bin/silice-make.py
%%DATADIR%%/frameworks/boards/README.md
+%%DATADIR%%/frameworks/boards/TROUBLESHOOTING.md
%%DATADIR%%/frameworks/boards/bare/bare.sh
%%DATADIR%%/frameworks/boards/bare/bare.v
%%DATADIR%%/frameworks/boards/bare/board.json
%%DATADIR%%/frameworks/boards/boards.json
+%%DATADIR%%/frameworks/boards/brot/board.json
+%%DATADIR%%/frameworks/boards/brot/brot.pcf
+%%DATADIR%%/frameworks/boards/brot/brot.v
+%%DATADIR%%/frameworks/boards/colorlight/board.json
+%%DATADIR%%/frameworks/boards/colorlight/colorlight.v
+%%DATADIR%%/frameworks/boards/colorlight/colorlight_i9_v7.2.lpf
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/board.json
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.pdc
%%DATADIR%%/frameworks/boards/crosslink_nx_evn/crosslink_nx_evn.sh
@@ -13,6 +20,9 @@
%%DATADIR%%/frameworks/boards/de10nano/build.sdc
%%DATADIR%%/frameworks/boards/de10nano/de10nano.v
%%DATADIR%%/frameworks/boards/de10nano/pins.tcl
+%%DATADIR%%/frameworks/boards/de2/board.json
+%%DATADIR%%/frameworks/boards/de2/de2.v
+%%DATADIR%%/frameworks/boards/de2/pins.tcl
%%DATADIR%%/frameworks/boards/ecpix5/board.json
%%DATADIR%%/frameworks/boards/ecpix5/ecpix5.lpf
%%DATADIR%%/frameworks/boards/ecpix5/ecpix5.v
@@ -35,8 +45,13 @@
%%DATADIR%%/frameworks/boards/icebreaker/icebreaker.pcf
%%DATADIR%%/frameworks/boards/icebreaker/icebreaker.sh
%%DATADIR%%/frameworks/boards/icebreaker/icebreaker.v
+%%DATADIR%%/frameworks/boards/icepi_zero/board.json
+%%DATADIR%%/frameworks/boards/icepi_zero/icepi-zero.lpf
+%%DATADIR%%/frameworks/boards/icepi_zero/icepi-zero.sh
+%%DATADIR%%/frameworks/boards/icepi_zero/icepi_zero.v
%%DATADIR%%/frameworks/boards/icestick/board.json
%%DATADIR%%/frameworks/boards/icestick/icestick.pcf
+%%DATADIR%%/frameworks/boards/icestick/icestick.py
%%DATADIR%%/frameworks/boards/icestick/icestick.sh
%%DATADIR%%/frameworks/boards/icestick/icestick.v
%%DATADIR%%/frameworks/boards/littlebee/board.json
@@ -53,6 +68,10 @@
%%DATADIR%%/frameworks/boards/mojov3/board.json
%%DATADIR%%/frameworks/boards/mojov3/mojov3.ucf
%%DATADIR%%/frameworks/boards/mojov3/mojov3.v
+%%DATADIR%%/frameworks/boards/musbx/board.json
+%%DATADIR%%/frameworks/boards/musbx/musbx.pcf
+%%DATADIR%%/frameworks/boards/musbx/musbx.v
+%%DATADIR%%/frameworks/boards/musbx/musbx_v3.v
%%DATADIR%%/frameworks/boards/orangecrab/board.json
%%DATADIR%%/frameworks/boards/orangecrab/orangecrab.sh
%%DATADIR%%/frameworks/boards/orangecrab/orangecrab.v
@@ -60,13 +79,31 @@
%%DATADIR%%/frameworks/boards/riegel/board.json
%%DATADIR%%/frameworks/boards/riegel/riegel.pcf
%%DATADIR%%/frameworks/boards/riegel/riegel.v
+%%DATADIR%%/frameworks/boards/tang_nano_20k/board.json
+%%DATADIR%%/frameworks/boards/tang_nano_20k/tang_nano_20k.cst
+%%DATADIR%%/frameworks/boards/tang_nano_20k/tang_nano_20k.sh
+%%DATADIR%%/frameworks/boards/tang_nano_20k/tang_nano_20k.v
%%DATADIR%%/frameworks/boards/techgraph/board.json
%%DATADIR%%/frameworks/boards/techgraph/techgraph.sh
%%DATADIR%%/frameworks/boards/techgraph/techgraph.v
+%%DATADIR%%/frameworks/boards/tinytapeout/board.json
+%%DATADIR%%/frameworks/boards/tinytapeout/tinytapeout.sh
+%%DATADIR%%/frameworks/boards/tinytapeout/tinytapeout.v
+%%DATADIR%%/frameworks/boards/tinytapeout/tt_ecpix5.v
+%%DATADIR%%/frameworks/boards/tinytapeout/tt_icebreaker.sh
+%%DATADIR%%/frameworks/boards/tinytapeout/tt_icebreaker.v
+%%DATADIR%%/frameworks/boards/tinytapeout/tt_icestick.sh
+%%DATADIR%%/frameworks/boards/tinytapeout/tt_icestick.v
+%%DATADIR%%/frameworks/boards/tinytapeout/tt_ulx3s.v
%%DATADIR%%/frameworks/boards/ulx3s/board.json
%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.lpf
+%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.py
%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.sh
%%DATADIR%%/frameworks/boards/ulx3s/ulx3s.v
+%%DATADIR%%/frameworks/boards/ulx4m_ls/board.json
+%%DATADIR%%/frameworks/boards/ulx4m_ls/ulx4m_ls.lpf
+%%DATADIR%%/frameworks/boards/ulx4m_ls/ulx4m_ls.sh
+%%DATADIR%%/frameworks/boards/ulx4m_ls/ulx4m_ls.v
%%DATADIR%%/frameworks/boards/verilator/board.json
%%DATADIR%%/frameworks/boards/verilator/verilator.sh
%%DATADIR%%/frameworks/boards/verilator/verilator.v
@@ -87,8 +124,13 @@
%%DATADIR%%/frameworks/templates/dualport_bram_generic.v.in
%%DATADIR%%/frameworks/templates/dualport_bram_wmask_byte.v.in
%%DATADIR%%/frameworks/templates/simple_dualport_bram_generic.v.in
+%%DATADIR%%/frameworks/templates/simple_dualport_bram_generic_rw.v.in
%%DATADIR%%/frameworks/templates/simple_dualport_bram_wmask_byte.v.in
%%DATADIR%%/frameworks/templates/simple_dualport_bram_wmask_half_bytes.v.in
+%%DATADIR%%/frameworks/verilator/PWMAudio.cpp
+%%DATADIR%%/frameworks/verilator/PWMAudio.h
+%%DATADIR%%/frameworks/verilator/ParallelScreen.cpp
+%%DATADIR%%/frameworks/verilator/ParallelScreen.h
%%DATADIR%%/frameworks/verilator/README.md
%%DATADIR%%/frameworks/verilator/SPIScreen.cpp
%%DATADIR%%/frameworks/verilator/SPIScreen.h
@@ -96,13 +138,8 @@
%%DATADIR%%/frameworks/verilator/VgaChip.h
%%DATADIR%%/frameworks/verilator/display.cpp
%%DATADIR%%/frameworks/verilator/display.h
-%%DATADIR%%/frameworks/verilator/flyover_simul.gif
%%DATADIR%%/frameworks/verilator/sdr_sdram.cpp
%%DATADIR%%/frameworks/verilator/sdr_sdram.h
-%%DATADIR%%/frameworks/verilator/verilator_bare.cpp
+%%DATADIR%%/frameworks/verilator/verilator_callbacks.h
%%DATADIR%%/frameworks/verilator/verilator_data.cpp
-%%DATADIR%%/frameworks/verilator/verilator_data.h
-%%DATADIR%%/frameworks/verilator/verilator_sdram.cpp
-%%DATADIR%%/frameworks/verilator/verilator_spiscreen.cpp
-%%DATADIR%%/frameworks/verilator/verilator_vga.cpp
-%%DATADIR%%/frameworks/verilator/verilator_vga_sdram.cpp
+%%DATADIR%%/frameworks/verilator/verilator_main.cpp

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