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Index: head/sys/dev/uart/uart_dev_pl011.c
===================================================================
--- head/sys/dev/uart/uart_dev_pl011.c
+++ head/sys/dev/uart/uart_dev_pl011.c
@@ -61,6 +61,7 @@
#define DR_OE (1 << 11) /* Overrun error */
#define UART_FR 0x06 /* Flag register */
+#define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */
#define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */
#define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
#define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
@@ -171,9 +172,9 @@
line |= LCR_H_PEN;
else
line &= ~LCR_H_PEN;
+ line |= LCR_H_FEN;
/* Configure the rest */
- line &= ~LCR_H_FEN;
ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
if (bas->rclk != 0 && baudrate != 0) {
@@ -219,7 +220,7 @@
uart_pl011_rxready(struct uart_bas *bas)
{
- return (__uart_getreg(bas, UART_FR) & FR_RXFF);
+ return !(__uart_getreg(bas, UART_FR) & FR_RXFE);
}
static int
@@ -417,8 +418,8 @@
device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
- sc->sc_rxfifosz = 1;
- sc->sc_txfifosz = 1;
+ sc->sc_rxfifosz = 16;
+ sc->sc_txfifosz = 16;
return (0);
}
@@ -440,7 +441,6 @@
break;
}
- __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM));
xc = __uart_getreg(bas, UART_DR);
rx = xc & 0xff;
@@ -481,20 +481,12 @@
uart_barrier(bas);
}
- /* If not empty wait until it is */
- if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) {
- sc->sc_txbusy = 1;
-
- /* Enable TX interrupt */
- __uart_setreg(bas, UART_IMSC, psc->imsc);
- }
+ /* Mark busy and enable TX interrupt */
+ sc->sc_txbusy = 1;
+ __uart_setreg(bas, UART_IMSC, psc->imsc);
uart_unlock(sc->sc_hwmtx);
- /* No interrupt expected, schedule the next fifo write */
- if (!sc->sc_txbusy)
- uart_sched_softih(sc, SER_INT_TXIDLE);
-
return (0);
}

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