D55253.diff
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	diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c
	--- a/sys/x86/cpufreq/hwpstate_amd.c
	+++ b/sys/x86/cpufreq/hwpstate_amd.c
	@@ -798,14 +798,6 @@
	data->init_request = sc->cppc.request;

	data->request = sc->cppc.request;
	- /*
	- * In Intel's reference manual, the default value of EPP is 0x80u which
	- * is the balanced mode. For consistency, we set the same value in AMD's
	- * CPPC driver.
	- */
	- SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_EPP_BITS, 0x80);
	- /* Enable autonomous mode by setting desired performance to 0. */
	- SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS, 0);
	/*
	* Assuming reading MSR_AMD_CPPC_CAPS_1 succeeded, if it stays at its
	* reset value (0) before CPPC activation (not supposed to happen, but
	@@ -834,6 +826,16 @@
	lowest_perf);
	SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_MAX_PERF_BITS,
	highest_perf);
	+ /*
	+ * Set controls to maximum performance to avoid regressions now that
	+ * CPPC is activated by default and to match what the P-state support
	+ * does.
	+ */
	+ SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_EPP_BITS, 0);
	+ /* 0 in "Desired Performance" is autonomous mode. */
	+ MPASS(highest_perf != 0);
	+ SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS,
	+ highest_perf);

	error = wrmsr_safe(MSR_AMD_CPPC_REQUEST, data->request);
	if (error != 0)