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Index: sys/amd64/amd64/machdep.c
===================================================================
--- sys/amd64/amd64/machdep.c
+++ sys/amd64/amd64/machdep.c
@@ -136,6 +136,9 @@
#ifdef FDT
#include <x86/fdt.h>
#endif
+#ifdef DEV_PCI
+#include <dev/pci/pcivar.h>
+#endif
#ifdef DEV_ATPIC
#include <x86/isa/icu.h>
@@ -176,6 +179,10 @@
/* Native function to fetch and parse the e820 map */
static void native_parse_memmap(caddr_t, vm_paddr_t *, int *);
+/* Helper functions for phys_avail_reserve. */
+static void phys_avail_insert_at(int index, vm_paddr_t val);
+static void phys_avail_delete_at(int index);
+
/* Default init_ops implementation. */
struct init_ops init_ops = {
.parse_preload_data = native_parse_preload_data,
@@ -1774,6 +1781,11 @@
/* now running on new page tables, configured,and u/iom is accessible */
+#ifdef DEV_PCI
+ /* This function might manipulate phys_avail. */
+ pci_early_quirks();
+#endif
+
if (late_console)
cninit();
@@ -2657,3 +2669,118 @@
}
#endif /* KDB */
+
+static void
+phys_avail_insert_at(int index, vm_paddr_t val)
+{
+ int j = PHYS_AVAIL_ARRAY_END;
+
+ while (j >= index) {
+ phys_avail[j+1] = phys_avail[j];
+ j--;
+ }
+ phys_avail[j+1] = val;
+}
+
+static void
+phys_avail_delete_at(int index)
+{
+ int j = index;
+
+ while (j <= PHYS_AVAIL_ARRAY_END) {
+ phys_avail[j] = phys_avail[j+1];
+ j++;
+ }
+}
+
+void
+phys_avail_reserve(vm_paddr_t start, vm_paddr_t end)
+{
+ int i = 0;
+
+ /* Check if inside a hole before first segment. */
+ if (end <= phys_avail[0])
+ return;
+
+ /* Check if inside any hole. */
+ while (phys_avail[i+2] != 0) {
+ if (start >= phys_avail[i+1] && end <= phys_avail[i+2])
+ return;
+ i += 2;
+ }
+
+ /* Check if new hole is after last segment end (i+1). */
+ if (start >= phys_avail[i+1])
+ return;
+
+ i=0;
+ /* Check if inside any segment */
+ while (phys_avail[i+1] != 0) {
+ if (start > phys_avail[i] && end < phys_avail[i+1]) {
+ phys_avail_insert_at(i+1, end);
+ phys_avail_insert_at(i+1, start);
+ return;
+ }
+ i += 2;
+ }
+
+ /* Other cases */
+ i=0;
+ while (phys_avail[i] < start && i <= PHYS_AVAIL_ARRAY_END) {
+ i++;
+ }
+
+ if (phys_avail[i+1] == 0) {
+ /* The new hole starts in the last segment and ends after. */
+ phys_avail[i] = start;
+ return;
+ }
+
+ /* At the index located on or after the new hole start. */
+ if (i % 2 == 0) {
+ /*
+ * Even index mean beginning of a segment. If hole ends in
+ * segment, shrink the segment. If exact match, delete the
+ * segment. Other cases are handled below.
+ */
+ if (start == phys_avail[i]) {
+ if (end < phys_avail[i+1]) {
+ phys_avail[i] = end;
+ return;
+ } else if (end == phys_avail[i+1]) {
+ phys_avail_delete_at(i);
+ phys_avail_delete_at(i);
+ return;
+ }
+ }
+ } else {
+ /*
+ * Odd index mean the hole starts inside a memory segment.
+ * Shrink segment to hole start.
+ */
+ phys_avail[i] = start;
+ i++;
+ }
+
+ int deleted = 0;
+ while (phys_avail[i] <= end && phys_avail[i+1] != 0) {
+ phys_avail_delete_at(i);
+ deleted++;
+ }
+
+ /* At the index located after the new hole end. */
+ if (i % 2 == 0 && deleted % 2 == 1) {
+ /*
+ * If index is even and odd number of entries have been deleted,
+ * we are at the end of a segment. Insert hole end before this
+ * segment end.
+ */
+ phys_avail_insert_at(i, end);
+ } else if (i % 2 == 1) {
+ /*
+ * Odd index mean our hole ends in the previous segment,
+ * move segment start to new hole end.
+ */
+ phys_avail[i-1] = start;
+ }
+}
Index: sys/conf/files
===================================================================
--- sys/conf/files
+++ sys/conf/files
@@ -2619,6 +2619,7 @@
dev/pci/ignore_pci.c optional pci
dev/pci/isa_pci.c optional pci isa
dev/pci/pci.c optional pci
+dev/pci/pci_early.c optional pci
dev/pci/pci_if.m standard
dev/pci/pci_iov.c optional pci pci_iov
dev/pci/pci_iov_if.m standard
Index: sys/dev/pci/pci_early.h
===================================================================
--- /dev/null
+++ sys/dev/pci/pci_early.h
@@ -0,0 +1,479 @@
+/*-
+ * Copyright (c) 2018 Johannes Lundberg
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _PCI_EARLY_H_
+#define _PCI_EARLY_H_
+
+/*
+ * TODO:
+ * Make a common drm/gpu header that both base and out of tree
+ * drm modules can use.
+ */
+
+#define PCI_ANY_ID (-1)
+#define PCI_VENDOR_INTEL 0x8086
+#define PCI_CLASS_VGA 0x0300
+
+#define INTEL_BSM 0x5c
+#define INTEL_BSM_MASK (-(1u << 20))
+
+#define INTEL_GMCH_CTRL 0x52
+#define INTEL_GMCH_VGA_DISABLE (1 << 1)
+#define SNB_GMCH_CTRL 0x50
+#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
+#define SNB_GMCH_GGMS_MASK 0x3
+#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
+#define SNB_GMCH_GMS_MASK 0x1f
+#define BDW_GMCH_GGMS_SHIFT 6
+#define BDW_GMCH_GGMS_MASK 0x3
+#define BDW_GMCH_GMS_SHIFT 8
+#define BDW_GMCH_GMS_MASK 0xff
+
+#define I830_GMCH_CTRL 0x52
+#define I830_GMCH_GMS_MASK 0x70
+#define I830_GMCH_GMS_LOCAL 0x10
+#define I830_GMCH_GMS_STOLEN_512 0x20
+#define I830_GMCH_GMS_STOLEN_1024 0x30
+#define I830_GMCH_GMS_STOLEN_8192 0x40
+
+#define I855_GMCH_GMS_MASK 0xF0
+#define I855_GMCH_GMS_STOLEN_0M 0x0
+#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
+#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
+#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
+#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
+#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
+#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
+#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
+#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
+#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
+
+#define INTEL_VGA_DEVICE(id, info) { \
+ 0x8086, id, \
+ (uintptr_t) info }
+
+#define INTEL_I810_IDS(info) \
+ INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
+ INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
+ INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
+
+#define INTEL_I815_IDS(info) \
+ INTEL_VGA_DEVICE(0x1132, info) /* I815*/
+
+#define INTEL_I830_IDS(info) \
+ INTEL_VGA_DEVICE(0x3577, info)
+
+#define INTEL_I845G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2562, info)
+
+#define INTEL_I85X_IDS(info) \
+ INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
+ INTEL_VGA_DEVICE(0x358e, info)
+
+#define INTEL_I865G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
+
+#define INTEL_I915G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
+ INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
+
+#define INTEL_I915GM_IDS(info) \
+ INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
+
+#define INTEL_I945G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
+
+#define INTEL_I945GM_IDS(info) \
+ INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
+ INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
+
+#define INTEL_I965G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
+ INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
+ INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
+ INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
+
+#define INTEL_G33_IDS(info) \
+ INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
+ INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
+ INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
+
+#define INTEL_I965GM_IDS(info) \
+ INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
+ INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
+
+#define INTEL_GM45_IDS(info) \
+ INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
+
+#define INTEL_G45_IDS(info) \
+ INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
+ INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
+ INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
+ INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
+ INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
+ INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
+
+#define INTEL_PINEVIEW_IDS(info) \
+ INTEL_VGA_DEVICE(0xa001, info), \
+ INTEL_VGA_DEVICE(0xa011, info)
+
+#define INTEL_IRONLAKE_D_IDS(info) \
+ INTEL_VGA_DEVICE(0x0042, info)
+
+#define INTEL_IRONLAKE_M_IDS(info) \
+ INTEL_VGA_DEVICE(0x0046, info)
+
+#define INTEL_SNB_D_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0102, info), \
+ INTEL_VGA_DEVICE(0x010A, info)
+
+#define INTEL_SNB_D_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0112, info), \
+ INTEL_VGA_DEVICE(0x0122, info)
+
+#define INTEL_SNB_D_IDS(info) \
+ INTEL_SNB_D_GT1_IDS(info), \
+ INTEL_SNB_D_GT2_IDS(info)
+
+#define INTEL_SNB_M_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0106, info)
+
+#define INTEL_SNB_M_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0116, info), \
+ INTEL_VGA_DEVICE(0x0126, info)
+
+#define INTEL_SNB_M_IDS(info) \
+ INTEL_SNB_M_GT1_IDS(info), \
+ INTEL_SNB_M_GT2_IDS(info)
+
+#define INTEL_IVB_M_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
+
+#define INTEL_IVB_M_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
+
+#define INTEL_IVB_M_IDS(info) \
+ INTEL_IVB_M_GT1_IDS(info), \
+ INTEL_IVB_M_GT2_IDS(info)
+
+#define INTEL_IVB_D_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
+
+#define INTEL_IVB_D_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
+
+#define INTEL_IVB_D_IDS(info) \
+ INTEL_IVB_D_GT1_IDS(info), \
+ INTEL_IVB_D_GT2_IDS(info)
+
+#define INTEL_IVB_Q_IDS(info) \
+ INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
+
+#define INTEL_HSW_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
+ INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
+ INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+ INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+ INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
+ INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
+ INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
+
+#define INTEL_HSW_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
+ INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
+ INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+ INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+ INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
+ INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
+ INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
+
+#define INTEL_HSW_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
+ INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
+ INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+ INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+ INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
+ INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
+ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+ INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
+ INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
+
+#define INTEL_HSW_IDS(info) \
+ INTEL_HSW_GT1_IDS(info), \
+ INTEL_HSW_GT2_IDS(info), \
+ INTEL_HSW_GT3_IDS(info)
+
+#define INTEL_VLV_IDS(info) \
+ INTEL_VGA_DEVICE(0x0f30, info), \
+ INTEL_VGA_DEVICE(0x0f31, info), \
+ INTEL_VGA_DEVICE(0x0f32, info), \
+ INTEL_VGA_DEVICE(0x0f33, info), \
+ INTEL_VGA_DEVICE(0x0157, info), \
+ INTEL_VGA_DEVICE(0x0155, info)
+
+#define INTEL_BDW_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+ INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
+
+#define INTEL_BDW_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
+ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
+
+#define INTEL_BDW_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
+ INTEL_VGA_DEVICE(0x162E, info), /* ULX */\
+ INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
+
+#define INTEL_BDW_RSVD_IDS(info) \
+ INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
+ INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
+ INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
+
+#define INTEL_BDW_IDS(info) \
+ INTEL_BDW_GT1_IDS(info), \
+ INTEL_BDW_GT2_IDS(info), \
+ INTEL_BDW_GT3_IDS(info), \
+ INTEL_BDW_RSVD_IDS(info)
+
+#define INTEL_CHV_IDS(info) \
+ INTEL_VGA_DEVICE(0x22b0, info), \
+ INTEL_VGA_DEVICE(0x22b1, info), \
+ INTEL_VGA_DEVICE(0x22b2, info), \
+ INTEL_VGA_DEVICE(0x22b3, info)
+
+#define INTEL_SKL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
+
+#define INTEL_SKL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
+
+#define INTEL_SKL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
+ INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
+ INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
+ INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
+
+#define INTEL_SKL_IDS(info) \
+ INTEL_SKL_GT1_IDS(info), \
+ INTEL_SKL_GT2_IDS(info), \
+ INTEL_SKL_GT3_IDS(info), \
+ INTEL_SKL_GT4_IDS(info)
+
+#define INTEL_BXT_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A84, info), \
+ INTEL_VGA_DEVICE(0x1A84, info), \
+ INTEL_VGA_DEVICE(0x1A85, info), \
+ INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
+ INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
+
+#define INTEL_GLK_IDS(info) \
+ INTEL_VGA_DEVICE(0x3184, info), \
+ INTEL_VGA_DEVICE(0x3185, info)
+
+#define INTEL_KBL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
+ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
+
+#define INTEL_KBL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
+
+#define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info)
+
+/* CFL S */
+#define INTEL_CFL_S_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
+ INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
+ INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
+
+#define INTEL_CFL_S_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
+
+/* CFL H */
+#define INTEL_CFL_H_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+
+/* CFL U GT1 */
+#define INTEL_CFL_U_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x3EA1, info), \
+ INTEL_VGA_DEVICE(0x3EA4, info)
+
+/* CFL U GT2 */
+#define INTEL_CFL_U_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x3EA0, info), \
+ INTEL_VGA_DEVICE(0x3EA3, info), \
+ INTEL_VGA_DEVICE(0x3EA9, info)
+
+/* CFL U GT3 */
+#define INTEL_CFL_U_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
+
+#define INTEL_CFL_IDS(info) \
+ INTEL_CFL_S_GT1_IDS(info), \
+ INTEL_CFL_S_GT2_IDS(info), \
+ INTEL_CFL_H_GT2_IDS(info), \
+ INTEL_CFL_U_GT1_IDS(info), \
+ INTEL_CFL_U_GT2_IDS(info), \
+ INTEL_CFL_U_GT3_IDS(info)
+
+/* CNL */
+#define INTEL_CNL_IDS(info) \
+ INTEL_VGA_DEVICE(0x5A51, info), \
+ INTEL_VGA_DEVICE(0x5A59, info), \
+ INTEL_VGA_DEVICE(0x5A41, info), \
+ INTEL_VGA_DEVICE(0x5A49, info), \
+ INTEL_VGA_DEVICE(0x5A52, info), \
+ INTEL_VGA_DEVICE(0x5A5A, info), \
+ INTEL_VGA_DEVICE(0x5A42, info), \
+ INTEL_VGA_DEVICE(0x5A4A, info), \
+ INTEL_VGA_DEVICE(0x5A50, info), \
+ INTEL_VGA_DEVICE(0x5A40, info), \
+ INTEL_VGA_DEVICE(0x5A54, info), \
+ INTEL_VGA_DEVICE(0x5A5C, info), \
+ INTEL_VGA_DEVICE(0x5A44, info), \
+ INTEL_VGA_DEVICE(0x5A4C, info)
+
+/* ICL */
+#define INTEL_ICL_11_IDS(info) \
+ INTEL_VGA_DEVICE(0x8A50, info), \
+ INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info), \
+ INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A5A, info), \
+ INTEL_VGA_DEVICE(0x8A5B, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A70, info)
+
+#endif /* _PCI_EARLY_H_ */
Index: sys/dev/pci/pci_early.c
===================================================================
--- /dev/null
+++ sys/dev/pci/pci_early.c
@@ -0,0 +1,333 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2018 Johannes Lundberg
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <x86/x86_var.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <vm/vm.h>
+
+#include "pci_early.h"
+
+#define MB (1024*1024)
+
+uint8_t pci_early_read_config_1(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+uint16_t pci_early_read_config_2(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+uint32_t pci_early_read_config_4(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset);
+
+struct pci_device_id {
+ uint32_t vendor;
+ uint32_t device;
+ uintptr_t data;
+};
+
+uint8_t
+pci_early_read_config_1(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset)
+{
+ uint32_t addr;
+ uint8_t val;
+
+ addr = (bus << 16) | (slot << 11) | (func << 8) | (offset & 0xFC);
+ outl(0xCF8, addr | 0x80000000 );
+ val = inb(0xCFC + (offset & 3));
+
+ return (val);
+}
+
+uint16_t
+pci_early_read_config_2(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset)
+{
+ uint32_t addr;
+ uint16_t val;
+
+ addr = (bus << 16) | (slot << 11) | (func << 8) | (offset & 0xFC);
+ outl(0xCF8, addr | 0x80000000);
+ val = inw(0xCFC + (offset & 2));
+
+ return (val);
+}
+
+uint32_t
+pci_early_read_config_4(uint8_t bus, uint8_t slot, uint8_t func, uint8_t offset)
+{
+ uint32_t addr;
+ uint32_t val;
+
+ addr = (bus << 16) | (slot << 11) | (func << 8) | (offset & 0xFC);
+ outl(0xCF8, addr | 0x80000000);
+ val = inl(0xCFC);
+
+ return (val);
+}
+
+
+
+#if defined(__amd64__)
+/*
+ * These global variables are read by LinuxKPI.
+ * LinuxKPI then provide this information to the i915 driver.
+ */
+vm_paddr_t intel_graphics_stolen_base = 0;
+vm_paddr_t intel_graphics_stolen_size = 0;
+
+/*
+ * Intel early quirks functions
+ */
+static vm_paddr_t
+intel_stolen_base_gen3(int bus, int slot, int func)
+{
+ vm_paddr_t val;
+
+ val = pci_early_read_config_4(bus, slot, func, INTEL_BSM);
+
+ return (val & INTEL_BSM_MASK);
+}
+
+static vm_paddr_t
+intel_stolen_size_gen3(int bus, int slot, int func)
+{
+ uint16_t ctrl;
+ uint16_t val;
+
+ ctrl = pci_early_read_config_2(0, 0, 0, I830_GMCH_CTRL);
+ val = ctrl & I855_GMCH_GMS_MASK;
+
+ switch (val) {
+ case I855_GMCH_GMS_STOLEN_1M:
+ return 1 * MB;
+ case I855_GMCH_GMS_STOLEN_4M:
+ return 4 * MB;
+ case I855_GMCH_GMS_STOLEN_8M:
+ return 8 * MB;
+ case I855_GMCH_GMS_STOLEN_16M:
+ return 16 * MB;
+ case I855_GMCH_GMS_STOLEN_32M:
+ return 32 * MB;
+ case I915_GMCH_GMS_STOLEN_48M:
+ return 48 * MB;
+ case I915_GMCH_GMS_STOLEN_64M:
+ return 64 * MB;
+ case G33_GMCH_GMS_STOLEN_128M:
+ return 128 * MB;
+ case G33_GMCH_GMS_STOLEN_256M:
+ return 256 * MB;
+ case INTEL_GMCH_GMS_STOLEN_96M:
+ return 96 * MB;
+ case INTEL_GMCH_GMS_STOLEN_160M:
+ return 160 * MB;
+ case INTEL_GMCH_GMS_STOLEN_224M:
+ return 224 * MB;
+ case INTEL_GMCH_GMS_STOLEN_352M:
+ return 352 * MB;
+ }
+
+ return 0;
+}
+
+static vm_paddr_t
+intel_stolen_size_gen6(int bus, int slot, int func)
+{
+ uint16_t ctrl;
+ uint16_t val;
+
+ ctrl = pci_early_read_config_2(bus, slot, func, SNB_GMCH_CTRL);
+ val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
+
+ return (val * 32 * MB);
+}
+
+static vm_paddr_t
+intel_stolen_size_gen8(int bus, int slot, int func)
+{
+ uint16_t ctrl;
+ vm_paddr_t val;
+
+ ctrl = pci_early_read_config_2(bus, slot, func, SNB_GMCH_CTRL);
+ val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
+
+ return (val * 32 * MB);
+}
+
+static vm_paddr_t
+intel_stolen_size_chv(int bus, int slot, int func)
+{
+ uint16_t ctrl;
+ uint16_t val;
+
+ ctrl = pci_early_read_config_2(bus, slot, func, SNB_GMCH_CTRL);
+ val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
+
+ /*
+ * 0x0 to 0x10: 32MB increments starting at 0MB
+ * 0x11 to 0x16: 4MB increments starting at 8MB
+ * 0x17 to 0x1d: 4MB increments start at 36MB
+ */
+ if (val < 0x11)
+ return (val * 32 * MB);
+ else if (val < 0x17)
+ return ((val - 0x11) * 4 * MB + 8 * MB);
+ else
+ return ((val - 0x17) * 4 * MB + 36 * MB);
+}
+
+static vm_paddr_t
+intel_stolen_size_gen9(int bus, int slot, int func)
+{
+ uint16_t ctrl;
+ uint16_t val;
+
+ ctrl = pci_early_read_config_2(bus, slot, func, SNB_GMCH_CTRL);
+ val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
+
+ /* 0x0 to 0xEF: 32MB increments starting at 0MB */
+ /* 0xF0 to 0xFE: 4MB increments starting at 4MB */
+ if (val < 0xF0)
+ return (val * 32 * MB);
+ else
+ return ((val - 0xF0) * 4 * MB + 4 * MB);
+ return 0;
+}
+
+struct intel_stolen_ops {
+ vm_paddr_t (*base)(int bus, int slot, int func);
+ vm_paddr_t (*size)(int bus, int slot, int func);
+};
+
+static const struct intel_stolen_ops intel_stolen_ops_gen3 = {
+ .base = intel_stolen_base_gen3,
+ .size = intel_stolen_size_gen3,
+};
+
+static const struct intel_stolen_ops intel_stolen_ops_gen6 = {
+ .base = intel_stolen_base_gen3,
+ .size = intel_stolen_size_gen6,
+};
+
+static const struct intel_stolen_ops intel_stolen_ops_gen8 = {
+ .base = intel_stolen_base_gen3,
+ .size = intel_stolen_size_gen8,
+};
+
+static const struct intel_stolen_ops intel_stolen_ops_gen9 = {
+ .base = intel_stolen_base_gen3,
+ .size = intel_stolen_size_gen9,
+};
+
+static const struct intel_stolen_ops intel_stolen_ops_chv = {
+ .base = intel_stolen_base_gen3,
+ .size = intel_stolen_size_chv,
+};
+
+static const struct pci_device_id intel_ids[] = {
+ INTEL_I915G_IDS(&intel_stolen_ops_gen3),
+ INTEL_I915GM_IDS(&intel_stolen_ops_gen3),
+ INTEL_I945G_IDS(&intel_stolen_ops_gen3),
+ INTEL_I945GM_IDS(&intel_stolen_ops_gen3),
+ INTEL_VLV_IDS(&intel_stolen_ops_gen6),
+ INTEL_PINEVIEW_IDS(&intel_stolen_ops_gen3),
+ INTEL_I965G_IDS(&intel_stolen_ops_gen3),
+ INTEL_G33_IDS(&intel_stolen_ops_gen3),
+ INTEL_I965GM_IDS(&intel_stolen_ops_gen3),
+ INTEL_GM45_IDS(&intel_stolen_ops_gen3),
+ INTEL_G45_IDS(&intel_stolen_ops_gen3),
+ INTEL_IRONLAKE_D_IDS(&intel_stolen_ops_gen3),
+ INTEL_IRONLAKE_M_IDS(&intel_stolen_ops_gen3),
+ INTEL_SNB_D_IDS(&intel_stolen_ops_gen6),
+ INTEL_SNB_M_IDS(&intel_stolen_ops_gen6),
+ INTEL_IVB_M_IDS(&intel_stolen_ops_gen6),
+ INTEL_IVB_D_IDS(&intel_stolen_ops_gen6),
+ INTEL_HSW_IDS(&intel_stolen_ops_gen6),
+ INTEL_BDW_IDS(&intel_stolen_ops_gen8),
+ INTEL_CHV_IDS(&intel_stolen_ops_chv),
+ INTEL_SKL_IDS(&intel_stolen_ops_gen9),
+ INTEL_BXT_IDS(&intel_stolen_ops_gen9),
+ INTEL_KBL_IDS(&intel_stolen_ops_gen9),
+ INTEL_CFL_IDS(&intel_stolen_ops_gen9),
+ INTEL_GLK_IDS(&intel_stolen_ops_gen9),
+ INTEL_CNL_IDS(&intel_stolen_ops_gen9),
+};
+
+/*
+ * Buggy BIOS don't reserve memory for the GPU properly and the OS
+ * can claim it before the GPU driver is loaded. This function will
+ * check the registers for base and size of this memory and reserve
+ * it for the GPU driver.
+ * gen3 (2004) and newer devices are supported. Support for older hw
+ * can be ported from Linux if needed.
+ */
+static void
+intel_graphics_stolen()
+{
+ const struct intel_stolen_ops *ops;
+ uint16_t vendor, device, class;
+ int i;
+ uint8_t bus = 0;
+ uint8_t slot = 2;
+ uint8_t func = 0;
+
+ vendor = pci_early_read_config_2(bus, slot, func, PCIR_VENDOR);
+ if (vendor != PCI_VENDOR_INTEL)
+ return;
+
+ class = pci_early_read_config_2(bus, slot, func, PCIR_SUBCLASS);
+ if (class != PCI_CLASS_VGA)
+ return;
+
+ device = pci_early_read_config_2(bus, slot, func, PCIR_DEVICE);
+ if (device == 0xFFFF)
+ return;
+
+ for (i = 0; i < nitems(intel_ids); i++) {
+ if (intel_ids[i].device != device)
+ continue;
+
+ ops = (const struct intel_stolen_ops*) intel_ids[i].data;
+
+ intel_graphics_stolen_base = ops->base(bus, slot, func);
+ intel_graphics_stolen_size = ops->size(bus, slot, func);
+
+ break;
+ }
+
+ phys_avail_reserve(intel_graphics_stolen_base,
+ intel_graphics_stolen_base + intel_graphics_stolen_size);
+}
+#endif /* defined(__amd64__) */
+
+void
+pci_early_quirks()
+{
+#if defined(__amd64__)
+ intel_graphics_stolen();
+#endif
+}
Index: sys/dev/pci/pcivar.h
===================================================================
--- sys/dev/pci/pcivar.h
+++ sys/dev/pci/pcivar.h
@@ -717,6 +717,14 @@
void vga_pci_unmap_bios(device_t dev, void *bios);
int vga_pci_repost(device_t dev);
+#if defined(__amd64__)
+extern vm_paddr_t intel_graphics_stolen_base;
+extern vm_paddr_t intel_graphics_stolen_size;
+#define PCI_EARLY_QUIRKS_INTEL_GRAPHICS_STOLEN 1
+#endif
+
+extern void pci_early_quirks(void);
+
/**
* Global eventhandlers invoked when PCI devices are added or removed
* from the system.
Index: sys/x86/include/x86_var.h
===================================================================
--- sys/x86/include/x86_var.h
+++ sys/x86/include/x86_var.h
@@ -149,5 +149,6 @@
int user_dbreg_trap(register_t dr6);
int minidumpsys(struct dumperinfo *);
struct pcb *get_pcb_td(struct thread *td);
+void phys_avail_reserve(vm_paddr_t start, vm_paddr_t end);
#endif

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