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Index: head/sys/arm/mv/mv_common.c
===================================================================
--- head/sys/arm/mv/mv_common.c
+++ head/sys/arm/mv/mv_common.c
@@ -2107,6 +2107,37 @@
return (EINVAL);
cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
+#ifdef SOC_MV_ARMADA38X
+ cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);
+#else
+ cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
+#endif
+ cpu_win_tbl[t].base = sram_base;
+ cpu_win_tbl[t].size = sram_size;
+ cpu_win_tbl[t].remap = ~0;
+ cpu_wins_no++;
+ debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
+
+ /* Check if there is a second CESA node */
+ while ((node = OF_peer(node)) != 0) {
+ if (fdt_is_compatible(node, "mrvl,cesa-sram")) {
+ if (fdt_regsize(node, &sram_base, &sram_size) != 0)
+ return (EINVAL);
+ break;
+ }
+ }
+
+ if (node == 0)
+ return (0);
+
+ t++;
+ if (t >= ((sizeof(cpu_win_tbl))/(sizeof(cpu_win_tbl[0])))) {
+ debugf("cannot fit CESA tuple into cpu_win_tbl\n");
+ return (ENOMEM);
+ }
+
+ /* Configure window for CESA1 */
+ cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
cpu_win_tbl[t].base = sram_base;
cpu_win_tbl[t].size = sram_size;
Index: head/sys/arm/mv/mvwin.h
===================================================================
--- head/sys/arm/mv/mvwin.h
+++ head/sys/arm/mv/mvwin.h
@@ -233,6 +233,19 @@
* 2: engine0
*/
#define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2))
+#elif defined(SOC_MV_ARMADA38X)
+#define MV_WIN_CESA_TARGET 9
+/*
+ * Bits [1:0] = Data swapping
+ * 0x0 = Byte swap
+ * 0x1 = No swap
+ * 0x2 = Byte and word swap
+ * 0x3 = Word swap
+ * Bits [4:2] = CESA select:
+ * 0x6 = CESA0
+ * 0x5 = CESA1
+ */
+#define MV_WIN_CESA_ATTR(eng_sel) (0x11 | (1 << (3 - (eng_sel))))
#else
#define MV_WIN_CESA_TARGET 3
#define MV_WIN_CESA_ATTR(eng_sel) 0

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