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Index: devel/abc/Makefile
===================================================================
--- /dev/null
+++ devel/abc/Makefile
@@ -0,0 +1,31 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= abc
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= System for Sequential Logic Synthesis and Formal Verification
+
+LICENSE= BSD
+LICENSE_FILE= ${WRKSRC}/copyright.txt
+
+USES= gmake readline
+
+USE_GITHUB= yes
+GH_ACCOUNT= berkeley-abc
+GH_PROJECT= abc
+GH_TAGNAME= e839091ba05083f166356f5455cea7ba3adad8d6
+
+MAKE_ARGS= CC=${CC} CXX=${CXX} ABC_USE_LIBSTDCXX=1
+
+PLIST_FILES= bin/abc
+
+do-install:
+ ${INSTALL_PROGRAM} ${WRKSRC}/abc ${STAGEDIR}${PREFIX}/bin
+
+post-install:
+ @${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/abc
+
+.include <bsd.port.mk>
Index: devel/abc/distinfo
===================================================================
--- /dev/null
+++ devel/abc/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1527189461
+SHA256 (berkeley-abc-abc-g20180310-e839091ba05083f166356f5455cea7ba3adad8d6_GH0.tar.gz) = 87f403e744db19f26c6bcfe92a926b1ba60e4f7d371e5c9903b03ab42d9c7487
+SIZE (berkeley-abc-abc-g20180310-e839091ba05083f166356f5455cea7ba3adad8d6_GH0.tar.gz) = 5577159
Index: devel/abc/pkg-descr
===================================================================
--- /dev/null
+++ devel/abc/pkg-descr
@@ -0,0 +1,3 @@
+ABC is System for Sequential Logic Synthesis and Formal Verification
+
+WWW: https://people.eecs.berkeley.edu/~alanmi/abc/
Index: devel/arachne-pnr/Makefile
===================================================================
--- /dev/null
+++ devel/arachne-pnr/Makefile
@@ -0,0 +1,25 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= arachne-pnr
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= Place and route tool for FPGAs
+
+LICENSE= MIT
+LICENSE_FILE= ${WRKSRC}/COPYING
+
+BUILD_DEPENDS= ${LOCALBASE}/share/icebox:devel/icestorm
+
+USES= gmake
+
+USE_GITHUB= yes
+GH_ACCOUNT= cseed
+GH_TAGNAME= 6701132cbd5c7b31edd0ff18ca6727eb3691186b
+
+post-install:
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/arachne-pnr
+
+.include <bsd.port.mk>
Index: devel/arachne-pnr/distinfo
===================================================================
--- /dev/null
+++ devel/arachne-pnr/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1527417304
+SHA256 (cseed-arachne-pnr-g20180310-6701132cbd5c7b31edd0ff18ca6727eb3691186b_GH0.tar.gz) = 0a4f3a5beefbe56863e6e9b680054b7f88bb7aed9682c8bb04c9147345320b49
+SIZE (cseed-arachne-pnr-g20180310-6701132cbd5c7b31edd0ff18ca6727eb3691186b_GH0.tar.gz) = 91249
Index: devel/arachne-pnr/pkg-descr
===================================================================
--- /dev/null
+++ devel/arachne-pnr/pkg-descr
@@ -0,0 +1,5 @@
+Arachne-pnr implements the place and route step of the hardware compilation
+process for FPGAs. It currently targets the Lattice Semiconductor iCE40 family
+of FPGAs.
+
+WWW: https://github.com/cseed/arachne-pnr
Index: devel/arachne-pnr/pkg-plist
===================================================================
--- /dev/null
+++ devel/arachne-pnr/pkg-plist
@@ -0,0 +1,5 @@
+%%DATADIR%%/chipdb-1k.bin
+%%DATADIR%%/chipdb-384.bin
+%%DATADIR%%/chipdb-5k.bin
+%%DATADIR%%/chipdb-8k.bin
+bin/arachne-pnr
Index: devel/icestorm/Makefile
===================================================================
--- /dev/null
+++ devel/icestorm/Makefile
@@ -0,0 +1,37 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= icestorm
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= IceStorm tools for Lattice iCE40 FPGAs
+
+LICENSE= ISCL
+LICENSE_FILE= ${WRKSRC}/COPYING
+
+LIB_DEPENDS= libftdi1.so:devel/libftdi1
+
+USES= gmake python:3.3+ shebangfix pkgconfig
+SHEBANG_FILES= ${WRKSRC}/icebox/*.py \
+ ${WRKSRC}/icebox/Makefile
+
+USE_GITHUB= yes
+GH_ACCOUNT= cliffordwolf
+GH_TAGNAME= 4476d83f76fa0222be0b691fe27c1e0228266f82
+
+post-patch:
+ @${REINPLACE_CMD} -e 's/python3 /python${PYTHON3_DEFAULT} /g' \
+ ${WRKSRC}/icebox/Makefile \
+ ${WRKSRC}/icetime/Makefile
+
+post-stage:
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/icepack
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/icepll
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/icebram
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/iceprog
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/icemulti
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/icetime
+
+.include <bsd.port.mk>
Index: devel/icestorm/distinfo
===================================================================
--- /dev/null
+++ devel/icestorm/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1527186186
+SHA256 (cliffordwolf-icestorm-g20180310-4476d83f76fa0222be0b691fe27c1e0228266f82_GH0.tar.gz) = 1dc3b821e0e4bcdc7f61655678e04fac847f820a5d15a2f89bcbe0baed477bcb
+SIZE (cliffordwolf-icestorm-g20180310-4476d83f76fa0222be0b691fe27c1e0228266f82_GH0.tar.gz) = 865104
Index: devel/icestorm/pkg-descr
===================================================================
--- /dev/null
+++ devel/icestorm/pkg-descr
@@ -0,0 +1,4 @@
+Project IceStorm aims at documenting the bitstream format of Lattice iCE40
+FPGAs and providing simple tools for analyzing and creating bitstream files.
+
+WWW: http://www.clifford.at/icestorm
Index: devel/icestorm/pkg-plist
===================================================================
--- /dev/null
+++ devel/icestorm/pkg-plist
@@ -0,0 +1,23 @@
+bin/icebox_asc2hlc
+bin/icebox_chipdb
+bin/icebox_colbuf
+bin/icebox_diff
+bin/icebox_explain
+bin/icebox_hlc2asc
+bin/icebox_html
+bin/icebox_maps
+bin/icebox_stat
+bin/icebox_vlog
+bin/icebox.py
+bin/iceboxdb.py
+bin/icebram
+bin/icemulti
+bin/icepack
+bin/icepll
+bin/iceprog
+bin/icetime
+bin/iceunpack
+share/icebox/chipdb-1k.txt
+share/icebox/chipdb-384.txt
+share/icebox/chipdb-5k.txt
+share/icebox/chipdb-8k.txt
Index: devel/lattice-ice40-examples-hx1k/Makefile
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx1k/Makefile
@@ -0,0 +1,42 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= lattice-ice40-examples-hx1k
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= Lattice iCE40 FPGA examples for Olimex HX1K board
+
+LICENSE= APACHE20
+LICENSE_FILE= ${WRKSRC}/LICENSE
+
+BUILD_DEPENDS= ${LOCALBASE}/bin/arachne-pnr:devel/arachne-pnr \
+ ${LOCALBASE}/bin/abc:devel/abc \
+ ${LOCALBASE}/bin/icepack:devel/icestorm \
+ ${LOCALBASE}/bin/yosys:devel/yosys
+
+USES= gmake
+
+NO_ARCH= yes
+USE_GITHUB= yes
+GH_ACCOUNT= OLIMEX
+GH_PROJECT= iCE40HX1K-EVB
+GH_TAGNAME= 69df5a7fc2daa8f00a984426b721499f6df22492
+
+EXAMPLESDIR= ${PREFIX}/share/examples/lattice-ice40-olimex
+
+do-build:
+ ${DO_MAKE_BUILD} -C ${WRKSRC}/demo/ice40hx1k-evb
+ ${DO_MAKE_BUILD} -C ${WRKSRC}/demo/ice40-io-video
+
+do-install:
+ @${MKDIR} ${STAGEDIR}${EXAMPLESDIR}
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40hx1k-evb/example.v ${STAGEDIR}${EXAMPLESDIR}/ice40hx1k-blinky.v
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40hx1k-evb/example.rpt ${STAGEDIR}${EXAMPLESDIR}/ice40hx1k-blinky.rpt
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40hx1k-evb/example.bin ${STAGEDIR}${EXAMPLESDIR}/ice40hx1k-blinky.bin
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40-io-video/example.v ${STAGEDIR}${EXAMPLESDIR}/ice40hx1k-vga-ps2.v
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40-io-video/example.rpt ${STAGEDIR}${EXAMPLESDIR}/ice40hx1k-vga-ps2.rpt
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40-io-video/example.bin ${STAGEDIR}${EXAMPLESDIR}/ice40hx1k-vga-ps2.bin
+
+.include <bsd.port.mk>
Index: devel/lattice-ice40-examples-hx1k/distinfo
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx1k/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1526722546
+SHA256 (OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz) = 99a6328ccfcd7a6a8a25d1521c028d1a1b5418b7de1dcc3b2db40e7d1bed9034
+SIZE (OLIMEX-iCE40HX1K-EVB-g20180310-69df5a7fc2daa8f00a984426b721499f6df22492_GH0.tar.gz) = 2181827
Index: devel/lattice-ice40-examples-hx1k/pkg-descr
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx1k/pkg-descr
@@ -0,0 +1,4 @@
+Examples (LED blinky and VGA + PS/2) for Lattice iCE40-HX1K FPGA board from
+Olimex
+
+WWW: https://github.com/OLIMEX/iCE40HX1K-EVB
Index: devel/lattice-ice40-examples-hx1k/pkg-plist
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx1k/pkg-plist
@@ -0,0 +1,6 @@
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx1k-blinky.bin
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx1k-blinky.rpt
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx1k-blinky.v
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx1k-vga-ps2.bin
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx1k-vga-ps2.rpt
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx1k-vga-ps2.v
Index: devel/lattice-ice40-examples-hx8k/Makefile
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx8k/Makefile
@@ -0,0 +1,42 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= lattice-ice40-examples-hx8k
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= Lattice iCE40 FPGA examples for Olimex HX8K board
+
+LICENSE= APACHE20
+LICENSE_FILE= ${WRKSRC}/LICENSE
+
+BUILD_DEPENDS= ${LOCALBASE}/bin/arachne-pnr:devel/arachne-pnr \
+ ${LOCALBASE}/bin/abc:devel/abc \
+ ${LOCALBASE}/bin/icepack:devel/icestorm \
+ ${LOCALBASE}/bin/yosys:devel/yosys
+
+USES= gmake
+
+NO_ARCH= yes
+USE_GITHUB= yes
+GH_ACCOUNT= OLIMEX
+GH_PROJECT= iCE40HX8K-EVB
+GH_TAGNAME= ae283711fc6c18f1905d0abf78195aed191ce612
+
+EXAMPLESDIR= ${PREFIX}/share/examples/lattice-ice40-olimex
+
+do-build:
+ ${DO_MAKE_BUILD} -C ${WRKSRC}/demo/ice40hx8k-evb
+ ${DO_MAKE_BUILD} -C ${WRKSRC}/demo/ice40-io-video
+
+do-install:
+ @${MKDIR} ${STAGEDIR}${EXAMPLESDIR}
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40hx8k-evb/example.v ${STAGEDIR}${EXAMPLESDIR}/ice40hx8k-blinky.v
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40hx8k-evb/example.rpt ${STAGEDIR}${EXAMPLESDIR}/ice40hx8k-blinky.rpt
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40hx8k-evb/example.bin ${STAGEDIR}${EXAMPLESDIR}/ice40hx8k-blinky.bin
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40-io-video/example.v ${STAGEDIR}${EXAMPLESDIR}/ice40hx8k-vga-ps2.v
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40-io-video/example.rpt ${STAGEDIR}${EXAMPLESDIR}/ice40hx8k-vga-ps2.rpt
+ ${INSTALL_DATA} ${WRKSRC}/demo/ice40-io-video/example.bin ${STAGEDIR}${EXAMPLESDIR}/ice40hx8k-vga-ps2.bin
+
+.include <bsd.port.mk>
Index: devel/lattice-ice40-examples-hx8k/distinfo
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx8k/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1526800249
+SHA256 (OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz) = 1f6d29d1420f608fda49f1b50085453bd4c6d32067773d210af386f95b24bd3a
+SIZE (OLIMEX-iCE40HX8K-EVB-g20180310-ae283711fc6c18f1905d0abf78195aed191ce612_GH0.tar.gz) = 1370726
Index: devel/lattice-ice40-examples-hx8k/pkg-descr
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx8k/pkg-descr
@@ -0,0 +1,4 @@
+Examples (LED blinky and VGA + PS/2) for Lattice iCE40-HX8K FPGA board from
+Olimex
+
+WWW: https://github.com/OLIMEX/iCE40HX8K-EVB
Index: devel/lattice-ice40-examples-hx8k/pkg-plist
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples-hx8k/pkg-plist
@@ -0,0 +1,6 @@
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx8k-blinky.bin
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx8k-blinky.rpt
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx8k-blinky.v
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx8k-vga-ps2.bin
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx8k-vga-ps2.rpt
+%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ice40hx8k-vga-ps2.v
Index: devel/lattice-ice40-examples/Makefile
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples/Makefile
@@ -0,0 +1,25 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= lattice-ice40-examples
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= Lattice iCE40 FPGA examples for Olimex boards
+
+LICENSE= APACHE20
+
+RUN_DEPENDS= ${EXAMPLESDIR}/ice40hx1k-blinky.bin:devel/lattice-ice40-examples-hx1k \
+ ${EXAMPLESDIR}/ice40hx1k-vga-ps2.bin:devel/lattice-ice40-examples-hx1k \
+ ${EXAMPLESDIR}/ice40hx8k-blinky.bin:devel/lattice-ice40-examples-hx8k \
+ ${EXAMPLESDIR}/ice40hx8k-vga-ps2.bin:devel/lattice-ice40-examples-hx8k
+
+EXAMPLESDIR= ${PREFIX}/share/examples/lattice-ice40-olimex
+
+NO_BUILD= yes
+NO_ARCH= yes
+
+USES= metaport
+
+.include <bsd.port.mk>
Index: devel/lattice-ice40-examples/pkg-descr
===================================================================
--- /dev/null
+++ devel/lattice-ice40-examples/pkg-descr
@@ -0,0 +1,4 @@
+Examples (LED blinky and VGA + PS/2) for Lattice iCE40 FPGA boards from Olimex
+
+WWW: https://github.com/OLIMEX/iCE40HX1K-EVB
+WWW: https://github.com/OLIMEX/iCE40HX8K-EVB
Index: devel/lattice-ice40-tools/Makefile
===================================================================
--- /dev/null
+++ devel/lattice-ice40-tools/Makefile
@@ -0,0 +1,24 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= lattice-ice40-tools
+PORTVERSION= g20180310
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= Open source tools for Lattice iCE40 FPGAs
+
+LICENSE= ISCL MIT
+LICENSE_COMB= multi
+
+RUN_DEPENDS= ${LOCALBASE}/bin/arachne-pnr:devel/arachne-pnr \
+ ${LOCALBASE}/bin/abc:devel/abc \
+ ${LOCALBASE}/bin/icepack:devel/icestorm \
+ ${LOCALBASE}/bin/yosys:devel/yosys
+
+NO_BUILD= yes
+NO_ARCH= yes
+
+USES= metaport
+
+.include <bsd.port.mk>
Index: devel/lattice-ice40-tools/pkg-descr
===================================================================
--- /dev/null
+++ devel/lattice-ice40-tools/pkg-descr
@@ -0,0 +1,6 @@
+Metaport which enables a fully open source Verilog-to-Bitstream flow for iCE40
+FPGAs.
+
+WWW: http://www.clifford.at/icestorm
+WWW: https://github.com/cseed/arachne-pnr
+WWW: http://www.clifford.at/yosys/
Index: devel/yosys/Makefile
===================================================================
--- /dev/null
+++ devel/yosys/Makefile
@@ -0,0 +1,45 @@
+# Created by: Johnny Sorocil <propaliidealist@gmail.com>
+# $FreeBSD$
+
+PORTNAME= yosys
+DISTVERSION= 0.7-783
+DISTVERSIONSUFFIX= -gbab39eac
+CATEGORIES= devel
+
+MAINTAINER= propaliidealist@gmail.com
+COMMENT= Yosys Open SYnthesis Suite
+
+LICENSE= ISCL
+LICENSE_FILE= ${WRKSRC}/COPYING
+
+BUILD_DEPENDS= gawk:lang/gawk \
+ pkgconf:devel/pkgconf \
+ tclsh:lang/tcl-wrapper \
+ bash:shells/bash \
+ abc:devel/abc
+
+USES= gmake shebangfix readline tcl bison python:3.6+,build
+SHEBANG_FILES= ${WRKSRC}/misc/yosys-config.in
+
+USE_GITHUB= yes
+GH_ACCOUNT= YosysHQ
+GH_TAGNAME= bab39eacce5c17c42d50a3a60a67cc8a9ee52d98
+
+LIB_DEPENDS+= libffi.so:devel/libffi
+
+post-patch:
+ @${REINPLACE_CMD} -e 's/python3 /python${PYTHON3_DEFAULT} /g' \
+ ${WRKSRC}/techlibs/ice40/Makefile.inc \
+ ${WRKSRC}/techlibs/xilinx/Makefile.inc \
+ ${WRKSRC}/techlibs/common/Makefile.inc \
+ ${WRKSRC}/tests/fsm/run-test.sh \
+ ${WRKSRC}/tests/realmath/run-test.sh \
+ ${WRKSRC}/tests/share/run-test.sh \
+ ${WRKSRC}/tests/bram/run-test.sh
+ @${SED} -i '' 's/ABCEXTERNAL ?=/ABCEXTERNAL ?= abc/g' ${WRKSRC}/Makefile
+
+post-install:
+ ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys
+ ${SED} -i '' 's/python3/python${PYTHON3_DEFAULT}/g' ${STAGEDIR}${LOCALBASE}/bin/yosys-smtbmc
+
+.include <bsd.port.mk>
Index: devel/yosys/distinfo
===================================================================
--- /dev/null
+++ devel/yosys/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1527191683
+SHA256 (YosysHQ-yosys-0.7-783-gbab39eac-bab39eacce5c17c42d50a3a60a67cc8a9ee52d98_GH0.tar.gz) = 1c97050a19f653fc957550cb5a505e1ebcb5722eade487bd86e8a5f9681ae09c
+SIZE (YosysHQ-yosys-0.7-783-gbab39eac-bab39eacce5c17c42d50a3a60a67cc8a9ee52d98_GH0.tar.gz) = 1089933
Index: devel/yosys/pkg-descr
===================================================================
--- /dev/null
+++ devel/yosys/pkg-descr
@@ -0,0 +1,5 @@
+Yosys is a framework for Verilog RTL synthesis. It currently has extensive
+Verilog-2005 support and provides a basic set of synthesis algorithms for
+various application domains.
+
+WWW: http://www.clifford.at/yosys/
Index: devel/yosys/pkg-plist
===================================================================
--- /dev/null
+++ devel/yosys/pkg-plist
@@ -0,0 +1,86 @@
+%%DATADIR%%/achronix/speedster22i/cells_map.v
+%%DATADIR%%/achronix/speedster22i/cells_sim.v
+%%DATADIR%%/adff2dff.v
+%%DATADIR%%/cells.lib
+%%DATADIR%%/coolrunner2/cells_latch.v
+%%DATADIR%%/coolrunner2/cells_sim.v
+%%DATADIR%%/coolrunner2/tff_extract.v
+%%DATADIR%%/coolrunner2/xc2_dff.lib
+%%DATADIR%%/dff2ff.v
+%%DATADIR%%/gowin/cells_map.v
+%%DATADIR%%/gowin/cells_sim.v
+%%DATADIR%%/greenpak4/cells_blackbox.v
+%%DATADIR%%/greenpak4/cells_latch.v
+%%DATADIR%%/greenpak4/cells_map.v
+%%DATADIR%%/greenpak4/cells_sim_ams.v
+%%DATADIR%%/greenpak4/cells_sim_digital.v
+%%DATADIR%%/greenpak4/cells_sim_wip.v
+%%DATADIR%%/greenpak4/cells_sim.v
+%%DATADIR%%/greenpak4/gp_dff.lib
+%%DATADIR%%/ice40/arith_map.v
+%%DATADIR%%/ice40/brams_init1.vh
+%%DATADIR%%/ice40/brams_init2.vh
+%%DATADIR%%/ice40/brams_init3.vh
+%%DATADIR%%/ice40/brams_map.v
+%%DATADIR%%/ice40/brams.txt
+%%DATADIR%%/ice40/cells_map.v
+%%DATADIR%%/ice40/cells_sim.v
+%%DATADIR%%/ice40/latches_map.v
+%%DATADIR%%/include/backends/ilang/ilang_backend.h
+%%DATADIR%%/include/frontends/ast/ast.h
+%%DATADIR%%/include/kernel/celledges.h
+%%DATADIR%%/include/kernel/celltypes.h
+%%DATADIR%%/include/kernel/consteval.h
+%%DATADIR%%/include/kernel/hashlib.h
+%%DATADIR%%/include/kernel/log.h
+%%DATADIR%%/include/kernel/macc.h
+%%DATADIR%%/include/kernel/modtools.h
+%%DATADIR%%/include/kernel/register.h
+%%DATADIR%%/include/kernel/rtlil.h
+%%DATADIR%%/include/kernel/satgen.h
+%%DATADIR%%/include/kernel/sigtools.h
+%%DATADIR%%/include/kernel/utils.h
+%%DATADIR%%/include/kernel/yosys.h
+%%DATADIR%%/include/libs/ezsat/ezminisat.h
+%%DATADIR%%/include/libs/ezsat/ezsat.h
+%%DATADIR%%/include/libs/sha1/sha1.h
+%%DATADIR%%/include/passes/fsm/fsmdata.h
+%%DATADIR%%/intel/a10gx/cells_map.v
+%%DATADIR%%/intel/a10gx/cells_sim.v
+%%DATADIR%%/intel/common/altpll_bb.v
+%%DATADIR%%/intel/common/brams_map.v
+%%DATADIR%%/intel/common/brams.txt
+%%DATADIR%%/intel/common/m9k_bb.v
+%%DATADIR%%/intel/cyclone10/cells_map.v
+%%DATADIR%%/intel/cyclone10/cells_sim.v
+%%DATADIR%%/intel/cycloneiv/cells_map.v
+%%DATADIR%%/intel/cycloneiv/cells_sim.v
+%%DATADIR%%/intel/cycloneive/cells_map.v
+%%DATADIR%%/intel/cycloneive/cells_sim.v
+%%DATADIR%%/intel/cyclonev/cells_map.v
+%%DATADIR%%/intel/cyclonev/cells_sim.v
+%%DATADIR%%/intel/max10/cells_map.v
+%%DATADIR%%/intel/max10/cells_sim.v
+%%DATADIR%%/pmux2mux.v
+%%DATADIR%%/python3/smtio.py
+%%DATADIR%%/simcells.v
+%%DATADIR%%/simlib.v
+%%DATADIR%%/techmap.v
+%%DATADIR%%/xilinx/arith_map.v
+%%DATADIR%%/xilinx/brams_bb.v
+%%DATADIR%%/xilinx/brams_init_%%PYTHON_SUFFIX%%.vh
+%%DATADIR%%/xilinx/brams_init_16.vh
+%%DATADIR%%/xilinx/brams_init_18.vh
+%%DATADIR%%/xilinx/brams_init_32.vh
+%%DATADIR%%/xilinx/brams_map.v
+%%DATADIR%%/xilinx/brams.txt
+%%DATADIR%%/xilinx/cells_map.v
+%%DATADIR%%/xilinx/cells_sim.v
+%%DATADIR%%/xilinx/cells_xtra.v
+%%DATADIR%%/xilinx/drams_map.v
+%%DATADIR%%/xilinx/drams.txt
+%%DATADIR%%/xilinx/lut2lut.v
+bin/yosys
+bin/yosys-config
+bin/yosys-filterlib
+bin/yosys-smtbmc

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