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	diff --git a/sys/arm64/arm64/busdma_bounce.c b/sys/arm64/arm64/busdma_bounce.c
	--- a/sys/arm64/arm64/busdma_bounce.c
	+++ b/sys/arm64/arm64/busdma_bounce.c
	@@ -985,15 +985,15 @@
	}

	static void
	-dma_preread_safe(vm_offset_t va, vm_size_t size)
	+dma_preread_safe(char *va, vm_size_t size)
	{
	/*
	* Write back any partial cachelines immediately before and
	* after the DMA region.
	*/
	- if (va & (dcache_line_size - 1))
	+ if (!__is_aligned(va, dcache_line_size))
	cpu_dcache_wb_range(va, 1);
	- if ((va + size) & (dcache_line_size - 1))
	+ if (!__is_aligned(va + size, dcache_line_size))
	cpu_dcache_wb_range(va + size, 1);

	cpu_dcache_inv_range(va, size);
	@@ -1030,7 +1030,7 @@
	switch (op) {
	case BUS_DMASYNC_PREWRITE:
	case BUS_DMASYNC_PREWRITE \| BUS_DMASYNC_PREREAD:
	- cpu_dcache_wb_range(va, len);
	+ cpu_dcache_wb_range((void *)va, len);
	break;
	case BUS_DMASYNC_PREREAD:
	/*
	@@ -1043,11 +1043,11 @@
	* misalignment. Buffers which are not mbufs bounce if
	* they are not aligned to a cacheline.
	*/
	- dma_preread_safe(va, len);
	+ dma_preread_safe((void *)va, len);
	break;
	case BUS_DMASYNC_POSTREAD:
	case BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE:
	- cpu_dcache_inv_range(va, len);
	+ cpu_dcache_inv_range((void *)va, len);
	break;
	default:
	panic("unsupported combination of sync operations: "
	@@ -1097,7 +1097,7 @@
	if (tempvaddr != 0)
	pmap_quick_remove_page(tempvaddr);
	if ((map->flags & DMAMAP_COHERENT) == 0)
	- cpu_dcache_wb_range(bpage->vaddr,
	+ cpu_dcache_wb_range((void *)bpage->vaddr,
	bpage->datacount);
	bpage = STAILQ_NEXT(bpage, links);
	}
	@@ -1105,7 +1105,7 @@
	} else if ((op & BUS_DMASYNC_PREREAD) != 0) {
	while (bpage != NULL) {
	if ((map->flags & DMAMAP_COHERENT) == 0)
	- cpu_dcache_wbinv_range(bpage->vaddr,
	+ cpu_dcache_wbinv_range((void *)bpage->vaddr,
	bpage->datacount);
	bpage = STAILQ_NEXT(bpage, links);
	}
	@@ -1114,7 +1114,7 @@
	if ((op & BUS_DMASYNC_POSTREAD) != 0) {
	while (bpage != NULL) {
	if ((map->flags & DMAMAP_COHERENT) == 0)
	- cpu_dcache_inv_range(bpage->vaddr,
	+ cpu_dcache_inv_range((void *)bpage->vaddr,
	bpage->datacount);
	tempvaddr = 0;
	datavaddr = bpage->datavaddr;
	diff --git a/sys/arm64/arm64/cpufunc_asm.S b/sys/arm64/arm64/cpufunc_asm.S
	--- a/sys/arm64/arm64/cpufunc_asm.S
	+++ b/sys/arm64/arm64/cpufunc_asm.S
	@@ -104,7 +104,7 @@
	END(arm64_tlb_flushID)

	/*
	- * void arm64_dcache_wb_range(vm_offset_t, vm_size_t)
	+ * void arm64_dcache_wb_range(void *, vm_size_t)
	*/
	ENTRY(arm64_dcache_wb_range)
	cache_handle_range dcop = cvac
	@@ -112,7 +112,7 @@
	END(arm64_dcache_wb_range)

	/*
	- * void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t)
	+ * void arm64_dcache_wbinv_range(void *, vm_size_t)
	*/
	ENTRY(arm64_dcache_wbinv_range)
	cache_handle_range dcop = civac
	@@ -120,7 +120,7 @@
	END(arm64_dcache_wbinv_range)

	/*
	- * void arm64_dcache_inv_range(vm_offset_t, vm_size_t)
	+ * void arm64_dcache_inv_range(void *, vm_size_t)
	*
	* Note, we must not invalidate everything. If the range is too big we
	* must use wb-inv of the entire cache.
	@@ -131,7 +131,7 @@
	END(arm64_dcache_inv_range)

	/*
	- * void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t)
	+ * void arm64_dic_idc_icache_sync_range(void *, vm_size_t)
	* When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb.
	* When the CTR_EL0.DIC bit is set icache invalidation becomes an isb.
	*/
	@@ -142,7 +142,7 @@
	END(arm64_dic_idc_icache_sync_range)

	/*
	- * void arm64_idc_aliasing_icache_sync_range(vm_offset_t, vm_size_t)
	+ * void arm64_idc_aliasing_icache_sync_range(void *, vm_size_t)
	* When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb.
	*/
	ENTRY(arm64_idc_aliasing_icache_sync_range)
	@@ -154,7 +154,7 @@
	END(arm64_idc_aliasing_icache_sync_range)

	/*
	- * void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t)
	+ * void arm64_aliasing_icache_sync_range(void *, vm_size_t)
	*/
	ENTRY(arm64_aliasing_icache_sync_range)
	/*
	@@ -170,7 +170,7 @@
	END(arm64_aliasing_icache_sync_range)

	/*
	- * int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t)
	+ * int arm64_icache_sync_range_checked(void *, vm_size_t)
	*/
	ENTRY(arm64_icache_sync_range_checked)
	adr x5, cache_maint_fault
	diff --git a/sys/arm64/arm64/db_interface.c b/sys/arm64/arm64/db_interface.c
	--- a/sys/arm64/arm64/db_interface.c
	+++ b/sys/arm64/arm64/db_interface.c
	@@ -175,7 +175,7 @@
	* Ensure the I & D cache are in sync if we wrote
	* to executable memory.
	*/
	- cpu_icache_sync_range(addr, (vm_size_t)size);
	+ cpu_icache_sync_range((void *)addr, (vm_size_t)size);
	}
	}
	(void)kdb_jmpbuf(prev_jb);
	diff --git a/sys/arm64/arm64/elf_machdep.c b/sys/arm64/arm64/elf_machdep.c
	--- a/sys/arm64/arm64/elf_machdep.c
	+++ b/sys/arm64/arm64/elf_machdep.c
	@@ -299,7 +299,7 @@
	{

	if (lf->id != 1)
	- cpu_icache_sync_range((vm_offset_t)lf->address, lf->size);
	+ cpu_icache_sync_range(lf->address, lf->size);
	return (0);
	}

	diff --git a/sys/arm64/arm64/freebsd32_machdep.c b/sys/arm64/arm64/freebsd32_machdep.c
	--- a/sys/arm64/arm64/freebsd32_machdep.c
	+++ b/sys/arm64/arm64/freebsd32_machdep.c
	@@ -94,7 +94,8 @@
	return (error);
	if ((uint64_t)args.addr + (uint64_t)args.size > 0xffffffff)
	return (EINVAL);
	- cpu_icache_sync_range_checked(args.addr, args.size);
	+ cpu_icache_sync_range_checked(
	+ (void *)(uintptr_t)args.addr, args.size);
	return 0;
	}
	case ARM_GET_VFPSTATE:
	diff --git a/sys/arm64/arm64/gicv3_its.c b/sys/arm64/arm64/gicv3_its.c
	--- a/sys/arm64/arm64/gicv3_its.c
	+++ b/sys/arm64/arm64/gicv3_its.c
	@@ -744,7 +744,7 @@
	LPI_CONFTAB_SIZE);

	/* Flush the table to memory */
	- cpu_dcache_wb_range((vm_offset_t)sc->sc_conf_base, LPI_CONFTAB_SIZE);
	+ cpu_dcache_wb_range(sc->sc_conf_base, LPI_CONFTAB_SIZE);
	}

	static void
	@@ -761,7 +761,7 @@
	0, LPI_PENDTAB_MAX_ADDR, LPI_PENDTAB_ALIGN, 0);

	/* Flush so the ITS can see the memory */
	- cpu_dcache_wb_range((vm_offset_t)sc->sc_pend_base[i],
	+ cpu_dcache_wb_range(sc->sc_pend_base[i],
	LPI_PENDTAB_SIZE);
	}
	}
	@@ -1158,7 +1158,7 @@

	if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
	/* Clean D-cache under command. */
	- cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_lpi], 1);
	+ cpu_dcache_wb_range(&conf[girq->gi_lpi], 1);
	} else {
	/* DSB inner shareable, store */
	dsb(ishst);
	@@ -1182,7 +1182,7 @@

	if ((sc->sc_its_flags & ITS_FLAGS_LPI_CONF_FLUSH) != 0) {
	/* Clean D-cache under command. */
	- cpu_dcache_wb_range((vm_offset_t)&conf[girq->gi_lpi], 1);
	+ cpu_dcache_wb_range(&conf[girq->gi_lpi], 1);
	} else {
	/* DSB inner shareable, store */
	dsb(ishst);
	@@ -1396,12 +1396,11 @@
	ptable->ptab_page_size, 0);

	if (!shareable)
	- cpu_dcache_wb_range((vm_offset_t)l2_table, ptable->ptab_l2_size);
	+ cpu_dcache_wb_range(l2_table, ptable->ptab_l2_size);

	table[index] = vtophys(l2_table) \| GITS_BASER_VALID;
	if (!shareable)
	- cpu_dcache_wb_range((vm_offset_t)&table[index],
	- sizeof(table[index]));
	+ cpu_dcache_wb_range(&table[index], sizeof(table[index]));

	dsb(sy);
	return (true);
	@@ -1463,7 +1462,7 @@

	/* Make sure device sees zeroed ITT. */
	if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0)
	- cpu_dcache_wb_range((vm_offset_t)its_dev->itt, its_dev->itt_size);
	+ cpu_dcache_wb_range(its_dev->itt, its_dev->itt_size);

	mtx_lock_spin(&sc->sc_its_dev_lock);
	TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
	@@ -1861,7 +1860,7 @@

	if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0) {
	/* Clean D-cache under command. */
	- cpu_dcache_wb_range((vm_offset_t)cmd, sizeof(*cmd));
	+ cpu_dcache_wb_range(cmd, sizeof(*cmd));
	} else {
	/* DSB inner shareable, store */
	dsb(ishst);
	diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
	--- a/sys/arm64/arm64/identcpu.c
	+++ b/sys/arm64/arm64/identcpu.c
	@@ -83,7 +83,7 @@
	* The default implementation of I-cache sync assumes we have an
	* aliasing cache until we know otherwise.
	*/
	-void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t) =
	+void (arm64_icache_sync_range)(void , vm_size_t) =
	&arm64_aliasing_icache_sync_range;

	static int
	diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c
	--- a/sys/arm64/arm64/pmap.c
	+++ b/sys/arm64/arm64/pmap.c
	@@ -4738,10 +4738,11 @@
	m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
	(opa != pa \|\| (orig_l3 & ATTR_S1_XN))) {
	PMAP_ASSERT_STAGE1(pmap);
	- cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
	+ cpu_icache_sync_range((void *)PHYS_TO_DMAP(pa),
	+ PAGE_SIZE);
	}
	} else {
	- cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
	+ cpu_dcache_wb_range((void *)PHYS_TO_DMAP(pa), PAGE_SIZE);
	}

	/*
	@@ -5006,7 +5007,7 @@
	if ((new_l2 & ATTR_S1_XN) == 0 && (PTE_TO_PHYS(new_l2) !=
	PTE_TO_PHYS(old_l2) \|\| (old_l2 & ATTR_S1_XN) != 0) &&
	pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) {
	- cpu_icache_sync_range(PHYS_TO_DMAP(PTE_TO_PHYS(new_l2)),
	+ cpu_icache_sync_range((void *)PHYS_TO_DMAP(PTE_TO_PHYS(new_l2)),
	L2_SIZE);
	}

	@@ -5219,7 +5220,7 @@
	/* Sync icache before the mapping is stored to PTE */
	if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
	m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
	- cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
	+ cpu_icache_sync_range((void *)PHYS_TO_DMAP(pa), PAGE_SIZE);

	pmap_store(l3, l3_val);
	dsb(ishst);
	@@ -6990,7 +6991,7 @@
	* the cache.
	*/
	if (mode == VM_MEMATTR_UNCACHEABLE)
	- cpu_dcache_wbinv_range(tmpva, pte_size);
	+ cpu_dcache_wbinv_range((void *)tmpva, pte_size);
	tmpva += pte_size;
	}
	}
	@@ -7673,7 +7674,7 @@
	("%s: Address not in canonical form: %lx", __func__, va));

	if (ADDR_IS_KERNEL(va)) {
	- cpu_icache_sync_range(va, sz);
	+ cpu_icache_sync_range((void *)va, sz);
	} else {
	u_int len, offset;
	vm_paddr_t pa;
	@@ -7686,7 +7687,8 @@
	/* Extract the physical address & find it in the DMAP */
	pa = pmap_extract(pmap, va);
	if (pa != 0)
	- cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
	+ cpu_icache_sync_range((void *)PHYS_TO_DMAP(pa),
	+ len);

	/* Move to the next page */
	sz -= len;
	diff --git a/sys/arm64/include/cpufunc.h b/sys/arm64/include/cpufunc.h
	--- a/sys/arm64/include/cpufunc.h
	+++ b/sys/arm64/include/cpufunc.h
	@@ -177,20 +177,20 @@
	#define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
	#define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))

	-extern void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t);
	+extern void (arm64_icache_sync_range)(void , vm_size_t);

	#define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
	#define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s))

	void arm64_nullop(void);
	void arm64_tlb_flushID(void);
	-void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t);
	-void arm64_idc_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
	-void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
	-int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t);
	-void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
	-void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
	-void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
	+void arm64_dic_idc_icache_sync_range(void *, vm_size_t);
	+void arm64_idc_aliasing_icache_sync_range(void *, vm_size_t);
	+void arm64_aliasing_icache_sync_range(void *, vm_size_t);
	+int arm64_icache_sync_range_checked(void *, vm_size_t);
	+void arm64_dcache_wbinv_range(void *, vm_size_t);
	+void arm64_dcache_inv_range(void *, vm_size_t);
	+void arm64_dcache_wb_range(void *, vm_size_t);
	bool arm64_get_writable_addr(vm_offset_t, vm_offset_t *);

	#endif /* _KERNEL */
	diff --git a/sys/arm64/include/kdb.h b/sys/arm64/include/kdb.h
	--- a/sys/arm64/include/kdb.h
	+++ b/sys/arm64/include/kdb.h
	@@ -44,7 +44,7 @@
	kdb_cpu_sync_icache(unsigned char *addr, size_t size)
	{

	- cpu_icache_sync_range((vm_offset_t)addr, size);
	+ cpu_icache_sync_range(addr, size);
	}

	static __inline void
	diff --git a/sys/cddl/dev/fbt/aarch64/fbt_isa.c b/sys/cddl/dev/fbt/aarch64/fbt_isa.c
	--- a/sys/cddl/dev/fbt/aarch64/fbt_isa.c
	+++ b/sys/cddl/dev/fbt/aarch64/fbt_isa.c
	@@ -77,7 +77,7 @@
	panic("%s: Unable to write new instruction", __func__);

	(fbt_patchval_t )addr = val;
	- cpu_icache_sync_range((vm_offset_t)fbt->fbtp_patchpoint, 4);
	+ cpu_icache_sync_range(fbt->fbtp_patchpoint, 4);
	}

	int
	diff --git a/sys/cddl/dev/kinst/aarch64/kinst_isa.c b/sys/cddl/dev/kinst/aarch64/kinst_isa.c
	--- a/sys/cddl/dev/kinst/aarch64/kinst_isa.c
	+++ b/sys/cddl/dev/kinst/aarch64/kinst_isa.c
	@@ -153,8 +153,7 @@
	kinst_memcpy(kp->kp_tramp, &kp->kp_savedval, INSN_SIZE);
	kinst_memcpy(&kp->kp_tramp[INSN_SIZE], &bpt, INSN_SIZE);

	- cpu_icache_sync_range((vm_offset_t)kp->kp_tramp,
	- (vm_size_t)KINST_TRAMP_SIZE);
	+ cpu_icache_sync_range(kp->kp_tramp, KINST_TRAMP_SIZE);
	}

	/*
	@@ -241,8 +240,7 @@
	if (!arm64_get_writable_addr((vm_offset_t)kp->kp_patchpoint, &addr))
	panic("%s: Unable to write new instruction", __func__);
	(kinst_patchval_t )addr = val;
	- cpu_icache_sync_range((vm_offset_t)kp->kp_patchpoint,
	- (vm_size_t)INSN_SIZE);
	+ cpu_icache_sync_range(kp->kp_patchpoint, INSN_SIZE);
	}

	static void

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