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Index: sys/arm/mv/mvreg.h
===================================================================
--- sys/arm/mv/mvreg.h
+++ sys/arm/mv/mvreg.h
@@ -127,6 +127,7 @@
*/
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define RSTOUTn_MASK 0x60
+#define RSTOUTn_MASK_WD 0x400
#define SYSTEM_SOFT_RESET 0x64
#define WD_RSTOUTn_MASK 0x4
#define WD_GLOBAL_MASK 0x00000100
@@ -219,8 +220,10 @@
#define CPU_TIMER0_AUTO 0x00000002
#define CPU_TIMER1_EN 0x00000004
#define CPU_TIMER1_AUTO 0x00000008
-#define CPU_TIMER_WD_EN 0x00000010
-#define CPU_TIMER_WD_AUTO 0x00000020
+#define CPU_TIMER2_EN 0x00000010
+#define CPU_TIMER2_AUTO 0x00000020
+#define CPU_TIMER_WD_EN 0x00000100
+#define CPU_TIMER_WD_AUTO 0x00000200
/* 25MHz mode is Armada XP - specific */
#define CPU_TIMER_WD_25MHZ_EN 0x00000400
#define CPU_TIMER0_25MHZ_EN 0x00000800
Index: sys/arm/mv/timer.c
===================================================================
--- sys/arm/mv/timer.c
+++ sys/arm/mv/timer.c
@@ -60,6 +60,12 @@
#define MV_CLOCK_SRC get_tclk()
#endif
+#if defined(SOC_MV_ARMADA38X)
+#define WATCHDOG_TIMER 4
+#else
+#define WATCHDOG_TIMER 2
+#endif
+
struct mv_timer_softc {
struct resource * timer_res[2];
bus_space_tag_t timer_bst;
@@ -70,10 +76,16 @@
static struct resource_spec mv_timer_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
- { SYS_RES_IRQ, 0, RF_ACTIVE },
+ { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
{ -1, 0 }
};
+static struct ofw_compat_data mv_timer_compat[] = {
+ {"mrvl,timer", true},
+ {"marvell,armada-380-wdt", true},
+ {NULL, false}
+};
+
static struct mv_timer_softc *timer_softc = NULL;
static int timers_initialized = 0;
@@ -111,7 +123,7 @@
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
+ if (!ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data)
return (ENXIO);
device_set_desc(dev, "Marvell CPU Timer");
@@ -147,6 +159,17 @@
mv_watchdog_disable();
EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
+ if (ofw_bus_is_compatible(dev, "marvell,armada-380-wdt")) {
+ /* Don't set timers for wdt-only entry. */
+ device_printf(dev, "only watchdog attached\n");
+ return (0);
+ } else if (sc->timer_res[1] == NULL) {
+ /* Interrupt resource is neccessary for timers. */
+ device_printf(dev, "no interrupt resource\n");
+ bus_release_resources(dev, mv_timer_spec, sc->timer_res);
+ return (ENXIO);
+ }
+
if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
mv_hardclock, NULL, sc, &ihl) != 0) {
bus_release_resources(dev, mv_timer_spec, sc->timer_res);
@@ -306,6 +329,10 @@
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
+
+ val = read_cpu_misc(RSTOUTn_MASK);
+ val &= ~RSTOUTn_MASK_WD;
+ write_cpu_misc(RSTOUTn_MASK, val);
#else
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask |= IRQ_TIMER_WD_MASK;
@@ -317,9 +344,12 @@
#endif
val = mv_get_timer_control();
- val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
-#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
- val |= CPU_TIMER_WD_25MHZ_EN;
+#if defined(SOC_MV_ARMADA38X)
+ val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
+#elif defined(SOC_MV_ARMADAXP)
+ val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
+#else
+ val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
#endif
mv_set_timer_control(val);
}
@@ -333,13 +363,21 @@
#endif
val = mv_get_timer_control();
+#if defined(SOC_MV_ARMADA38X)
val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
+#else
+ val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
+#endif
mv_set_timer_control(val);
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
+
+ val = read_cpu_misc(RSTOUTn_MASK);
+ val |= RSTOUTn_MASK_WD;
+ write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
#else
val = read_cpu_ctrl(RSTOUTn_MASK);
val &= ~WD_RST_OUT_EN;
@@ -378,8 +416,7 @@
if (ticks > MAX_WATCHDOG_TICKS)
mv_watchdog_disable();
else {
- /* Timer 2 is the watchdog */
- mv_set_timer(2, ticks);
+ mv_set_timer(WATCHDOG_TIMER, ticks);
mv_watchdog_enable();
*error = 0;
}

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