BROKEN_aarch64= compilation fails: Creating OVM precompiled package... Segmentation fault (core dumped) # update to the current revision might help but it has C++ errors
BROKEN_armv6= compilation fails: Creating OVM precompiled package... libunwind: personality function returned unknown result 5
-BROKEN_i386= compilation fails: conversion function cannot be redeclared, see https://github.com/chipsalliance/Surelog/issues/3206
OPTIONS_DEFAULT= PYTHON TCMALLOC # should be the same TCMALLOC default as in cad/yosys, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog