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D19904.id56187.diff
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Index: usr.sbin/bhyve/pci_emul.c
===================================================================
--- usr.sbin/bhyve/pci_emul.c
+++ usr.sbin/bhyve/pci_emul.c
@@ -947,17 +947,30 @@
int err;
struct pciecap pciecap;
- if (type != PCIEM_TYPE_ROOT_PORT)
- return (-1);
+ bzero(&pciecap, sizeof(pciecap));
- bzero(&pciecap, sizeof(pciecap));
+ /*
+ * If the caller is requesting a PCIe capability for an endpoint, but
+ * the device appears to be a part of the root complex (i.e. bus 0),
+ * change the type to integrated endpoint.
+ */
+ if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) {
+ fprintf(stderr, "PCIe Capability for %02x:%02x.%u adjusted to "
+ "Integrated Endpoint\r\n", pi->pi_bus, pi->pi_slot,
+ pi->pi_func);
+ type = PCIEM_TYPE_ROOT_INT_EP;
+ }
pciecap.capid = PCIY_EXPRESS;
- pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
- pciecap.link_capabilities = 0x411; /* gen1, x1 */
- pciecap.link_status = 0x11; /* gen1, x1 */
+ pciecap.pcie_capabilities = PCIECAP_VERSION | type;
+
+ if (type != PCIEM_TYPE_ROOT_INT_EP) {
+ pciecap.link_capabilities = 0x411; /* gen1, x1 */
+ pciecap.link_status = 0x11; /* gen1, x1 */
+ }
err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
+
return (err);
}
Index: usr.sbin/bhyve/pci_nvme.c
===================================================================
--- usr.sbin/bhyve/pci_nvme.c
+++ usr.sbin/bhyve/pci_nvme.c
@@ -1925,6 +1925,12 @@
goto done;
}
+ error = pci_emul_add_pciecap(pi, PCIEM_TYPE_ENDPOINT);
+ if (error) {
+ WPRINTF(("%s pci add Express capability failed\r\n", __func__));
+ goto done;
+ }
+
pthread_mutex_init(&sc->mtx, NULL);
sem_init(&sc->iosemlock, 0, sc->ioslots);

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