D32247.id96077.diff
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D32247.id96077.diff
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	Index: sys/dev/nvme/nvme_ctrlr.c
	===================================================================
	--- sys/dev/nvme/nvme_ctrlr.c
	+++ sys/dev/nvme/nvme_ctrlr.c
	@@ -53,6 +53,12 @@
	static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
	struct nvme_async_event_request *aer);

	+static void
	+nvme_ctrlr_barrier(struct nvme_controller *ctrlr, int flags)
	+{
	+ bus_barrier(ctrlr->resource, 0, rman_get_size(ctrlr->resource), flags);
	+}
	+
	static void
	nvme_ctrlr_devctl_log(struct nvme_controller ctrlr, const char type, const char *msg, ...)
	{
	@@ -354,9 +360,7 @@
	return (err);

	nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr);
	- DELAY(5000);
	nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr);
	- DELAY(5000);

	/* acqs and asqs are 0-based. */
	qsize = ctrlr->adminq.num_entries - 1;
	@@ -365,7 +369,6 @@
	aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT;
	aqa \|= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT;
	nvme_mmio_write_4(ctrlr, aqa, aqa);
	- DELAY(5000);

	/* Initialization values for CC */
	cc = 0;
	@@ -379,6 +382,7 @@
	/* This evaluates to 0, which is according to spec. */
	cc \|= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT;

	+ nvme_ctrlr_barrier(ctrlr, BUS_SPACE_BARRIER_WRITE);
	nvme_mmio_write_4(ctrlr, cc, cc);

	return (nvme_ctrlr_wait_for_ready(ctrlr, 1));