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diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -464,6 +464,7 @@
#define PCIP_SERIALBUS_USB_OHCI 0x10
#define PCIP_SERIALBUS_USB_EHCI 0x20
#define PCIP_SERIALBUS_USB_XHCI 0x30
+#define PCIP_SERIALBUS_USB_USB4 0x40
#define PCIP_SERIALBUS_USB_DEVICE 0xfe
#define PCIS_SERIALBUS_FC 0x04
#define PCIS_SERIALBUS_SMBUS 0x05
diff --git a/sys/dev/thunderbolt/nhi.c b/sys/dev/thunderbolt/nhi.c
--- a/sys/dev/thunderbolt/nhi.c
+++ b/sys/dev/thunderbolt/nhi.c
@@ -1029,6 +1029,10 @@
* descriptor, and we know if we have reached the last descriptor that the
* hardware touched. This technique saves at least 2 MEMIO reads per
* interrupt.
+ *
+ * TODO Is this actually okay? What if we fail to get a completion interrupts
+ * but hardware updated CI anyway? I know this can happen, but is this an
+ * issue?
*/
void
nhi_intr(void *data)
@@ -1049,6 +1053,16 @@
if ((r = trkr->ring) == NULL)
return;
+ /*
+ * Need to read this necessarily to clear it; see 12.6.3.4.1. Disable
+ * ISR Auto-Clear must be set to 0.
+ *
+ * XXX This might not be necessary on all platforms. It is on Pink
+ * Sardine, but this was not being done previously so it might have
+ * been working without this on whatever Scott was testing on.
+ */
+ nhi_read_reg(sc, NHI_ISR0);
+
/*
* Process TX completions from the adapter. Only go through
* the ring once to prevent unbounded looping.
diff --git a/sys/dev/thunderbolt/nhi_pci.c b/sys/dev/thunderbolt/nhi_pci.c
--- a/sys/dev/thunderbolt/nhi_pci.c
+++ b/sys/dev/thunderbolt/nhi_pci.c
@@ -154,6 +154,12 @@
device_set_desc(dev, n->desc);
return (BUS_PROBE_DEFAULT);
}
+ if ((pci_get_class(dev) == PCIC_SERIALBUS)
+ && (pci_get_subclass(dev) == PCIS_SERIALBUS_USB)
+ && (pci_get_progif(dev) == PCIP_SERIALBUS_USB_USB4)) {
+ device_set_desc(dev, "Generic USB4 host controller");
+ return (BUS_PROBE_DEFAULT);
+ }
return (ENXIO);
}
diff --git a/sys/dev/thunderbolt/router.c b/sys/dev/thunderbolt/router.c
--- a/sys/dev/thunderbolt/router.c
+++ b/sys/dev/thunderbolt/router.c
@@ -389,6 +389,10 @@
break;
sc->inflight_cmd = NULL;
tb_debug(sc, DBG_ROUTER, "Config command timed out, retries=%d\n", retries);
+ /*
+ * TODO We might want to check if the done (DD) bit is set in
+ * the ring memory but we didn't get an interrupt.
+ */
}
if (cmd->ev != 0)
diff --git a/sys/dev/thunderbolt/tb_pcib.h b/sys/dev/thunderbolt/tb_pcib.h
--- a/sys/dev/thunderbolt/tb_pcib.h
+++ b/sys/dev/thunderbolt/tb_pcib.h
@@ -83,6 +83,8 @@
#define TB_DEV_AR_C_2C 0x15da
#define TB_DEV_ICL_0 0x8a1d
#define TB_DEV_ICL_1 0x8a21
+#define TB_DEV_PINK_SARDINE_0 0x14ef
+#define TB_DEV_PINK_SARDINE_1 0x14ea
#define TB_PCIB_VSEC(dev) ((struct tb_pcib_softc *)(device_get_softc(dev)))->vsec;
#define TB_DESC_MAX 80
diff --git a/sys/dev/thunderbolt/tb_pcib.c b/sys/dev/thunderbolt/tb_pcib.c
--- a/sys/dev/thunderbolt/tb_pcib.c
+++ b/sys/dev/thunderbolt/tb_pcib.c
@@ -102,6 +102,10 @@
"Thunderbolt 3 PCI-PCI Bridge (IceLake)" },
{ VENDOR_INTEL, TB_DEV_ICL_1, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_ICL,
"Thunderbolt 3 PCI-PCI Bridge (IceLake)" },
+ { VENDOR_AMD, TB_DEV_PINK_SARDINE_0, 0xffff, 0xffff,
+ TB_GEN_USB4|TB_HWIF_USB4, "USB4 PCI-PCI Bridge (Pink sardine)" },
+ { VENDOR_AMD, TB_DEV_PINK_SARDINE_1, 0xffff, 0xffff,
+ TB_GEN_USB4|TB_HWIF_USB4, "USB4 PCI-PCI Bridge (Pink sardine)" },
{ 0, 0, 0, 0, 0, NULL }
};

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