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Index: sys/conf/files.powerpc
===================================================================
--- sys/conf/files.powerpc
+++ sys/conf/files.powerpc
@@ -137,6 +137,7 @@
powerpc/mpc85xx/mpc85xx_gpio.c optional mpc85xx gpio
powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx
powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx
+powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx
powerpc/ofw/ofw_machdep.c standard
powerpc/ofw/ofw_pci.c optional pci
powerpc/ofw/ofw_pcibus.c optional pci
Index: sys/dev/pci/pci_pci.c
===================================================================
--- sys/dev/pci/pci_pci.c
+++ sys/dev/pci/pci_pci.c
@@ -442,16 +442,7 @@
dev = sc->dev;
if (pci_clear_pcib) {
- pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
- pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
- pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
- pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
- pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
- pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
- pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
- pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
- pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
- pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
+ pcib_bridge_init(dev);
}
/* Determine if the I/O port window is implemented. */
@@ -1131,6 +1122,21 @@
return (bus_generic_resume(dev));
}
+void
+pcib_bridge_init(device_t dev)
+{
+ pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
+ pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
+ pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
+ pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
+ pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
+ pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
+ pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
+ pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
+ pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
+ pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
+}
+
int
pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
Index: sys/dev/pci/pcib_private.h
===================================================================
--- sys/dev/pci/pcib_private.h
+++ sys/dev/pci/pcib_private.h
@@ -148,6 +148,7 @@
#endif
int pcib_attach(device_t dev);
void pcib_attach_common(device_t dev);
+void pcib_bridge_init(device_t dev);
#ifdef NEW_PCIB
const char *pcib_child_name(device_t child);
#endif
Index: sys/powerpc/mpc85xx/pci_mpc85xx.c
===================================================================
--- sys/powerpc/mpc85xx/pci_mpc85xx.c
+++ sys/powerpc/mpc85xx/pci_mpc85xx.c
@@ -265,6 +265,19 @@
*/
sc->sc_busnr = 0;
maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
+ ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
+#if 0
+ if (ltssm >= LTSSM_STAT_L0) {
+ cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECBUS_1, 1);
+ if (cfgreg == fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_PRIBUS_1, 1)) {
+ fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECBUS_1, cfgreg + 1, 1);
+ printf("Odd, SECBUS is same as PRIBUS\n");
+ }
+ cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SUBBUS_1, 1);
+ if (cfgreg == fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_PRIBUS_1, 1))
+ fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SUBBUS_1, cfgreg + 1, 1);
+ }
+#endif
fsl_pcib_init(sc, sc->sc_busnr, maxslot);
if (sc->sc_pcie) {
@@ -570,10 +583,15 @@
subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
func, PCIR_SUBCLASS, 1);
+ /*
+ * The PCI Root Complex comes up as a Processor/PowerPC,
+ * but is a bridge.
+ */
/* Allow only proper PCI-PCI briges */
- if (class != PCIC_BRIDGE)
+ if (class != PCIC_BRIDGE && class != PCIC_PROCESSOR)
continue;
- if (subclass != PCIS_BRIDGE_PCI)
+ if (subclass != PCIS_BRIDGE_PCI &&
+ subclass != PCIS_PROCESSOR_POWERPC)
continue;
secbus++;
@@ -825,4 +843,3 @@
return (0);
}
-
Index: sys/powerpc/mpc85xx/pci_mpc85xx_pcib.c
===================================================================
--- /dev/null
+++ sys/powerpc/mpc85xx/pci_mpc85xx_pcib.c
@@ -0,0 +1,104 @@
+/*-
+ * Copyright 2015 Justin Hibbits
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/ktr.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/queue.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/endian.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcib_private.h>
+
+#include "pcib_if.h"
+
+static int
+fsl_pcib_rc_probe(device_t dev)
+{
+ printf("Probe called\n");
+ if (pci_get_vendor(dev) != 0x1957)
+ return (ENXIO);
+ if (pci_get_progif(dev) != 0)
+ return (ENXIO);
+ if (pci_get_class(dev) != PCIC_PROCESSOR)
+ return (ENXIO);
+ if (pci_get_subclass(dev) != PCIS_PROCESSOR_POWERPC)
+ return (ENXIO);
+
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+fsl_pcib_rc_attach(device_t dev)
+{
+ struct pcib_softc *sc;
+ device_t child;
+
+ pcib_bridge_init(dev);
+ pcib_attach_common(dev);
+
+ sc = device_get_softc(dev);
+ if (sc->bus.sec != 0) {
+ child = device_add_child(dev, "pci", -1);
+ if (child != NULL)
+ return (bus_generic_attach(dev));
+ }
+
+ return (0);
+}
+
+static device_method_t fsl_pcib_rc_methods[] = {
+ DEVMETHOD(device_probe, fsl_pcib_rc_probe),
+ DEVMETHOD(device_attach, fsl_pcib_rc_attach),
+ DEVMETHOD_END
+};
+
+static devclass_t fsl_pcib_rc_devclass;
+DEFINE_CLASS_1(pcib, fsl_pcib_rc_driver, fsl_pcib_rc_methods,
+ sizeof(struct pcib_softc), pcib_driver);
+DRIVER_MODULE(rcpcib, pci, fsl_pcib_rc_driver, fsl_pcib_rc_devclass, 0, 0);
+

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