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Index: sys/dev/bhnd/cores/mips/mipscore.c
===================================================================
--- /dev/null
+++ sys/dev/bhnd/cores/mips/mipscore.c
@@ -0,0 +1,135 @@
+/*-
+ * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ * redistribution must be conditioned upon including a substantially
+ * similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/errno.h>
+#include <sys/rman.h>
+#include <sys/stddef.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhndvar.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include "mipscorevar.h"
+
+static const struct resource_spec mipscore_rspec[MIPSCORE_MAX_RSPEC] = {
+ { SYS_RES_MEMORY, 0, RF_ACTIVE },
+ { -1, -1, 0 }
+};
+
+struct bhnd_device mipscore_match[] = {
+ MIPS_DEVICE(MIPS, "BHND MIPS processor", NULL),
+ MIPS_DEVICE(MIPS33, "BHND MIPS3302 processor", NULL),
+ MIPS_DEVICE(MIPS74K, "BHND MIPS74K processor", NULL),
+ BHND_DEVICE_END
+};
+
+static int mipscore_probe(device_t dev) {
+
+ const struct bhnd_device *id;
+
+ id = bhnd_device_lookup(dev, mipscore_match, sizeof(mipscore_match[0]));
+ if (id == NULL)
+ return (ENXIO);
+
+ bhnd_set_default_core_desc(dev);
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int mipscore_attach(device_t dev) {
+ struct mipscore_softc *sc;
+ struct resource *res;
+ struct mipscore_regs *regs;
+
+ sc = device_get_softc(dev);
+ uint32_t devid = bhnd_get_device(dev);
+
+ sc->devid = devid;
+ sc->dev = dev;
+
+ /* Allocate bus resources */
+ memcpy(sc->rspec, mipscore_rspec, sizeof(sc->rspec));
+ int error = bhnd_alloc_resources(dev, sc->rspec, sc->res);
+ if(error)
+ return (error);
+
+ res = sc->res[0]->res;
+
+ if(!res)
+ return (ENXIO);
+
+
+ bus_space_handle_t hdl = rman_get_bushandle(res);
+ bus_space_tag_t tag = rman_get_bustag(res);
+
+ regs = malloc(sizeof(struct mipscore_regs), M_BHND, M_NOWAIT);
+ if (!regs) {
+ error = ENXIO;
+ goto cleanup;
+ }
+
+ if (devid == BHND_COREID_MIPS74K) {
+ bus_space_read_multi_4(tag, hdl, 0, (uint32_t*)regs,
+ sizeof(struct mipscore_regs)/ sizeof(uint32_t));
+
+ regs->intmask[5] = (1 << 31);
+ /* Use intmask5 register to route the timer interrupt */
+ bus_space_write_4(tag, hdl,
+ offsetof(struct mipscore_regs, intmask[5]),
+ regs->intmask[5]);
+ }
+cleanup:
+ if (!regs)
+ free(regs, M_BHND);
+ return error;
+}
+
+static device_method_t mipscore_methods[] = {
+ DEVMETHOD(device_probe, mipscore_probe),
+ DEVMETHOD(device_attach, mipscore_attach),
+ DEVMETHOD_END
+};
+
+devclass_t bhnd_mipscore_devclass;
+
+DEFINE_CLASS_0(bhnd_mipscore, mipscore_driver, mipscore_methods,
+ sizeof(struct mipscore_softc));
+DRIVER_MODULE(bhnd_mipscore, bhnd, mipscore_driver, bhnd_mipscore_devclass,
+ 0, 0);
+MODULE_VERSION(bhnd_mipscore, 1);
Index: sys/dev/bhnd/cores/mips/mipscorevar.h
===================================================================
--- /dev/null
+++ sys/dev/bhnd/cores/mips/mipscorevar.h
@@ -0,0 +1,55 @@
+/*-
+ * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ * redistribution must be conditioned upon including a substantially
+ * similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#pragma once
+
+#define MIPSCORE_MAX_RSPEC 2
+
+struct mipscore_softc {
+ device_t dev; /* CPU device */
+ uint32_t devid;
+ struct resource_spec rspec[MIPSCORE_MAX_RSPEC];
+ struct bhnd_resource *res[MIPSCORE_MAX_RSPEC];
+};
+
+struct mipscore_regs{
+ uint32_t corecontrol;
+ uint32_t exceptionbase;
+ uint32_t PAD1[1];
+ uint32_t biststatus;
+ uint32_t intstatus;
+ uint32_t intmask[6];
+ uint32_t nmimask;
+ uint32_t PAD2[4];
+ uint32_t gpioselect;
+ uint32_t gpiooutput;
+ uint32_t gpioenable;
+ uint32_t PA3[101];
+ uint32_t clkcontrolstatus;
+} ;

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