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Index: head/sys/mips/include/atomic.h
===================================================================
--- head/sys/mips/include/atomic.h
+++ head/sys/mips/include/atomic.h
@@ -341,24 +341,6 @@
ATOMIC_STORE_LOAD(32)
ATOMIC_STORE_LOAD(64)
-#if !defined(__mips_n64) && !defined(__mips_n32)
-void atomic_store_64(__volatile uint64_t *, uint64_t);
-uint64_t atomic_load_64(__volatile uint64_t *);
-#elif defined (__mips_n32)
-static __inline void
-atomic_store_64(__volatile uint64_t *p, uint64_t v)
-{
- *p = v;
-}
-
-static __inline uint64_t
-atomic_load_64(__volatile uint64_t *p)
-{
- return (*p);
-}
-/* #else atomic_common.h definitions of atomic_load/store_64 are used */
-#endif
-
#undef ATOMIC_STORE_LOAD
/*
Index: head/sys/mips/mips/db_interface.c
===================================================================
--- head/sys/mips/mips/db_interface.c
+++ head/sys/mips/mips/db_interface.c
@@ -152,6 +152,7 @@
/*
* 'addr' could be a memory-mapped I/O address. Try to
* do atomic load/store in unit of size requested.
+ * size == 8 is only atomic on 64bit or n32 kernel.
*/
if ((size == 2 || size == 4 || size == 8) &&
((addr & (size -1)) == 0) &&
@@ -164,8 +165,7 @@
*(uint32_t *)data = *(uint32_t *)addr;
break;
case 8:
- *(uint64_t *)data = atomic_load_64(
- (void *)addr);
+ *(uint64_t *)data = *(uint64_t *)addr;
break;
}
} else {
@@ -195,6 +195,7 @@
/*
* 'addr' could be a memory-mapped I/O address. Try to
* do atomic load/store in unit of size requested.
+ * size == 8 is only atomic on 64bit or n32 kernel.
*/
if ((size == 2 || size == 4 || size == 8) &&
((addr & (size -1)) == 0) &&
@@ -207,8 +208,7 @@
*(uint32_t *)addr = *(uint32_t *)data;
break;
case 8:
- atomic_store_64((uint64_t *)addr,
- *(uint64_t *)data);
+ *(uint64_t *)addr = *(uint64_t *)data;
break;
}
} else {
Index: head/sys/mips/mips/support.S
===================================================================
--- head/sys/mips/mips/support.S
+++ head/sys/mips/mips/support.S
@@ -839,74 +839,7 @@
nop
END(atomic_subtract_8)
-/*
- * atomic 64-bit register read/write assembly language support routines.
- */
-
.set noreorder # Noreorder is default style!
-
-#if !defined(__mips_n64) && !defined(__mips_n32)
- /*
- * I don't know if these routines have the right number of
- * NOPs in it for all processors. XXX
- *
- * Maybe it would be better to just leave this undefined in that case.
- *
- * XXX These routines are not safe in the case of a TLB miss on a1 or
- * a0 unless the trapframe is 64-bit, which it just isn't with O32.
- * If we take any exception, not just an interrupt, the upper
- * 32-bits will be clobbered. Use only N32 and N64 kernels if you
- * want to use 64-bit registers while interrupts are enabled or
- * with memory operations. Since this isn't even using load-linked
- * and store-conditional, perhaps it should just use two registers
- * instead, as is right and good with the O32 ABI.
- */
-LEAF(atomic_store_64)
- mfc0 t1, MIPS_COP_0_STATUS
- and t2, t1, ~MIPS_SR_INT_IE
- mtc0 t2, MIPS_COP_0_STATUS
- nop
- nop
- nop
- nop
- ld t0, (a1)
- nop
- nop
- sd t0, (a0)
- nop
- nop
- mtc0 t1,MIPS_COP_0_STATUS
- nop
- nop
- nop
- nop
- j ra
- nop
-END(atomic_store_64)
-
-LEAF(atomic_load_64)
- mfc0 t1, MIPS_COP_0_STATUS
- and t2, t1, ~MIPS_SR_INT_IE
- mtc0 t2, MIPS_COP_0_STATUS
- nop
- nop
- nop
- nop
- ld t0, (a0)
- nop
- nop
- sd t0, (a1)
- nop
- nop
- mtc0 t1,MIPS_COP_0_STATUS
- nop
- nop
- nop
- nop
- j ra
- nop
-END(atomic_load_64)
-#endif
#if defined(DDB) || defined(DEBUG)

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