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diff --git a/sys/arm/mv/mv_common.c b/sys/arm/mv/mv_common.c
--- a/sys/arm/mv/mv_common.c
+++ b/sys/arm/mv/mv_common.c
@@ -76,14 +76,11 @@
static enum soc_family soc_family;
-static int mv_win_cesa_attr_armv5(int eng_sel);
static int mv_win_cesa_attr_armada38x(int eng_sel);
static int mv_win_cesa_attr_armadaxp(int eng_sel);
-uint32_t read_cpu_ctrl_armv5(uint32_t reg);
uint32_t read_cpu_ctrl_armv7(uint32_t reg);
-void write_cpu_ctrl_armv5(uint32_t reg, uint32_t val);
void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val);
static int win_eth_can_remap(int i);
@@ -127,41 +124,29 @@
static void decode_win_pcie_dump(u_long);
static uint32_t win_cpu_cr_read(int);
-static uint32_t win_cpu_armv5_cr_read(int);
static uint32_t win_cpu_armv7_cr_read(int);
static uint32_t win_cpu_br_read(int);
-static uint32_t win_cpu_armv5_br_read(int);
static uint32_t win_cpu_armv7_br_read(int);
static uint32_t win_cpu_remap_l_read(int);
-static uint32_t win_cpu_armv5_remap_l_read(int);
static uint32_t win_cpu_armv7_remap_l_read(int);
static uint32_t win_cpu_remap_h_read(int);
-static uint32_t win_cpu_armv5_remap_h_read(int);
static uint32_t win_cpu_armv7_remap_h_read(int);
static void win_cpu_cr_write(int, uint32_t);
-static void win_cpu_armv5_cr_write(int, uint32_t);
static void win_cpu_armv7_cr_write(int, uint32_t);
static void win_cpu_br_write(int, uint32_t);
-static void win_cpu_armv5_br_write(int, uint32_t);
static void win_cpu_armv7_br_write(int, uint32_t);
static void win_cpu_remap_l_write(int, uint32_t);
-static void win_cpu_armv5_remap_l_write(int, uint32_t);
static void win_cpu_armv7_remap_l_write(int, uint32_t);
static void win_cpu_remap_h_write(int, uint32_t);
-static void win_cpu_armv5_remap_h_write(int, uint32_t);
static void win_cpu_armv7_remap_h_write(int, uint32_t);
static uint32_t ddr_br_read(int);
static uint32_t ddr_sz_read(int);
-static uint32_t ddr_armv5_br_read(int);
-static uint32_t ddr_armv5_sz_read(int);
static uint32_t ddr_armv7_br_read(int);
static uint32_t ddr_armv7_sz_read(int);
static void ddr_br_write(int, uint32_t);
static void ddr_sz_write(int, uint32_t);
-static void ddr_armv5_br_write(int, uint32_t);
-static void ddr_armv5_sz_write(int, uint32_t);
static void ddr_armv7_br_write(int, uint32_t);
static void ddr_armv7_sz_write(int, uint32_t);
@@ -190,16 +175,6 @@
typedef void (*dump_win_t)(u_long);
typedef int (*valid_t)(void);
-/*
- * The power status of device feature is only supported on
- * Kirkwood and Discovery SoCs.
- */
-#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
-#define SOC_MV_POWER_STAT_SUPPORTED 1
-#else
-#define SOC_MV_POWER_STAT_SUPPORTED 0
-#endif
-
struct soc_node_spec {
const char *compat;
decode_win_setup_t decode_handler;
@@ -306,27 +281,6 @@
&get_tclk_armadaxp,
&get_cpu_freq_armadaxp,
},
- {
- &read_cpu_ctrl_armv5,
- &write_cpu_ctrl_armv5,
- &win_cpu_armv5_cr_read,
- &win_cpu_armv5_br_read,
- &win_cpu_armv5_remap_l_read,
- &win_cpu_armv5_remap_h_read,
- &win_cpu_armv5_cr_write,
- &win_cpu_armv5_br_write,
- &win_cpu_armv5_remap_l_write,
- &win_cpu_armv5_remap_h_write,
- MV_WIN_CPU_MAX,
- &mv_win_cesa_attr_armv5,
- MV_WIN_CESA_TARGET,
- &ddr_armv5_br_read,
- &ddr_armv5_sz_read,
- &ddr_armv5_br_write,
- &ddr_armv5_sz_write,
- NULL,
- NULL,
- },
};
struct fdt_pm_mask_entry {
@@ -345,16 +299,6 @@
{ NULL, 0 }
};
-static __inline int
-pm_is_disabled(uint32_t mask)
-{
-#if SOC_MV_POWER_STAT_SUPPORTED
- return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
-#else
- return (0);
-#endif
-}
-
/*
* Disable device using power management register.
* 1 - Device Power On
@@ -389,12 +333,6 @@
* machines.
*/
-static int mv_win_cesa_attr_armv5(int eng_sel)
-{
-
- return MV_WIN_CESA_ATTR(eng_sel);
-}
-
static int mv_win_cesa_attr_armada38x(int eng_sel)
{
@@ -426,21 +364,6 @@
soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_38X];
soc_family = MV_SOC_ARMADA_38X;
break;
- case MV_DEV_88F5181:
- case MV_DEV_88F5182:
- case MV_DEV_88F5281:
- case MV_DEV_88F6281:
- case MV_DEV_88RC8180:
- case MV_DEV_88RC9480:
- case MV_DEV_88RC9580:
- case MV_DEV_88F6781:
- case MV_DEV_88F6282:
- case MV_DEV_MV78100_Z0:
- case MV_DEV_MV78100:
- case MV_DEV_MV78160:
- soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMV5];
- soc_family = MV_SOC_ARMV5;
- break;
default:
soc_family = MV_SOC_UNSUPPORTED;
return (MV_SOC_UNSUPPORTED);
@@ -457,15 +380,10 @@
#ifdef DIAGNOSTIC
uint32_t reg;
- reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
- printf("Power Management Register: 0%x\n", reg);
-
+ reg = CPU_PM_CTRL_ALL;
reg &= ~mask;
soc_power_ctrl_set(reg);
printf("Device %x is disabled\n", mask);
-
- reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
- printf("Power Management Register: 0%x\n", reg);
#endif
}
@@ -503,16 +421,6 @@
compat = ofw_bus_node_is_compatible(node,
fdt_pm_mask_table[i].compat);
-#if defined(SOC_MV_KIRKWOOD)
- if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
- dev_mask |= (1 << i);
- ena = 0;
- break;
- } else if (compat) {
- dev_mask |= (1 << i);
- break;
- }
-#else
if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
dev_mask |= (1 << i);
ena = 0;
@@ -521,7 +429,6 @@
dev_mask |= (1 << i);
break;
}
-#endif
}
return (ena);
@@ -536,13 +443,6 @@
return (-1);
}
-uint32_t
-read_cpu_ctrl_armv5(uint32_t reg)
-{
-
- return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
-}
-
uint32_t
read_cpu_ctrl_armv7(uint32_t reg)
{
@@ -558,13 +458,6 @@
soc_decode_win_spec->write_cpu_ctrl(reg, val);
}
-void
-write_cpu_ctrl_armv5(uint32_t reg, uint32_t val)
-{
-
- bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
-}
-
void
write_cpu_ctrl_armv7(uint32_t reg, uint32_t val)
{
@@ -600,64 +493,16 @@
bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
}
-uint32_t
-cpu_extra_feat(void)
-{
- uint32_t dev, rev;
- uint32_t ef = 0;
-
- soc_id(&dev, &rev);
-
- switch (dev) {
- case MV_DEV_88F6281:
- case MV_DEV_88F6282:
- case MV_DEV_88RC8180:
- case MV_DEV_MV78100_Z0:
- case MV_DEV_MV78100:
- __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
- break;
- case MV_DEV_88F5182:
- case MV_DEV_88F5281:
- __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
- break;
- default:
- if (bootverbose)
- printf("This ARM Core does not support any extra features\n");
- }
-
- return (ef);
-}
-
-/*
- * Get the power status of device. This feature is only supported on
- * Kirkwood and Discovery SoCs.
- */
-uint32_t
-soc_power_ctrl_get(uint32_t mask)
-{
-
-#if SOC_MV_POWER_STAT_SUPPORTED
- if (mask != CPU_PM_CTRL_NONE)
- mask &= read_cpu_ctrl(CPU_PM_CTRL);
-
- return (mask);
-#else
- return (mask);
-#endif
-}
-
/*
- * Set the power status of device. This feature is only supported on
+ * Set the power status of device. This feature was only supported on
* Kirkwood and Discovery SoCs.
*/
void
soc_power_ctrl_set(uint32_t mask)
{
-#if !defined(SOC_MV_ORION)
if (mask != CPU_PM_CTRL_NONE)
write_cpu_ctrl(CPU_PM_CTRL, mask);
-#endif
}
void
@@ -686,7 +531,7 @@
static void
soc_identify(uint32_t d, uint32_t r)
{
- uint32_t size, mode, freq;
+ uint32_t mode, freq;
const char *dev;
const char *rev;
@@ -696,55 +541,6 @@
rev = "";
switch (d) {
- case MV_DEV_88F5181:
- dev = "Marvell 88F5181";
- if (r == 3)
- rev = "B1";
- break;
- case MV_DEV_88F5182:
- dev = "Marvell 88F5182";
- if (r == 2)
- rev = "A2";
- break;
- case MV_DEV_88F5281:
- dev = "Marvell 88F5281";
- if (r == 4)
- rev = "D0";
- else if (r == 5)
- rev = "D1";
- else if (r == 6)
- rev = "D2";
- break;
- case MV_DEV_88F6281:
- dev = "Marvell 88F6281";
- if (r == 0)
- rev = "Z0";
- else if (r == 2)
- rev = "A0";
- else if (r == 3)
- rev = "A1";
- break;
- case MV_DEV_88RC8180:
- dev = "Marvell 88RC8180";
- break;
- case MV_DEV_88RC9480:
- dev = "Marvell 88RC9480";
- break;
- case MV_DEV_88RC9580:
- dev = "Marvell 88RC9580";
- break;
- case MV_DEV_88F6781:
- dev = "Marvell 88F6781";
- if (r == 2)
- rev = "Y0";
- break;
- case MV_DEV_88F6282:
- dev = "Marvell 88F6282";
- if (r == 0)
- rev = "A0";
- else if (r == 1)
- rev = "A1";
- break;
case MV_DEV_88F6828:
dev = "Marvell 88F6828";
break;
@@ -754,15 +550,6 @@
case MV_DEV_88F6810:
dev = "Marvell 88F6810";
break;
- case MV_DEV_MV78100_Z0:
- dev = "Marvell MV78100 Z0";
- break;
- case MV_DEV_MV78100:
- dev = "Marvell MV78100";
- break;
- case MV_DEV_MV78160:
- dev = "Marvell MV78160";
- break;
case MV_DEV_MV78260:
dev = "Marvell MV78260";
break;
@@ -787,25 +574,6 @@
printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
(mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
(mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
-
- switch (d) {
- case MV_DEV_88F6281:
- case MV_DEV_88F6282:
- mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
- printf(" 256KB 4-way set-associative %s unified L2 cache\n",
- mode ? "write-through" : "write-back");
- break;
- case MV_DEV_MV78100:
- mode = read_cpu_ctrl(CPU_CONTROL);
- size = mode & CPU_CONTROL_L2_SIZE;
- mode = mode & CPU_CONTROL_L2_MODE;
- printf(" %s set-associative %s unified L2 cache\n",
- size ? "256KB 4-way" : "512KB 8-way",
- mode ? "write-through" : "write-back");
- break;
- default:
- break;
- }
}
#ifdef KDB
@@ -857,14 +625,6 @@
/**************************************************************************
* Decode windows registers accessors
**************************************************************************/
-WIN_REG_IDX_RD(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_RD(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_RD(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_RD(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_WR(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_WR(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_WR(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE)
-WIN_REG_IDX_WR(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE)
@@ -1000,11 +760,6 @@
WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE);
#ifndef SOC_MV_DOVE
-WIN_REG_IDX_RD(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
-WIN_REG_IDX_RD(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
-WIN_REG_IDX_WR(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
-WIN_REG_IDX_WR(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
-
WIN_REG_IDX_RD(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7)
WIN_REG_IDX_RD(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7)
WIN_REG_IDX_WR(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7)
@@ -1116,17 +871,9 @@
soc_id(&dev, &rev);
/* Depending on the SoC certain windows have remap capability */
- if ((dev == MV_DEV_88F5182 && i < 2) ||
- (dev == MV_DEV_88F5281 && i < 4) ||
- (dev == MV_DEV_88F6281 && i < 4) ||
- (dev == MV_DEV_88F6282 && i < 4) ||
- (dev == MV_DEV_88F6828 && i < 20) ||
+ if ((dev == MV_DEV_88F6828 && i < 20) ||
(dev == MV_DEV_88F6820 && i < 20) ||
- (dev == MV_DEV_88F6810 && i < 20) ||
- (dev == MV_DEV_88RC8180 && i < 2) ||
- (dev == MV_DEV_88F6781 && i < 4) ||
- (dev == MV_DEV_MV78100_Z0 && i < 8) ||
- ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
+ (dev == MV_DEV_88F6810 && i < 20))
return (1);
return (0);
@@ -1338,13 +1085,7 @@
uint32_t
ddr_attr(int i)
{
- uint32_t dev, rev, attr;
-
- soc_id(&dev, &rev);
- if (dev == MV_DEV_88RC8180)
- return ((ddr_sz_read(i) & 0xf0) >> 4);
- if (dev == MV_DEV_88F6781)
- return (0);
+ uint32_t attr;
attr = (i == 0 ? 0xe :
(i == 1 ? 0xd :
@@ -1356,27 +1097,6 @@
return (attr);
}
-uint32_t
-ddr_target(int i)
-{
- uint32_t dev, rev;
-
- soc_id(&dev, &rev);
- if (dev == MV_DEV_88RC8180) {
- i = (ddr_sz_read(i) & 0xf0) >> 4;
- return (i == 0xe ? 0xc :
- (i == 0xd ? 0xd :
- (i == 0xb ? 0xe :
- (i == 0x7 ? 0xf : 0xc))));
- }
-
- /*
- * On SOCs other than 88RC8180 Mbus unit ID for
- * DDR SDRAM controller is always 0x0.
- */
- return (0);
-}
-
/**************************************************************************
* CESA windows routines
**************************************************************************/
@@ -1432,7 +1152,6 @@
cr = (((size - 1) & 0xffff0000) |
(ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
- (ddr_target(i) << IO_WIN_TGT_SHIFT) |
IO_WIN_ENA_MASK);
/* Set the first free CESA window */
@@ -1477,9 +1196,6 @@
{
int i;
- if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1)))
- return;
-
for (i = 0; i < MV_WIN_USB_MAX; i++)
printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
win_usb_cr_read(base, i), win_usb_br_read(base, i));
@@ -1494,9 +1210,6 @@
uint32_t br, cr;
int i, j;
- if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
- return;
-
usb_port++;
for (i = 0; i < MV_WIN_USB_MAX; i++) {
@@ -1513,8 +1226,7 @@
* burst limit field in the ctrl reg
*/
cr = (((ddr_size(i) - 1) & 0xffff0000) |
- (ddr_attr(i) << 8) |
- (ddr_target(i) << 4) | 1);
+ (ddr_attr(i) << 8) | 1);
/* Set the first free USB window */
for (j = 0; j < MV_WIN_USB_MAX; j++) {
@@ -1570,7 +1282,6 @@
cr = (((ddr_size(i) - 1) &
(IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
(ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
- (ddr_target(i) << IO_WIN_TGT_SHIFT) |
IO_WIN_ENA_MASK);
/* Set the first free USB3.0 window */
@@ -1639,9 +1350,6 @@
{
int i;
- if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1)))
- return;
-
for (i = 0; i < MV_WIN_ETH_MAX; i++) {
printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
win_eth_br_read(base, i),
@@ -1658,17 +1366,12 @@
win_eth_epap_read(base));
}
-#define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n)
-
static void
decode_win_eth_setup(u_long base)
{
uint32_t br, sz;
int i, j;
- if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port)))
- return;
-
eth_port++;
/* Disable, clear and revoke protection for all ETH windows */
@@ -1684,7 +1387,7 @@
/* Only access to active DRAM banks is required */
for (i = 0; i < MV_WIN_DDR_MAX; i++)
if (ddr_is_active(i)) {
- br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
+ br = ddr_base(i) | (ddr_attr(i) << 8);
sz = ((ddr_size(i) - 1) & 0xffff0000);
/* Set the first free ETH window */
@@ -1782,7 +1485,7 @@
/* Map DDR to BAR 1 */
cr = (ddr_size(i) - 1) & 0xffff0000;
size += ddr_size(i) & 0xffff0000;
- cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
+ cr |= (ddr_attr(i) << 8) | 1;
br = ddr_base(i);
if (br < ddrbase)
ddrbase = br;
@@ -1822,228 +1525,6 @@
/**************************************************************************
* IDMA windows routines
**************************************************************************/
-#if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
-static int
-idma_bare_read(u_long base, int i)
-{
- uint32_t v;
-
- v = win_idma_bare_read(base);
- v &= (1 << i);
-
- return (v >> i);
-}
-
-static void
-idma_bare_write(u_long base, int i, int val)
-{
- uint32_t v;
-
- v = win_idma_bare_read(base);
- v &= ~(1 << i);
- v |= (val << i);
- win_idma_bare_write(base, v);
-}
-
-/*
- * Sets channel protection 'val' for window 'w' on channel 'c'
- */
-static void
-idma_cap_write(u_long base, int c, int w, int val)
-{
- uint32_t v;
-
- v = win_idma_cap_read(base, c);
- v &= ~(0x3 << (w * 2));
- v |= (val << (w * 2));
- win_idma_cap_write(base, c, v);
-}
-
-/*
- * Set protection 'val' on all channels for window 'w'
- */
-static void
-idma_set_prot(u_long base, int w, int val)
-{
- int c;
-
- for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
- idma_cap_write(base, c, w, val);
-}
-
-static int
-win_idma_can_remap(int i)
-{
-
- /* IDMA decode windows 0-3 have remap capability */
- if (i < 4)
- return (1);
-
- return (0);
-}
-
-void
-decode_win_idma_setup(u_long base)
-{
- uint32_t br, sz;
- int i, j;
-
- if (pm_is_disabled(CPU_PM_CTRL_IDMA))
- return;
- /*
- * Disable and clear all IDMA windows, revoke protection for all channels
- */
- for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
- idma_bare_write(base, i, 1);
- win_idma_br_write(base, i, 0);
- win_idma_sz_write(base, i, 0);
- if (win_idma_can_remap(i) == 1)
- win_idma_har_write(base, i, 0);
- }
- for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
- win_idma_cap_write(base, i, 0);
-
- /*
- * Set up access to all active DRAM banks
- */
- for (i = 0; i < MV_WIN_DDR_MAX; i++)
- if (ddr_is_active(i)) {
- br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
- sz = ((ddr_size(i) - 1) & 0xffff0000);
-
- /* Place DDR entries in non-remapped windows */
- for (j = 0; j < MV_WIN_IDMA_MAX; j++)
- if (win_idma_can_remap(j) != 1 &&
- idma_bare_read(base, j) == 1) {
- /* Configure window */
- win_idma_br_write(base, j, br);
- win_idma_sz_write(base, j, sz);
-
- /* Set protection RW on all channels */
- idma_set_prot(base, j, 0x3);
-
- /* Enable window */
- idma_bare_write(base, j, 0);
- break;
- }
- }
-
- /*
- * Remaining targets -- from statically defined table
- */
- for (i = 0; i < idma_wins_no; i++)
- if (idma_wins[i].target > 0) {
- br = (idma_wins[i].base & 0xffff0000) |
- (idma_wins[i].attr << 8) | idma_wins[i].target;
- sz = ((idma_wins[i].size - 1) & 0xffff0000);
-
- /* Set the first free IDMA window */
- for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
- if (idma_bare_read(base, j) == 0)
- continue;
-
- /* Configure window */
- win_idma_br_write(base, j, br);
- win_idma_sz_write(base, j, sz);
- if (win_idma_can_remap(j) &&
- idma_wins[j].remap >= 0)
- win_idma_har_write(base, j,
- idma_wins[j].remap);
-
- /* Set protection RW on all channels */
- idma_set_prot(base, j, 0x3);
-
- /* Enable window */
- idma_bare_write(base, j, 0);
- break;
- }
- }
-}
-
-int
-decode_win_idma_valid(void)
-{
- const struct decode_win *wintab;
- int c, i, j, rv;
- uint32_t b, e, s;
-
- if (idma_wins_no > MV_WIN_IDMA_MAX) {
- printf("IDMA windows: too many entries: %d\n", idma_wins_no);
- return (0);
- }
- for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
- if (ddr_is_active(i))
- c++;
-
- if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
- printf("IDMA windows: too many entries: %d, available: %d\n",
- idma_wins_no, MV_WIN_IDMA_MAX - c);
- return (0);
- }
-
- wintab = idma_wins;
- rv = 1;
- for (i = 0; i < idma_wins_no; i++, wintab++) {
- if (wintab->target == 0) {
- printf("IDMA window#%d: DDR target window is not "
- "supposed to be reprogrammed!\n", i);
- rv = 0;
- }
-
- if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
- printf("IDMA window#%d: not capable of remapping, but "
- "val 0x%08x defined\n", i, wintab->remap);
- rv = 0;
- }
-
- s = wintab->size;
- b = wintab->base;
- e = b + s - 1;
- if (s > (0xFFFFFFFF - b + 1)) {
- /* XXX this boundary check should account for 64bit and
- * remapping.. */
- printf("IDMA window#%d: no space for size 0x%08x at "
- "0x%08x\n", i, s, b);
- rv = 0;
- continue;
- }
-
- j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
- if (j >= 0) {
- printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
- "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
- idma_wins[j].base,
- idma_wins[j].base + idma_wins[j].size - 1);
- rv = 0;
- }
- }
-
- return (rv);
-}
-
-void
-decode_win_idma_dump(u_long base)
-{
- int i;
-
- if (pm_is_disabled(CPU_PM_CTRL_IDMA))
- return;
-
- for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
- printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
- win_idma_br_read(base, i), win_idma_sz_read(base, i));
-
- if (win_idma_can_remap(i))
- printf(", ha 0x%08x", win_idma_har_read(base, i));
-
- printf("\n");
- }
- for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
- printf("IDMA channel#%d: ap 0x%08x\n", i,
- win_idma_cap_read(base, i));
- printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base));
-}
-#else
/* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
int
@@ -2062,285 +1543,10 @@
decode_win_idma_dump(u_long base)
{
}
-#endif
/**************************************************************************
* XOR windows routines
**************************************************************************/
-#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
-static int
-xor_ctrl_read(u_long base, int i, int c, int e)
-{
- uint32_t v;
- v = win_xor_ctrl_read(base, c, e);
- v &= (1 << i);
-
- return (v >> i);
-}
-
-static void
-xor_ctrl_write(u_long base, int i, int c, int e, int val)
-{
- uint32_t v;
-
- v = win_xor_ctrl_read(base, c, e);
- v &= ~(1 << i);
- v |= (val << i);
- win_xor_ctrl_write(base, c, e, v);
-}
-
-/*
- * Set channel protection 'val' for window 'w' on channel 'c'
- */
-static void
-xor_chan_write(u_long base, int c, int e, int w, int val)
-{
- uint32_t v;
-
- v = win_xor_ctrl_read(base, c, e);
- v &= ~(0x3 << (w * 2 + 16));
- v |= (val << (w * 2 + 16));
- win_xor_ctrl_write(base, c, e, v);
-}
-
-/*
- * Set protection 'val' on all channels for window 'w' on engine 'e'
- */
-static void
-xor_set_prot(u_long base, int w, int e, int val)
-{
- int c;
-
- for (c = 0; c < MV_XOR_CHAN_MAX; c++)
- xor_chan_write(base, c, e, w, val);
-}
-
-static int
-win_xor_can_remap(int i)
-{
-
- /* XOR decode windows 0-3 have remap capability */
- if (i < 4)
- return (1);
-
- return (0);
-}
-
-static int
-xor_max_eng(void)
-{
- uint32_t dev, rev;
-
- soc_id(&dev, &rev);
- switch (dev) {
- case MV_DEV_88F6281:
- case MV_DEV_88F6282:
- case MV_DEV_MV78130:
- case MV_DEV_MV78160:
- case MV_DEV_MV78230:
- case MV_DEV_MV78260:
- case MV_DEV_MV78460:
- return (2);
- case MV_DEV_MV78100:
- case MV_DEV_MV78100_Z0:
- return (1);
- default:
- return (0);
- }
-}
-
-static void
-xor_active_dram(u_long base, int c, int e, int *window)
-{
- uint32_t br, sz;
- int i, m, w;
-
- /*
- * Set up access to all active DRAM banks
- */
- m = xor_max_eng();
- for (i = 0; i < m; i++)
- if (ddr_is_active(i)) {
- br = ddr_base(i) | (ddr_attr(i) << 8) |
- ddr_target(i);
- sz = ((ddr_size(i) - 1) & 0xffff0000);
-
- /* Place DDR entries in non-remapped windows */
- for (w = 0; w < MV_WIN_XOR_MAX; w++)
- if (win_xor_can_remap(w) != 1 &&
- (xor_ctrl_read(base, w, c, e) == 0) &&
- w > *window) {
- /* Configure window */
- win_xor_br_write(base, w, e, br);
- win_xor_sz_write(base, w, e, sz);
-
- /* Set protection RW on all channels */
- xor_set_prot(base, w, e, 0x3);
-
- /* Enable window */
- xor_ctrl_write(base, w, c, e, 1);
- (*window)++;
- break;
- }
- }
-}
-
-void
-decode_win_xor_setup(u_long base)
-{
- uint32_t br, sz;
- int i, j, z, e = 1, m, window;
-
- if (pm_is_disabled(CPU_PM_CTRL_XOR))
- return;
-
- /*
- * Disable and clear all XOR windows, revoke protection for all
- * channels
- */
- m = xor_max_eng();
- for (j = 0; j < m; j++, e--) {
- /* Number of non-remaped windows */
- window = MV_XOR_NON_REMAP - 1;
-
- for (i = 0; i < MV_WIN_XOR_MAX; i++) {
- win_xor_br_write(base, i, e, 0);
- win_xor_sz_write(base, i, e, 0);
- }
-
- if (win_xor_can_remap(i) == 1)
- win_xor_har_write(base, i, e, 0);
-
- for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
- win_xor_ctrl_write(base, i, e, 0);
- xor_active_dram(base, i, e, &window);
- }
-
- /*
- * Remaining targets -- from a statically defined table
- */
- for (i = 0; i < xor_wins_no; i++)
- if (xor_wins[i].target > 0) {
- br = (xor_wins[i].base & 0xffff0000) |
- (xor_wins[i].attr << 8) |
- xor_wins[i].target;
- sz = ((xor_wins[i].size - 1) & 0xffff0000);
-
- /* Set the first free XOR window */
- for (z = 0; z < MV_WIN_XOR_MAX; z++) {
- if (xor_ctrl_read(base, z, 0, e) &&
- xor_ctrl_read(base, z, 1, e))
- continue;
-
- /* Configure window */
- win_xor_br_write(base, z, e, br);
- win_xor_sz_write(base, z, e, sz);
- if (win_xor_can_remap(z) &&
- xor_wins[z].remap >= 0)
- win_xor_har_write(base, z, e,
- xor_wins[z].remap);
-
- /* Set protection RW on all channels */
- xor_set_prot(base, z, e, 0x3);
-
- /* Enable window */
- xor_ctrl_write(base, z, 0, e, 1);
- xor_ctrl_write(base, z, 1, e, 1);
- break;
- }
- }
- }
-}
-
-int
-decode_win_xor_valid(void)
-{
- const struct decode_win *wintab;
- int c, i, j, rv;
- uint32_t b, e, s;
-
- if (xor_wins_no > MV_WIN_XOR_MAX) {
- printf("XOR windows: too many entries: %d\n", xor_wins_no);
- return (0);
- }
- for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
- if (ddr_is_active(i))
- c++;
-
- if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
- printf("XOR windows: too many entries: %d, available: %d\n",
- xor_wins_no, MV_WIN_IDMA_MAX - c);
- return (0);
- }
-
- wintab = xor_wins;
- rv = 1;
- for (i = 0; i < xor_wins_no; i++, wintab++) {
- if (wintab->target == 0) {
- printf("XOR window#%d: DDR target window is not "
- "supposed to be reprogrammed!\n", i);
- rv = 0;
- }
-
- if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
- printf("XOR window#%d: not capable of remapping, but "
- "val 0x%08x defined\n", i, wintab->remap);
- rv = 0;
- }
-
- s = wintab->size;
- b = wintab->base;
- e = b + s - 1;
- if (s > (0xFFFFFFFF - b + 1)) {
- /*
- * XXX this boundary check should account for 64bit
- * and remapping..
- */
- printf("XOR window#%d: no space for size 0x%08x at "
- "0x%08x\n", i, s, b);
- rv = 0;
- continue;
- }
-
- j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
- if (j >= 0) {
- printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
- "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
- xor_wins[j].base,
- xor_wins[j].base + xor_wins[j].size - 1);
- rv = 0;
- }
- }
-
- return (rv);
-}
-
-void
-decode_win_xor_dump(u_long base)
-{
- int i, j;
- int e = 1;
-
- if (pm_is_disabled(CPU_PM_CTRL_XOR))
- return;
-
- for (j = 0; j < xor_max_eng(); j++, e--) {
- for (i = 0; i < MV_WIN_XOR_MAX; i++) {
- printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
- win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e));
-
- if (win_xor_can_remap(i))
- printf(", ha 0x%08x", win_xor_har_read(base, i, e));
-
- printf("\n");
- }
- for (i = 0; i < MV_XOR_CHAN_MAX; i++)
- printf("XOR control#%d: 0x%08x\n", i,
- win_xor_ctrl_read(base, i, e));
- }
-}
-
-#else
/* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
static int
decode_win_xor_valid(void)
@@ -2358,7 +1564,6 @@
decode_win_xor_dump(u_long base)
{
}
-#endif
/**************************************************************************
* SATA windows routines
@@ -2369,9 +1574,6 @@
uint32_t cr, br;
int i, j;
- if (pm_is_disabled(CPU_PM_CTRL_SATA))
- return;
-
for (i = 0; i < MV_WIN_SATA_MAX; i++) {
win_sata_cr_write(base, i, 0);
win_sata_br_write(base, i, 0);
@@ -2380,7 +1582,7 @@
for (i = 0; i < MV_WIN_DDR_MAX; i++)
if (ddr_is_active(i)) {
cr = ((ddr_size(i) - 1) & 0xffff0000) |
- (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
+ (ddr_attr(i) << 8) | 1;
br = ddr_base(i);
/* Use the first available SATA window */
@@ -2413,7 +1615,6 @@
for (i = 0; i < MV_WIN_DDR_MAX; i++) {
if (ddr_is_active(i)) {
cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
- (ddr_target(i) << IO_WIN_TGT_SHIFT) |
IO_WIN_ENA_MASK;
br = ddr_base(i);
sz = (ddr_size(i) - 1) &
@@ -2453,8 +1654,6 @@
uint32_t dev, rev;
soc_id(&dev, &rev);
- if (dev == MV_DEV_88F5281)
- return (1);
return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
}
@@ -2476,7 +1675,6 @@
cr = (((ddr_size(i) - 1) &
(IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) |
(ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
- (ddr_target(i) << IO_WIN_TGT_SHIFT) |
IO_WIN_ENA_MASK);
/* Use the first available SDHCI window */
diff --git a/sys/arm/mv/mvreg.h b/sys/arm/mv/mvreg.h
--- a/sys/arm/mv/mvreg.h
+++ b/sys/arm/mv/mvreg.h
@@ -36,23 +36,6 @@
#include <arm/mv/mvwin.h>
-#if defined(SOC_MV_DISCOVERY)
-#define IRQ_CAUSE_ERROR 0x0
-#define IRQ_CAUSE 0x4
-#define IRQ_CAUSE_HI 0x8
-#define IRQ_MASK_ERROR 0xC
-#define IRQ_MASK 0x10
-#define IRQ_MASK_HI 0x14
-#define IRQ_CAUSE_SELECT 0x18
-#define FIQ_MASK_ERROR 0x1C
-#define FIQ_MASK 0x20
-#define FIQ_MASK_HI 0x24
-#define FIQ_CAUSE_SELECT 0x28
-#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
-#define ENDPOINT_IRQ_MASK(n) 0x30
-#define ENDPOINT_IRQ_MASK_HI(n) 0x34
-#define ENDPOINT_IRQ_CAUSE_SELECT 0x38
-#else
#define IRQ_CAUSE 0x0
#define IRQ_MASK 0x4
#define FIQ_MASK 0x8
@@ -64,7 +47,6 @@
#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */
#define IRQ_MASK_ERROR (-1) /* interrupt controller code */
-#endif
#define MAIN_IRQ_NUM 116
#define ERR_IRQ_NUM 32
@@ -119,71 +101,16 @@
/*
* Power Control
*/
-#if defined(SOC_MV_KIRKWOOD)
-#define CPU_PM_CTRL 0x18
-#else
#define CPU_PM_CTRL 0x1C
-#endif
#define CPU_PM_CTRL_NONE 0
#define CPU_PM_CTRL_ALL ~0x0
-#if defined(SOC_MV_KIRKWOOD)
-#define CPU_PM_CTRL_GE0 (1 << 0)
-#define CPU_PM_CTRL_PEX0_PHY (1 << 1)
-#define CPU_PM_CTRL_PEX0 (1 << 2)
-#define CPU_PM_CTRL_USB0 (1 << 3)
-#define CPU_PM_CTRL_SDIO (1 << 4)
-#define CPU_PM_CTRL_TSU (1 << 5)
-#define CPU_PM_CTRL_DUNIT (1 << 6)
-#define CPU_PM_CTRL_RUNIT (1 << 7)
-#define CPU_PM_CTRL_XOR0 (1 << 8)
-#define CPU_PM_CTRL_AUDIO (1 << 9)
-#define CPU_PM_CTRL_SATA0 (1 << 14)
-#define CPU_PM_CTRL_SATA1 (1 << 15)
-#define CPU_PM_CTRL_XOR1 (1 << 16)
-#define CPU_PM_CTRL_CRYPTO (1 << 17)
-#define CPU_PM_CTRL_GE1 (1 << 19)
-#define CPU_PM_CTRL_TDM (1 << 20)
-#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1)
-#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0)
-#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
-#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
- (1 - (u)))
-#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE)
-#elif defined(SOC_MV_DISCOVERY)
-#define CPU_PM_CTRL_GE0 (1 << 1)
-#define CPU_PM_CTRL_GE1 (1 << 2)
-#define CPU_PM_CTRL_PEX00 (1 << 5)
-#define CPU_PM_CTRL_PEX01 (1 << 6)
-#define CPU_PM_CTRL_PEX02 (1 << 7)
-#define CPU_PM_CTRL_PEX03 (1 << 8)
-#define CPU_PM_CTRL_PEX10 (1 << 9)
-#define CPU_PM_CTRL_PEX11 (1 << 10)
-#define CPU_PM_CTRL_PEX12 (1 << 11)
-#define CPU_PM_CTRL_PEX13 (1 << 12)
-#define CPU_PM_CTRL_SATA0_PHY (1 << 13)
-#define CPU_PM_CTRL_SATA0 (1 << 14)
-#define CPU_PM_CTRL_SATA1_PHY (1 << 15)
-#define CPU_PM_CTRL_SATA1 (1 << 16)
-#define CPU_PM_CTRL_USB0 (1 << 17)
-#define CPU_PM_CTRL_USB1 (1 << 18)
-#define CPU_PM_CTRL_USB2 (1 << 19)
-#define CPU_PM_CTRL_IDMA (1 << 20)
-#define CPU_PM_CTRL_XOR (1 << 21)
-#define CPU_PM_CTRL_CRYPTO (1 << 22)
-#define CPU_PM_CTRL_DEVICE (1 << 23)
-#define CPU_PM_CTRL_USB(u) (1 << (17 + (u)))
-#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
-#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
- (1 - (u)))
-#else
#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE)
#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE)
#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE)
#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE)
#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE)
#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE)
-#endif
/*
* Timers
@@ -308,11 +235,6 @@
#define MV_GPIO_OUT_OPEN_DRAIN 0x2
#define MV_GPIO_OUT_OPEN_SRC 0x4
-#if defined(SOC_MV_ORION)
-#define SAMPLE_AT_RESET 0x10
-#elif defined(SOC_MV_KIRKWOOD)
-#define SAMPLE_AT_RESET 0x30
-#endif
#define SAMPLE_AT_RESET_ARMADA38X 0x400
#define SAMPLE_AT_RESET_LO 0x30
#define SAMPLE_AT_RESET_HI 0x34
@@ -320,13 +242,6 @@
/*
* Clocks
*/
-#if defined(SOC_MV_ORION)
-#define TCLK_MASK 0x00000300
-#define TCLK_SHIFT 0x08
-#elif defined(SOC_MV_DISCOVERY)
-#define TCLK_MASK 0x00000180
-#define TCLK_SHIFT 0x07
-#endif
#define TCLK_MASK_ARMADA38X 0x00008000
#define TCLK_SHIFT_ARMADA38X 15
@@ -371,28 +286,14 @@
/*
* Chip ID
*/
-#define MV_DEV_88F5181 0x5181
-#define MV_DEV_88F5182 0x5182
-#define MV_DEV_88F5281 0x5281
-#define MV_DEV_88F6281 0x6281
-#define MV_DEV_88F6282 0x6282
-#define MV_DEV_88F6781 0x6781
#define MV_DEV_88F6828 0x6828
#define MV_DEV_88F6820 0x6820
#define MV_DEV_88F6810 0x6810
-#define MV_DEV_MV78100_Z0 0x6381
-#define MV_DEV_MV78100 0x7810
-#define MV_DEV_MV78130 0x7813
-#define MV_DEV_MV78160 0x7816
#define MV_DEV_MV78230 0x7823
#define MV_DEV_MV78260 0x7826
#define MV_DEV_MV78460 0x7846
-#define MV_DEV_88RC8180 0x8180
-#define MV_DEV_88RC9480 0x9480
-#define MV_DEV_88RC9580 0x9580
#define MV_DEV_FAMILY_MASK 0xff00
-#define MV_DEV_DISCOVERY 0x7800
#define MV_DEV_ARMADA38X 0x6800
/*
diff --git a/sys/arm/mv/mvvar.h b/sys/arm/mv/mvvar.h
--- a/sys/arm/mv/mvvar.h
+++ b/sys/arm/mv/mvvar.h
@@ -56,7 +56,6 @@
enum soc_family{
MV_SOC_ARMADA_38X = 0x00,
MV_SOC_ARMADA_XP = 0x01,
- MV_SOC_ARMV5 = 0x02,
MV_SOC_UNSUPPORTED = 0xff,
};
@@ -84,7 +83,6 @@
int soc_decode_win(void);
void soc_id(uint32_t *dev, uint32_t *rev);
void soc_dump_decode_win(void);
-uint32_t soc_power_ctrl_get(uint32_t mask);
void soc_power_ctrl_set(uint32_t mask);
int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
@@ -98,9 +96,7 @@
uint32_t ddr_base(int i);
uint32_t ddr_size(int i);
uint32_t ddr_attr(int i);
-uint32_t ddr_target(int i);
-uint32_t cpu_extra_feat(void);
uint32_t get_tclk(void);
uint32_t get_cpu_freq(void);
uint32_t get_l2clk(void);
diff --git a/sys/arm/mv/mvwin.h b/sys/arm/mv/mvwin.h
--- a/sys/arm/mv/mvwin.h
+++ b/sys/arm/mv/mvwin.h
@@ -56,15 +56,7 @@
* External devices: 0x80000000, 1 GB (VA == PA)
* Includes Device Bus, PCI and PCIE.
*/
-#if defined(SOC_MV_ORION)
-#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
-#elif defined(SOC_MV_KIRKWOOD)
-#define MV_PCI_PORTS 1 /* 1x PCIE */
-#elif defined(SOC_MV_DISCOVERY)
-#define MV_PCI_PORTS 8 /* 8x PCIE */
-#else
#define MV_PCI_PORTS 1 /* 1x PCIE -> worst case */
-#endif
/* PCI/PCIE Memory */
#define MV_PCI_MEM_PHYS_BASE 0x80000000
@@ -132,11 +124,7 @@
#define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
#define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
-#if defined(SOC_MV_DISCOVERY)
-#define MV_WIN_CPU_MAX 14
-#else
#define MV_WIN_CPU_MAX 8
-#endif
#define MV_WIN_CPU_MAX_ARMV7 20
#define MV_WIN_CPU_ATTR_SHIFT 8
@@ -154,13 +142,8 @@
#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
#define MV_WIN_DDR_TARGET 0x0
-#if defined(SOC_MV_DISCOVERY)
-#define MV_WIN_CESA_TARGET 9
-#define MV_WIN_CESA_ATTR(eng_sel) 1
-#else
#define MV_WIN_CESA_TARGET 3
#define MV_WIN_CESA_ATTR(eng_sel) 0
-#endif
#define MV_WIN_CESA_TARGET_ARMADAXP 9
/*
@@ -227,19 +210,9 @@
#define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4)
#define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
#define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
-#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
-#define MV_WIN_PCIE_TARGET(n) 4
-#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
-#define MV_WIN_PCIE_IO_ATTR(n) 0xE0
-#elif defined(SOC_MV_ORION)
-#define MV_WIN_PCIE_TARGET(n) 4
-#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
-#define MV_WIN_PCIE_IO_ATTR(n) 0x51
-#else
#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
-#endif
#define MV_WIN_PCI_TARGET 3
#define MV_WIN_PCI_MEM_ATTR 0x59
diff --git a/sys/arm/mv/timer.c b/sys/arm/mv/timer.c
--- a/sys/arm/mv/timer.c
+++ b/sys/arm/mv/timer.c
@@ -120,9 +120,7 @@
static int mv_timer_stop(struct eventtimer *et);
static void mv_setup_timers(void);
-static void mv_watchdog_enable_armv5(void);
static void mv_watchdog_enable_armadaxp(void);
-static void mv_watchdog_disable_armv5(void);
static void mv_watchdog_disable_armadaxp(void);
static void mv_delay(int usec, void* arg);
@@ -137,20 +135,9 @@
IRQ_TIMER0_CLR_ARMADAXP,
IRQ_TIMER_WD_CLR_ARMADAXP,
};
-static struct mv_timer_config timer_armv5_config =
-{
- MV_SOC_ARMV5,
- &mv_watchdog_enable_armv5,
- &mv_watchdog_disable_armv5,
- 0,
- BRIDGE_IRQ_CAUSE,
- IRQ_TIMER0_CLR,
- IRQ_TIMER_WD_CLR,
-};
static struct ofw_compat_data mv_timer_soc_config[] = {
{"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config },
- {"mrvl,timer", (uintptr_t)&timer_armv5_config },
{NULL, (uintptr_t)NULL },
};
@@ -380,28 +367,6 @@
timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
}
-static void
-mv_watchdog_enable_armv5(void)
-{
- uint32_t val, irq_cause, irq_mask;
-
- irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
- irq_cause &= timer_softc->config->irq_timer_wd_clr;
- write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
-
- irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
- irq_mask |= IRQ_TIMER_WD_MASK;
- write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
-
- val = read_cpu_ctrl(RSTOUTn_MASK);
- val |= WD_RST_OUT_EN;
- write_cpu_ctrl(RSTOUTn_MASK, val);
-
- val = mv_get_timer_control();
- val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
- mv_set_timer_control(val);
-}
-
static void
mv_watchdog_enable_armadaxp(void)
{
@@ -424,28 +389,6 @@
mv_set_timer_control(val);
}
-static void
-mv_watchdog_disable_armv5(void)
-{
- uint32_t val, irq_cause,irq_mask;
-
- val = mv_get_timer_control();
- val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
- mv_set_timer_control(val);
-
- val = read_cpu_ctrl(RSTOUTn_MASK);
- val &= ~WD_RST_OUT_EN;
- write_cpu_ctrl(RSTOUTn_MASK, val);
-
- irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
- irq_mask &= ~(IRQ_TIMER_WD_MASK);
- write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
-
- irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
- irq_cause &= timer_softc->config->irq_timer_wd_clr;
- write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
-}
-
static void
mv_watchdog_disable_armadaxp(void)
{
diff --git a/sys/conf/options.arm b/sys/conf/options.arm
--- a/sys/conf/options.arm
+++ b/sys/conf/options.arm
@@ -38,9 +38,6 @@
SOC_IMX6 opt_global.h
SOC_MV_ARMADAXP opt_global.h
SOC_MV_ARMADA38X opt_global.h
-SOC_MV_DISCOVERY opt_global.h
-SOC_MV_KIRKWOOD opt_global.h
-SOC_MV_ORION opt_global.h
SOC_OMAP3 opt_global.h
SOC_OMAP4 opt_global.h
SOC_TI_AM335X opt_global.h
diff --git a/sys/dev/cesa/cesa.c b/sys/dev/cesa/cesa.c
--- a/sys/dev/cesa/cesa.c
+++ b/sys/dev/cesa/cesa.c
@@ -1183,31 +1183,11 @@
soc_id(&d, &r);
switch (d) {
- case MV_DEV_88F6281:
- case MV_DEV_88F6282:
- /* Check if CESA peripheral device has power turned on */
- if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) ==
- CPU_PM_CTRL_CRYPTO) {
- device_printf(dev, "not powered on\n");
- return (ENXIO);
- }
- sc->sc_tperr = 0;
- break;
case MV_DEV_88F6828:
case MV_DEV_88F6820:
case MV_DEV_88F6810:
sc->sc_tperr = 0;
break;
- case MV_DEV_MV78100:
- case MV_DEV_MV78100_Z0:
- /* Check if CESA peripheral device has power turned on */
- if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) !=
- CPU_PM_CTRL_CRYPTO) {
- device_printf(dev, "not powered on\n");
- return (ENXIO);
- }
- sc->sc_tperr = CESA_ICR_TPERR;
- break;
default:
return (ENXIO);
}
diff --git a/sys/dev/mge/if_mge.c b/sys/dev/mge/if_mge.c
--- a/sys/dev/mge/if_mge.c
+++ b/sys/dev/mge/if_mge.c
@@ -398,33 +398,16 @@
uint32_t d, r;
soc_id(&d, &r);
- if (d == MV_DEV_88F6281 || d == MV_DEV_88F6781 ||
- d == MV_DEV_88F6282 ||
- d == MV_DEV_MV78100 ||
- d == MV_DEV_MV78100_Z0 ||
- (d & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY) {
- sc->mge_ver = 2;
- sc->mge_mtu = 0x4e8;
- sc->mge_tfut_ipg_max = 0xFFFF;
- sc->mge_rx_ipg_max = 0xFFFF;
- sc->mge_tx_arb_cfg = 0xFC0000FF;
- sc->mge_tx_tok_cfg = 0xFFFF7FFF;
- sc->mge_tx_tok_cnt = 0x3FFFFFFF;
- } else {
- sc->mge_ver = 1;
- sc->mge_mtu = 0x458;
- sc->mge_tfut_ipg_max = 0x3FFF;
- sc->mge_rx_ipg_max = 0x3FFF;
- sc->mge_tx_arb_cfg = 0x000000FF;
- sc->mge_tx_tok_cfg = 0x3FFFFFFF;
- sc->mge_tx_tok_cnt = 0x3FFFFFFF;
- }
- if (d == MV_DEV_88RC8180)
- sc->mge_intr_cnt = 1;
- else
- sc->mge_intr_cnt = 2;
-
- if (d == MV_DEV_MV78160 || d == MV_DEV_MV78260 || d == MV_DEV_MV78460)
+ sc->mge_ver = 1;
+ sc->mge_mtu = 0x458;
+ sc->mge_tfut_ipg_max = 0x3FFF;
+ sc->mge_rx_ipg_max = 0x3FFF;
+ sc->mge_tx_arb_cfg = 0x000000FF;
+ sc->mge_tx_tok_cfg = 0x3FFFFFFF;
+ sc->mge_tx_tok_cnt = 0x3FFFFFFF;
+ sc->mge_intr_cnt = 2;
+
+ if (d == MV_DEV_MV78260 || d == MV_DEV_MV78460)
sc->mge_hw_csum = 0;
else
sc->mge_hw_csum = 1;
diff --git a/sys/dev/mvs/mvs_soc.c b/sys/dev/mvs/mvs_soc.c
--- a/sys/dev/mvs/mvs_soc.c
+++ b/sys/dev/mvs/mvs_soc.c
@@ -61,11 +61,6 @@
int ports;
int quirks;
} mvs_ids[] = {
- {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC},
- {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC},
- {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC},
- {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC},
- {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC},
{MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC},
{MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC},
{0, 0x00, NULL, 0, 0}

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