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diff --git a/sysutils/u-boot-beagleplay-a53/Makefile b/sysutils/u-boot-beagleplay-a53/Makefile
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/Makefile
@@ -0,0 +1,12 @@
+MASTERDIR= ${.CURDIR}/../u-boot-master
+
+MODEL= beagleplay_a53
+BOARD_CONFIG= am62x_beagleplay_a53_defconfig
+FAMILY= k3a53
+
+CONFIG_FRAGMENT= ${.CURDIR}/files/bp_a53_fragment
+FRAGMENT_NAME= bp_a53_fragment
+
+EXTRA_PATCHES= ${.CURDIR}/files/
+
+.include "${MASTERDIR}/Makefile"
diff --git a/sysutils/u-boot-beagleplay-a53/files/0001-board-beagle-beagleplay-Enable-32k-crystal.patch b/sysutils/u-boot-beagleplay-a53/files/0001-board-beagle-beagleplay-Enable-32k-crystal.patch
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/files/0001-board-beagle-beagleplay-Enable-32k-crystal.patch
@@ -0,0 +1,75 @@
+From 0fdc81734b3e9fdf642f871a3578089533e29315 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Tue, 20 Feb 2024 12:39:48 -0600
+Subject: [PATCH 1/5] board: beagle: beagleplay: Enable 32k crystal
+
+Enable the external 32k crystal similar to that found on other
+production AM62X board. The trim settings for the crystal is board
+dependent, so the sequences tend to be board specific. Since this is
+a configuration that needs to be done prior to DM managing the system
+and all other muxes get set, do the same from R5 context.
+
+Tested-by: Robert Nelson <robertcnelson@gmail.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ board/beagle/beagleplay/beagleplay.c | 37 ++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c
+index 20819ecf45..a75b3145fa 100644
+--- a/board/beagle/beagleplay/beagleplay.c
++++ b/board/beagle/beagleplay/beagleplay.c
+@@ -11,6 +11,8 @@
+ #include <fdt_support.h>
+ #include <spl.h>
+
++#include <asm/arch/hardware.h>
++
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int board_init(void)
+@@ -28,6 +30,41 @@ int dram_init_banksize(void)
+ return fdtdec_setup_memory_banksize();
+ }
+
++#ifdef CONFIG_SPL_BOARD_INIT
++
++/*
++ * Enable the 32k Crystal: needed for accurate 32k clock
++ * and external clock sources such as wlan 32k input clock
++ * supplied from the SoC to the wlan chip.
++ *
++ * The trim setup can be very highly board type specific choice of the crystal
++ * So this is done in the board file, though, in this case, no specific trim
++ * is necessary.
++ */
++static void crystal_32k_enable(void)
++{
++ /* Only mess with 32k at the start of boot from R5 */
++ if (IS_ENABLED(CONFIG_CPU_V7R)) {
++ /*
++ * We have external 32k crystal, so lets enable it (0x0)
++ * and disable bypass (0x0)
++ */
++ writel(0x0, MCU_CTRL_LFXOSC_CTRL);
++
++ /* Add any crystal specific TRIM needed here.. */
++
++ /* Make sure to mux the SoC 32k from the crystal */
++ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
++ MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
++ }
++}
++
++void spl_board_init(void)
++{
++ crystal_32k_enable();
++}
++#endif
++
+ #ifdef CONFIG_BOARD_LATE_INIT
+ int board_late_init(void)
+ {
+--
+2.45.2
+
diff --git a/sysutils/u-boot-beagleplay-a53/files/0002-configs-am62x_beagleplay_r5_defconfig-Enable-SPL_BOA.patch b/sysutils/u-boot-beagleplay-a53/files/0002-configs-am62x_beagleplay_r5_defconfig-Enable-SPL_BOA.patch
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/files/0002-configs-am62x_beagleplay_r5_defconfig-Enable-SPL_BOA.patch
@@ -0,0 +1,28 @@
+From 14c6b88f79f5d1604eaf9342777cfe57dda867a0 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Tue, 20 Feb 2024 12:39:49 -0600
+Subject: [PATCH 2/5] configs: am62x_beagleplay_r5_defconfig: Enable
+ SPL_BOARD_INIT
+
+Enable CONFIG_SPL_BOARD_INIT to configure the 32k crystal.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ configs/am62x_beagleplay_r5_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
+index 2f3264b7ed..9413c85987 100644
+--- a/configs/am62x_beagleplay_r5_defconfig
++++ b/configs/am62x_beagleplay_r5_defconfig
+@@ -36,6 +36,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+ CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+ CONFIG_SPL_BSS_MAX_SIZE=0x3000
+ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
++CONFIG_SPL_BOARD_INIT=y
+ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_SEPARATE_BSS=y
+--
+2.45.2
+
diff --git a/sysutils/u-boot-beagleplay-a53/files/0003-arm-mach-k3-am62-Add-Debounce-configuration-register.patch b/sysutils/u-boot-beagleplay-a53/files/0003-arm-mach-k3-am62-Add-Debounce-configuration-register.patch
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/files/0003-arm-mach-k3-am62-Add-Debounce-configuration-register.patch
@@ -0,0 +1,31 @@
+From 39fc84f970fbdd33d7edc600faa0485c306bfdea Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Tue, 20 Feb 2024 12:39:50 -0600
+Subject: [PATCH 3/5] arm: mach-k3: am62: Add Debounce configuration register
+ definitions
+
+Add the Debounce configuration registers that need to be configured one
+time for the platform for the entire SoC.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
+index 54380f36e1..4cf7778a89 100644
+--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
++++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
+@@ -75,6 +75,9 @@
+
+ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
+
++/* Debounce register configuration */
++#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4))
++
+ #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
+
+ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
+--
+2.45.2
+
diff --git a/sysutils/u-boot-beagleplay-a53/files/0004-board-beagle-beagleplay-Configure-debounce-registers.patch b/sysutils/u-boot-beagleplay-a53/files/0004-board-beagle-beagleplay-Configure-debounce-registers.patch
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/files/0004-board-beagle-beagleplay-Configure-debounce-registers.patch
@@ -0,0 +1,54 @@
+From 019ad55839438031092677cd2522a912d88d32d0 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Tue, 20 Feb 2024 12:39:51 -0600
+Subject: [PATCH 4/5] board: beagle: beagleplay: Configure debounce registers
+
+Configure the debounce configuration that makes sense for BeaglePlay
+usage model.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ board/beagle/beagleplay/beagleplay.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c
+index a75b3145fa..5640fdf41e 100644
+--- a/board/beagle/beagleplay/beagleplay.c
++++ b/board/beagle/beagleplay/beagleplay.c
+@@ -59,9 +59,33 @@ static void crystal_32k_enable(void)
+ }
+ }
+
++static void debounce_configure(void)
++{
++ /* Configure debounce one time from R5 */
++ if (IS_ENABLED(CONFIG_CPU_V7R)) {
++ /*
++ * Setup debounce time registers.
++ * arbitrary values. Times are approx
++ */
++ /* 1.9ms debounce @ 32k */
++ writel(0x1, CTRLMMR_DBOUNCE_CFG(1));
++ /* 5ms debounce @ 32k */
++ writel(0x5, CTRLMMR_DBOUNCE_CFG(2));
++ /* 20ms debounce @ 32k */
++ writel(0x14, CTRLMMR_DBOUNCE_CFG(3));
++ /* 46ms debounce @ 32k */
++ writel(0x18, CTRLMMR_DBOUNCE_CFG(4));
++ /* 100ms debounce @ 32k */
++ writel(0x1c, CTRLMMR_DBOUNCE_CFG(5));
++ /* 156ms debounce @ 32k */
++ writel(0x1f, CTRLMMR_DBOUNCE_CFG(6));
++ }
++}
++
+ void spl_board_init(void)
+ {
+ crystal_32k_enable();
++ debounce_configure();
+ }
+ #endif
+
+--
+2.45.2
+
diff --git a/sysutils/u-boot-beagleplay-a53/files/0005-board-beagle-beagleplay-env-Drop-usb-and-pxe-as-boot.patch b/sysutils/u-boot-beagleplay-a53/files/0005-board-beagle-beagleplay-env-Drop-usb-and-pxe-as-boot.patch
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/files/0005-board-beagle-beagleplay-env-Drop-usb-and-pxe-as-boot.patch
@@ -0,0 +1,40 @@
+From 881379e9e286d0b40d9f054a1d176cbbcfed835e Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Tue, 20 Feb 2024 12:39:52 -0600
+Subject: [PATCH 5/5] board: beagle: beagleplay: env: Drop usb and pxe as boot
+ targets
+
+We had enabled USB and network pxe boot with the hope to get it all
+merged on time. However, it has not panned out. Drop usb and pxe boot
+else bootflow scan -l throws in:
+a) Unknown uclass 'usb' in label
+b) Crashes when attempting pxe - cpsw/mdio driver apparently has missing
+ error handling of what ever form. This is the one that Jan noticed in
+ his log.
+
+We can enable these on a later date once things are working.
+
+Cc: Roger Quadros <rogerq@kernel.org>
+
+Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
+Closes: https://lore.kernel.org/all/782ea2c0-eef5-478d-a122-cc6e2d066762@siemens.com/
+Signed-off-by: Nishanth Menon <nm@ti.com>
+---
+ board/beagle/beagleplay/beagleplay.env | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env
+index 647b25d14c..bbf6b925d0 100644
+--- a/board/beagle/beagleplay/beagleplay.env
++++ b/board/beagle/beagleplay/beagleplay.env
+@@ -13,6 +13,6 @@ boot=mmc
+ mmcdev=1
+ bootpart=1:1
+ bootdir=/boot
+-boot_targets=mmc1 mmc0 usb pxe
++boot_targets=mmc1 mmc0
+ bootmeths=script extlinux efi pxe
+ rd_spec=-
+--
+2.45.2
+
diff --git a/sysutils/u-boot-beagleplay-a53/files/bp_a53_fragment b/sysutils/u-boot-beagleplay-a53/files/bp_a53_fragment
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/files/bp_a53_fragment
@@ -0,0 +1,118 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
+CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80c80000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_EXT4_WRITE=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LZO=y
diff --git a/sysutils/u-boot-beagleplay-a53/pkg-descr b/sysutils/u-boot-beagleplay-a53/pkg-descr
new file mode 100644
--- /dev/null
+++ b/sysutils/u-boot-beagleplay-a53/pkg-descr
@@ -0,0 +1 @@
+U-Boot loader for BeaglePlay A53 core on the AM625

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