D55996.id174190.diff
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	diff --git a/sys/x86/x86/cpu_machdep.c b/sys/x86/x86/cpu_machdep.c
	--- a/sys/x86/x86/cpu_machdep.c
	+++ b/sys/x86/x86/cpu_machdep.c
	@@ -423,7 +423,7 @@
	cpu_est_clockrate(int cpu_id, uint64_t *rate)
	{
	uint64_t tsc1, tsc2;
	- uint64_t acnt, mcnt, perf;
	+ uint64_t acnt_start, acnt_end, mcnt_start, mcnt_end, perf;
	register_t reg;

	if (pcpu_find(cpu_id) == NULL \|\| rate == NULL)
	@@ -452,15 +452,15 @@
	/* Calibrate by measuring a short delay. */
	reg = intr_disable();
	if (tsc_is_invariant) {
	- wrmsr(MSR_MPERF, 0);
	- wrmsr(MSR_APERF, 0);
	+ mcnt_start = rdmsr(MSR_MPERF);
	+ acnt_start = rdmsr(MSR_APERF);
	tsc1 = rdtsc();
	DELAY(1000);
	- mcnt = rdmsr(MSR_MPERF);
	- acnt = rdmsr(MSR_APERF);
	+ mcnt_end = rdmsr(MSR_MPERF);
	+ acnt_end = rdmsr(MSR_APERF);
	tsc2 = rdtsc();
	intr_restore(reg);
	- if (mcnt == 0) {
	+ if (mcnt_end == mcnt_start) {
	tsc_perf_stat = 0;
	return (EOPNOTSUPP);
	}
	diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c
	--- a/sys/x86/x86/tsc.c
	+++ b/sys/x86/x86/tsc.c
	@@ -433,6 +433,8 @@
	void
	start_TSC(void)
	{
	+ uint64_t mperf, aperf;
	+
	if ((cpu_feature & CPUID_TSC) == 0 \|\| tsc_disabled)
	return;

	@@ -442,11 +444,13 @@
	/*
	* XXX Some emulators expose host CPUID without actual support
	* for these MSRs. We must test whether they really work.
	+ * They may also be read-only, so test for increment.
	+ *
	*/
	- wrmsr(MSR_MPERF, 0);
	- wrmsr(MSR_APERF, 0);
	+ mperf = rdmsr(MSR_MPERF);
	+ aperf = rdmsr(MSR_APERF);
	DELAY(10);
	- if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
	+ if (rdmsr(MSR_MPERF) != mperf && rdmsr(MSR_APERF) != aperf)
	tsc_perf_stat = 1;
	}