Page MenuHomeFreeBSD
Files F150266369

D55607.id172976.diff
No OneTemporary
Actions

D55607.id172976.diff
View Options

diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c
--- a/sys/dev/hwpmc/hwpmc_amd.c
+++ b/sys/dev/hwpmc/hwpmc_amd.c
@@ -655,7 +655,24 @@
KASSERT(ri >= 0 && ri < amd_npmcs,
("[amd,%d] ri %d out of range", __LINE__, ri));
- *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
+ switch (amd_pmcdesc[ri].pm_subclass) {
+ case PMC_AMD_SUB_CLASS_CORE:
+ if (amd_pmcdesc[ri].pm_perfctr >= AMD_PMC_CORE_BASE)
+ *msr = (amd_pmcdesc[ri].pm_perfctr -
+ AMD_PMC_CORE_BASE) / 2;
+ else
+ *msr = amd_pmcdesc[ri].pm_perfctr -
+ AMD_PMC_PERFCTR_0;
+ break;
+ case PMC_AMD_SUB_CLASS_L3_CACHE:
+ *msr = (amd_pmcdesc[ri].pm_perfctr - AMD_PMC_L3_BASE) / 2;
+ break;
+ case PMC_AMD_SUB_CLASS_DATA_FABRIC:
+ *msr = (amd_pmcdesc[ri].pm_perfctr - AMD_PMC_DF_BASE) / 2;
+ break;
+ default:
+ return (EINVAL);
+ }
return (0);
}
@@ -688,8 +705,23 @@
KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
for (n = 0, phw = pac->pc_amdpmcs; n < amd_npmcs; n++, phw++) {
- phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
- PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
+ /*
+ * DF MSRs are shared across all cores in the package.
+ * See AMD PPR section 2.1.9 [Register Sharing].
+ * Only mark DF counters as enabled on the package
+ * master CPU (lowest CPU ID in the package, cg_first
+ * of cpu_top) to prevent multiple CPUs from writing
+ * the shared MSRs simultaneously.
+ */
+ if (amd_pmcdesc[n].pm_subclass ==
+ PMC_AMD_SUB_CLASS_DATA_FABRIC &&
+ cpu != cpu_top->cg_first) {
+ phw->phw_state = 0;
+ } else {
+ phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
+ PMC_PHW_CPU_TO_STATE(cpu) |
+ PMC_PHW_INDEX_TO_STATE(n);
+ }
phw->phw_pmc = NULL;
pc->pc_hwpmcs[n + first_ri] = phw;
}

File Metadata

Mime Type
text/plain
Expires
Tue, Mar 31, 6:22 PM (3 h, 48 m)
Storage Engine
blob
Storage Format
Raw Data
Storage Handle
29167066
Default Alt Text
D55607.id172976.diff (1 KB)

Event Timeline