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D36876.id111638.diff
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diff --git a/sys/riscv/riscv/trap.c b/sys/riscv/riscv/trap.c
--- a/sys/riscv/riscv/trap.c
+++ b/sys/riscv/riscv/trap.c
@@ -303,6 +303,13 @@
dump_regs(frame);
panic("Memory access exception at 0x%016lx\n", frame->tf_sepc);
break;
+ case SCAUSE_LOAD_MISALIGNED:
+ case SCAUSE_STORE_MISALIGNED:
+ case SCAUSE_INST_MISALIGNED:
+ dump_regs(frame);
+ panic("Misaligned address exception at %#016lx: %#016lx\n",
+ frame->tf_sepc, frame->tf_stval);
+ break;
case SCAUSE_STORE_PAGE_FAULT:
case SCAUSE_LOAD_PAGE_FAULT:
case SCAUSE_INST_PAGE_FAULT:
@@ -371,6 +378,13 @@
exception);
userret(td, frame);
break;
+ case SCAUSE_LOAD_MISALIGNED:
+ case SCAUSE_STORE_MISALIGNED:
+ case SCAUSE_INST_MISALIGNED:
+ call_trapsignal(td, SIGBUS, BUS_ADRALN, (void *)frame->tf_sepc,
+ exception);
+ userret(td, frame);
+ break;
case SCAUSE_STORE_PAGE_FAULT:
case SCAUSE_LOAD_PAGE_FAULT:
case SCAUSE_INST_PAGE_FAULT:
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D36876.id111638.diff (942 B)
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D36876: riscv: handle misaligned address exceptions
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