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diff --git a/sys/amd64/amd64/trap.c b/sys/amd64/amd64/trap.c
--- a/sys/amd64/amd64/trap.c
+++ b/sys/amd64/amd64/trap.c
@@ -933,7 +933,7 @@
static void
trap_diag(struct trapframe *frame, vm_offset_t eva)
{
- int code, ss;
+ int code;
u_int type;
struct soft_segment_descriptor softseg;
struct user_segment_descriptor *gdt;
@@ -941,7 +941,7 @@
code = frame->tf_err;
type = frame->tf_trapno;
gdt = *PCPU_PTR(gdt);
- sdtossd(&gdt[IDXSEL(frame->tf_cs & 0xffff)], &softseg);
+ sdtossd(&gdt[IDXSEL(frame->tf_cs)], &softseg);
printf("\n\nFatal trap %d: %s while in %s mode\n", type,
type < nitems(trap_msg) ? trap_msg[type] : UNKNOWN,
@@ -960,11 +960,12 @@
code & PGEX_RSV ? "reserved bits in PTE" :
code & PGEX_P ? "protection violation" : "page not present");
}
- printf("instruction pointer = 0x%lx:0x%lx\n",
- frame->tf_cs & 0xffff, frame->tf_rip);
- ss = frame->tf_ss & 0xffff;
- printf("stack pointer = 0x%x:0x%lx\n", ss, frame->tf_rsp);
- printf("frame pointer = 0x%x:0x%lx\n", ss, frame->tf_rbp);
+ printf("instruction pointer = %#hx:%#lx\n",
+ frame->tf_cs, frame->tf_rip);
+ printf("stack pointer = %#hx:%#lx\n", frame->tf_ss,
+ frame->tf_rsp);
+ printf("frame pointer = %#hx:%#lx\n", frame->tf_ss,
+ frame->tf_rbp);
printf("code segment = base 0x%lx, limit 0x%lx, type 0x%x\n",
softseg.ssd_base, softseg.ssd_limit, softseg.ssd_type);
printf(" = DPL %d, pres %d, long %d, def32 %d, gran %d\n",
@@ -1058,7 +1059,7 @@
"r8 %#lx r9 %#lx r10 %#lx\n"
"r11 %#lx r12 %#lx r13 %#lx\n"
"r14 %#lx r15 %#lx rflags %#lx\n"
- "cs %#lx ss %#lx ds %#hx es %#hx fs %#hx gs %#hx\n"
+ "cs %#hx ss %#hx ds %#hx es %#hx fs %#hx gs %#hx\n"
"fsbase %#lx gsbase %#lx kgsbase %#lx\n",
frame->tf_rip, frame->tf_rsp, frame->tf_rbp,
frame->tf_rax, frame->tf_rdx, frame->tf_rbx,
diff --git a/sys/x86/include/frame.h b/sys/x86/include/frame.h
--- a/sys/x86/include/frame.h
+++ b/sys/x86/include/frame.h
@@ -143,17 +143,60 @@
/* below portion defined in hardware */
register_t tf_err;
register_t tf_rip;
- register_t tf_cs;
+ uint16_t tf_cs;
+ uint16_t tf_fred_evinfo3;
+ uint32_t tf_fred_zero2;
register_t tf_rflags;
/* the amd64 frame always has the stack registers */
register_t tf_rsp;
- register_t tf_ss;
+ uint16_t tf_ss;
+ uint16_t tf_fred_evinfo1;
+ uint32_t tf_fred_evinfo2;
+ /* two long words added by FRED */
+ uint64_t tf_fred_evdata;
+ uint64_t tf_fred_zero1;
};
-#define TF_HASSEGS 0x1
-#define TF_HASBASES 0x2
-#define TF_HASFPXSTATE 0x4
-#define TF_RESERV0 0x8 /* no tlsbase in the trapframe */
+#define TF_FRED_EVDATA_B0 0x0000000000000001ull /* %dr6 B0 */
+#define TF_FRED_EVDATA_B1 0x0000000000000002ull
+#define TF_FRED_EVDATA_B2 0x0000000000000004ull
+#define TF_FRED_EVDATA_B3 0x0000000000000008ull
+#define TF_FRED_EVDATA_BLD 0x0000000000000800ull /* bus lock acq
+ detected */
+#define TF_FRED_EVDATA_BD 0x0000000000002000ull /* dr access detected */
+#define TF_FRED_EVDATA_BS 0x0000000000004000ull /* single step */
+#define TF_FRED_EVDATA_RTM 0x0000000000010000ull /* #db or #bp in RTM */
+
+#define TF_FRED_EVINFO1_STIINT 0x0001 /* hw intr blocked by STI */
+#define TF_FRED_EVINFO1_SYSCALL 0x0002 /* SYSCALL/SYSENTER/INTn */
+#define TF_FRED_EVINFO1_NMI 0x0004 /* NMI */
+
+#define TF_FRED_EVINFO2_VECMASK 0x000000ff /* event vector mask */
+#define TF_FRED_EVINFO2_TYPEMASK 0x000f0000 /* event type mask */
+#define TF_FRED_EVINFO2_TYPE_EXTINT 0x00000000
+#define TF_FRED_EVINFO2_TYPE_NMI 0x00020000
+#define TF_FRED_EVINFO2_TYPE_EXC 0x00030000
+#define TF_FRED_EVINFO2_TYPE_INTn 0x00040000
+#define TF_FRED_EVINFO2_TYPE_INT1 0x00050000
+#define TF_FRED_EVINFO2_TYPE_INT3 0x00060000
+#define TF_FRED_EVINFO2_TYPE_SYSCALL 0x00070000
+#define TF_FRED_EVINFO2_ENCL 0x01000000 /* SGX-related */
+#define TF_FRED_EVINFO2_LM 0x02000000 /* in 64bit mode */
+#define TF_FRED_EVINFO2_NEST 0x04000000 /* during ev delivery */
+#define TF_FRED_EVINFO2_INSTLENMASK 0xf0000000 /* instr length mask */
+#define TF_FRED_EVINFO2_INSTLENSHIFT 28 /* instr length shift */
+
+#define TF_FRED_EVINFO2_VEC_SYSCALL 1
+#define TF_FRED_EVINFO2_VEC_SYSENTER 2
+
+#define TF_FRED_EVINFO3_CSLMASK 0x0003 /* event CSL mask */
+#define TF_FRED_EVINFO3_WFE 0x0004 /* in WAIT_FOR_ENDBRANCH */
+
+#define TF_HASSEGS 0x00000001
+#define TF_HASBASES 0x00000002
+#define TF_HASFPXSTATE 0x00000004
+#define TF_RESERV0 0x00000008 /* no tlsbase in the trapframe */
+#define TF_FRED 0x00000010
#endif /* __amd64__ */
#endif /* _MACHINE_FRAME_H_ */

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