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D52744.id163008.diff
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diff --git a/share/man/man9/atomic.9 b/share/man/man9/atomic.9
--- a/share/man/man9/atomic.9
+++ b/share/man/man9/atomic.9
@@ -235,6 +235,18 @@
However, they will not prevent the compiler or processor from moving loads
or stores into the critical section, which does not violate the semantics of
a mutex.
+.Ss Architecture-dependent caveats for compare-and-swap
+The
+.Fn atomic_[f]cmpset_<type>
+operations, specifically the ones without explicitly specified memory
+ordering variants, are defined as relaxed.
+However, the implementation on the
+.Tn x86
+architectures provides sequentially consistent semantics.
+On
+.Tn arm64/aarch64
+architecture, the operation provides acquire semantic for load
+and release semantic for store accesses.
.Ss Thread Fence Operations
Alternatively, a programmer can use atomic thread fence operations to
constrain the reordering of accesses.
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D52744: atomic.9: provide fine details about CAS memory model MD semantic
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