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Index: sys/conf/Makefile.riscv
===================================================================
--- sys/conf/Makefile.riscv
+++ sys/conf/Makefile.riscv
@@ -46,10 +46,6 @@
CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
.endif
-# Currently, the compile flags don't let the kernel know if this is a hard-float
-# ABI build or a soft-float ABI build. We need to pass in this information.
-CFLAGS += -DMACHINE_ARCH=\"${MACHINE_ARCH}\"
-
# hack because genassym.c includes sys/bus.h which includes these.
genassym.o: bus_if.h device_if.h
Index: sys/conf/kern.mk
===================================================================
--- sys/conf/kern.mk
+++ sys/conf/kern.mk
@@ -139,14 +139,23 @@
#
# For RISC-V we specify the soft-float ABI (lp64) to avoid the use of floating
-# point registers within the kernel. We also specify the "medium" code model,
-# which generates code suitable for a 2GiB addressing range located at any
-# offset, allowing modules to be located anywhere in the 64-bit address space.
-# Note that clang and GCC refer to this code model as "medium" and "medany"
-# respectively.
+# point registers within the kernel. However, for kernels supporting hardware
+# float (FPE), we have to include that in the march so we can have limited
+# floating point support in context switching needed for that. This is different
+# than userland where we use a hard-float ABI (lp64d).
+#
+# We also specify the "medium" code model, which generates code suitable for a
+# 2GiB addressing range located at any offset, allowing modules to be located
+# anywhere in the 64-bit address space. Note that clang and GCC refer to this
+# code model as "medium" and "medany" respectively.
#
.if ${MACHINE_CPUARCH} == "riscv"
-CFLAGS+= -march=rv64imafdc -mabi=lp64
+.if ${MACHINE_ARCH:Mriscv*sf}
+CFLAGS+= -march=rv64imac
+.else
+CFLAGS+= -march=rv64imafdc
+.endif
+CFLAGS+= -mabi=lp64
CFLAGS.clang+= -mcmodel=medium
CFLAGS.gcc+= -mcmodel=medany
INLINE_LIMIT?= 8000
Index: sys/riscv/include/param.h
===================================================================
--- sys/riscv/include/param.h
+++ sys/riscv/include/param.h
@@ -46,10 +46,17 @@
#define MACHINE "riscv"
#endif
#ifndef MACHINE_ARCH
-#ifdef __riscv_float_abi_soft
-#define MACHINE_ARCH "riscv64sf"
-#else
+/*
+ * Check to see if we're building with hardware floating instructions
+ * allowed. We check this instead of hard vs soft float ABI because we build the
+ * kernel with soft float ABI to avoid hard float instruction generation. If
+ * we ever allow a 'soft ABI but with hard floats' userland, then we'll need
+ * to rethink this.
+ */
+#ifdef __riscv_flen
#define MACHINE_ARCH "riscv64"
+#else
+#define MACHINE_ARCH "riscv64sf"
#endif
#endif

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