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D26495.id77256.diff
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Index: sys/arm64/arm64/busdma_bounce.c
===================================================================
--- sys/arm64/arm64/busdma_bounce.c
+++ sys/arm64/arm64/busdma_bounce.c
@@ -72,6 +72,7 @@
struct bus_dma_tag {
struct bus_dma_tag_common common;
+ size_t alloc_size;
int map_count;
int bounce_flags;
bus_dma_segment_t *segments;
@@ -209,8 +210,21 @@
newtag->map_count = 0;
newtag->segments = NULL;
- if ((flags & BUS_DMA_COHERENT) != 0)
+ if ((flags & BUS_DMA_COHERENT) != 0) {
newtag->bounce_flags |= BF_COHERENT;
+ newtag->alloc_size = newtag->common.maxsize;
+ } else {
+ /*
+ * Ensure the buffer is aligned to a cacheline when allocating
+ * a non-coherent buffer. This is so we don't have any data
+ * that another CPU may be accessing around DMA buffer
+ * causing the cache to become dirty.
+ */
+ newtag->common.alignment = MAX(newtag->common.alignment,
+ dcache_line_size);
+ newtag->alloc_size = roundup2(newtag->common.maxsize,
+ dcache_line_size);
+ }
if (parent != NULL) {
if ((newtag->common.filter != NULL ||
@@ -526,21 +540,21 @@
*
* In the meantime warn the user if malloc gets it wrong.
*/
- if ((dmat->common.maxsize <= PAGE_SIZE) &&
- (dmat->common.alignment <= dmat->common.maxsize) &&
+ if ((dmat->alloc_size <= PAGE_SIZE) &&
+ (dmat->common.alignment <= dmat->alloc_size) &&
dmat->common.lowaddr >= ptoa((vm_paddr_t)Maxmem) &&
attr == VM_MEMATTR_DEFAULT) {
- *vaddr = malloc(dmat->common.maxsize, M_DEVBUF, mflags);
+ *vaddr = malloc(dmat->alloc_size, M_DEVBUF, mflags);
} else if (dmat->common.nsegments >=
- howmany(dmat->common.maxsize, MIN(dmat->common.maxsegsz, PAGE_SIZE)) &&
+ howmany(dmat->alloc_size, MIN(dmat->common.maxsegsz, PAGE_SIZE)) &&
dmat->common.alignment <= PAGE_SIZE &&
(dmat->common.boundary % PAGE_SIZE) == 0) {
/* Page-based multi-segment allocations allowed */
- *vaddr = (void *)kmem_alloc_attr(dmat->common.maxsize, mflags,
+ *vaddr = (void *)kmem_alloc_attr(dmat->alloc_size, mflags,
0ul, dmat->common.lowaddr, attr);
dmat->bounce_flags |= BF_KMEM_ALLOC;
} else {
- *vaddr = (void *)kmem_alloc_contig(dmat->common.maxsize, mflags,
+ *vaddr = (void *)kmem_alloc_contig(dmat->alloc_size, mflags,
0ul, dmat->common.lowaddr, dmat->common.alignment != 0 ?
dmat->common.alignment : 1ul, dmat->common.boundary, attr);
dmat->bounce_flags |= BF_KMEM_ALLOC;
@@ -577,7 +591,7 @@
if ((dmat->bounce_flags & BF_KMEM_ALLOC) == 0)
free(vaddr, M_DEVBUF);
else
- kmem_free((vm_offset_t)vaddr, dmat->common.maxsize);
+ kmem_free((vm_offset_t)vaddr, dmat->alloc_size);
free(map, M_DEVBUF);
dmat->map_count--;
CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat,
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D26495: Ensure we always align and size arm64 busdma allocations to a cacheline
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