D39814.id121021.diff
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D39814.id121021.diff
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	diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
	--- a/sys/riscv/riscv/identcpu.c
	+++ b/sys/riscv/riscv/identcpu.c
	@@ -64,10 +64,19 @@
	register_t marchid; /* The architecture ID */
	register_t mimpid; /* The implementation ID */

	+/*
	+ * MMU virtual-addressing modes. Support for each level implies the previous,
	+ * so Sv48-enabled systems MUST support Sv39, etc.
	+ */
	+#define MMU_SV39 0x1 /* 3-level paging */
	+#define MMU_SV48 0x2 /* 4-level paging */
	+#define MMU_SV57 0x4 /* 5-level paging */
	+
	struct cpu_desc {
	const char *cpu_mvendor_name;
	const char *cpu_march_name;
	u_int isa_extensions; /* Single-letter extensions. */
	+ u_int mmu;
	};

	struct cpu_desc cpu_desc[MAXCPU];
	@@ -322,6 +331,15 @@
	isa[i] = tolower(isa[i]);
	parse_riscv_isa(desc, isa, len);

	+ /* Parse the mmu-type, clobbering isa[] */
	+ desc->mmu = MMU_SV39;
	+ if (OF_getprop(node, "mmu-type", isa, sizeof(isa)) > 0) {
	+ if (strcmp(isa, "riscv,sv48") == 0)
	+ desc->mmu \|= MMU_SV48;
	+ else if (strcmp(isa, "riscv,sv57") == 0)
	+ desc->mmu \|= MMU_SV48 \| MMU_SV57;
	+ }
	+
	/* Set up capabilities for userspace. */
	update_hwcap(desc);

	@@ -431,6 +449,11 @@
	printf(" marchid: %#lx, mimpid: %#lx\n",
	marchid, mimpid);
	}
	+ printf(" MMU: %#b\n", desc->mmu,
	+ "\020"
	+ "\01SV39"
	+ "\02SV48"
	+ "\03SV57");
	printf(" ISA: %#b\n", desc->isa_extensions,
	"\020"
	"\01Atomic"