Page MenuHomeFreeBSD
Files F146405962

D40888.diff
No OneTemporary
Actions

D40888.diff
View Options

diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -572,6 +572,11 @@
MRS_HWCAP_END
};
+static const struct mrs_field_value id_aa64isar0_tme[] = {
+ MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, TME, NONE, IMPL),
+ MRS_FIELD_VALUE_END,
+};
+
static const struct mrs_field_value id_aa64isar0_atomic[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL),
MRS_FIELD_VALUE_END,
@@ -644,6 +649,7 @@
id_aa64isar0_sha3_caps),
MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, id_aa64isar0_rdm,
id_aa64isar0_rdm_caps),
+ MRS_FIELD(ID_AA64ISAR0, TME, false, MRS_EXACT, id_aa64isar0_tme),
MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER,
id_aa64isar0_atomic, id_aa64isar0_atomic_caps),
MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER,
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -570,11 +570,11 @@
/* ID_AA64ISAR0_EL1 */
#define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1)
-#define ID_AA64ISAR0_EL1_op0 0x3
-#define ID_AA64ISAR0_EL1_op1 0x0
-#define ID_AA64ISAR0_EL1_CRn 0x0
-#define ID_AA64ISAR0_EL1_CRm 0x6
-#define ID_AA64ISAR0_EL1_op2 0x0
+#define ID_AA64ISAR0_EL1_op0 3
+#define ID_AA64ISAR0_EL1_op1 0
+#define ID_AA64ISAR0_EL1_CRn 0
+#define ID_AA64ISAR0_EL1_CRm 6
+#define ID_AA64ISAR0_EL1_op2 0
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK)
@@ -602,6 +602,10 @@
#define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK)
#define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
#define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
+#define ID_AA64ISAR0_TME_SHIFT 24
+#define ID_AA64ISAR0_TME_MASK (UL(0xf) << ID_AA64ISAR0_TME_SHIFT)
+#define ID_AA64ISAR0_TME_NONE (UL(0x0) << ID_AA64ISAR0_TME_SHIFT)
+#define ID_AA64ISAR0_TME_IMPL (UL(0x1) << ID_AA64ISAR0_TME_SHIFT)
#define ID_AA64ISAR0_RDM_SHIFT 28
#define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK)

File Metadata

Mime Type
text/plain
Expires
Tue, Mar 3, 10:55 AM (19 h, 5 m)
Storage Engine
blob
Storage Format
Raw Data
Storage Handle
29184450
Default Alt Text
D40888.diff (2 KB)

Event Timeline