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Index: sys/dev/hwpmc/hwpmc_intel.c
===================================================================
--- sys/dev/hwpmc/hwpmc_intel.c
+++ sys/dev/hwpmc/hwpmc_intel.c
@@ -149,7 +149,7 @@
break;
case 0x2A: /* Per Intel document 253669-039US 05/2011. */
cputype = PMC_CPU_INTEL_SANDYBRIDGE;
- nclasses = 5;
+ nclasses = 3;
break;
case 0x2D: /* Per Intel document 253669-044US 08/2012. */
cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
@@ -195,7 +195,7 @@
case 0x3C: /* Per Intel document 325462-045US 01/2013. */
case 0x45: /* Per Intel document 325462-045US 09/2014. */
cputype = PMC_CPU_INTEL_HASWELL;
- nclasses = 5;
+ nclasses = 3;
break;
case 0x37:
case 0x4A:
@@ -275,10 +275,27 @@
* Intel Corei7 and Westmere processors.
*/
case PMC_CPU_INTEL_COREI7:
- case PMC_CPU_INTEL_HASWELL:
- case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_WESTMERE:
+#ifdef notyet
+ /*
+ * TODO: re-enable uncore class on these processors.
+ *
+ * The uncore unit was reworked beginning with Sandy Bridge, including
+ * the MSRs required to program it. In particular, we need to:
+ * - Support reading and writing the ARB and C-box units, depending on
+ * the exact event requested
+ * - Parse the MSR_UNC_CBO_CONFIG MSR for number of C-box units in the
+ * system
+ * - Create some kind of mapping between C-box <--> CPU
+ *
+ * Also TODO: support later changes to these interfaces, to enable the
+ * uncore class on generations newer than Broadwell. Skylake and later
+ * appear to have different addresses for the uncore MSRs.
+ */
+ case PMC_CPU_INTEL_HASWELL:
case PMC_CPU_INTEL_BROADWELL:
+ case PMC_CPU_INTEL_SANDYBRIDGE:
+#endif
error = pmc_uncore_initialize(pmc_mdep, ncpus);
break;
default:
@@ -329,11 +346,13 @@
* Uncore.
*/
switch (md->pmd_cputype) {
- case PMC_CPU_INTEL_BROADWELL:
case PMC_CPU_INTEL_COREI7:
+ case PMC_CPU_INTEL_WESTMERE:
+#ifdef notyet
case PMC_CPU_INTEL_HASWELL:
+ case PMC_CPU_INTEL_BROADWELL:
case PMC_CPU_INTEL_SANDYBRIDGE:
- case PMC_CPU_INTEL_WESTMERE:
+#endif
pmc_uncore_finalize(md);
break;
default:

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