D9221.diff
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	Index: head/sys/dev/ahci/ahci.h
	===================================================================
	--- head/sys/dev/ahci/ahci.h
	+++ head/sys/dev/ahci/ahci.h
	@@ -598,6 +598,7 @@
	#define AHCI_Q_FORCE_PI 0x00040000
	#define AHCI_Q_RESTORE_CAP 0x00080000
	#define AHCI_Q_NOMSIX 0x00100000
	+#define AHCI_Q_MRVL_SR_DEL 0x00200000

	#define AHCI_Q_BIT_STRING \
	"\020" \
	Index: head/sys/dev/ahci/ahci.c
	===================================================================
	--- head/sys/dev/ahci/ahci.c
	+++ head/sys/dev/ahci/ahci.c
	@@ -1598,6 +1598,14 @@
	}

	/*
	+ * Some Marvell controllers require additional time
	+ * after soft reset to work properly. Setup delay
	+ * to 50ms after soft reset.
	+ */
	+ if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
	+ DELAY(50000);
	+
	+ /*
	* Marvell HBAs with non-RAID firmware do not wait for
	* readiness after soft reset, so we have to wait here.
	* Marvell RAIDs do not have this problem, but instead