D1744.diff
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	Index: sys/dev/drm2/i915/i915_drv.h
	===================================================================
	--- sys/dev/drm2/i915/i915_drv.h
	+++ sys/dev/drm2/i915/i915_drv.h
	@@ -166,6 +166,7 @@

	struct intel_device_info {
	u8 gen;
	+ u8 not_supported:1;
	u8 is_mobile:1;
	u8 is_i85x:1;
	u8 is_i915g:1;
	Index: sys/dev/drm2/i915/i915_drv.c
	===================================================================
	--- sys/dev/drm2/i915/i915_drv.c
	+++ sys/dev/drm2/i915/i915_drv.c
	@@ -208,6 +208,7 @@
	.has_blt_ring = 1,
	.has_llc = 1,
	.has_pch_split = 1,
	+ .not_supported = 1,
	};

	static const struct intel_device_info intel_haswell_m_info = {
	@@ -217,6 +218,7 @@
	.has_blt_ring = 1,
	.has_llc = 1,
	.has_pch_split = 1,
	+ .not_supported = 1,
	};

	#define INTEL_VGA_DEVICE(id, info_) { \
	@@ -282,6 +284,8 @@
	{0, 0}
	};

	+static int i915_enable_unsupported;
	+
	static int i915_drm_freeze(struct drm_device *dev)
	{
	struct drm_i915_private *dev_priv;
	@@ -458,6 +462,8 @@
	for (did = &pciidlist[0]; did->device != 0; did++) {
	if (did->device != device)
	continue;
	+ if (did->info->not_supported && !i915_enable_unsupported)
	+ return (NULL);
	return (did->info);
	}
	return (NULL);
	@@ -527,6 +533,7 @@
	TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
	int i915_enable_hangcheck = 1;
	TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
	+TUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported);

	#define PCI_VENDOR_INTEL 0x8086
	#define INTEL_PCH_DEVICE_ID_MASK 0xff00