D3487.id8218.diff
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	Index: sys/dev/drm2/drmP.h
	===================================================================
	--- sys/dev/drm2/drmP.h
	+++ sys/dev/drm2/drmP.h
	@@ -1095,7 +1095,7 @@
	char busid_str[128];
	int modesetting;

	- drm_pci_id_list_t id_entry; / PCI ID, name, and chipset private */
	+ const drm_pci_id_list_t id_entry; / PCI ID, name, and chipset private */
	};

	#define DRM_SWITCH_POWER_ON 0
	@@ -1735,8 +1735,8 @@
	bool dmi_check_system(const struct dmi_system_id *);

	/* Device setup support (drm_drv.c) */
	-int drm_probe_helper(device_t kdev, drm_pci_id_list_t *idlist);
	-int drm_attach_helper(device_t kdev, drm_pci_id_list_t *idlist,
	+int drm_probe_helper(device_t kdev, const drm_pci_id_list_t *idlist);
	+int drm_attach_helper(device_t kdev, const drm_pci_id_list_t *idlist,
	struct drm_driver *driver);
	int drm_generic_detach(device_t kdev);

	Index: sys/dev/drm2/drm_os_freebsd.c
	===================================================================
	--- sys/dev/drm2/drm_os_freebsd.c
	+++ sys/dev/drm2/drm_os_freebsd.c
	@@ -67,8 +67,8 @@
	return (tv);
	}

	-static drm_pci_id_list_t *
	-drm_find_description(int vendor, int device, drm_pci_id_list_t *idlist)
	+static const drm_pci_id_list_t *
	+drm_find_description(int vendor, int device, const drm_pci_id_list_t *idlist)
	{
	int i = 0;

	@@ -87,9 +87,9 @@
	* method.
	*/
	int
	-drm_probe_helper(device_t kdev, drm_pci_id_list_t *idlist)
	+drm_probe_helper(device_t kdev, const drm_pci_id_list_t *idlist)
	{
	- drm_pci_id_list_t *id_entry;
	+ const drm_pci_id_list_t *id_entry;
	int vendor, device;

	vendor = pci_get_vendor(kdev);
	@@ -118,7 +118,7 @@
	* method.
	*/
	int
	-drm_attach_helper(device_t kdev, drm_pci_id_list_t *idlist,
	+drm_attach_helper(device_t kdev, const drm_pci_id_list_t *idlist,
	struct drm_driver *driver)
	{
	struct drm_device *dev;
	Index: sys/dev/drm2/i915/i915_reg.h
	===================================================================
	--- sys/dev/drm2/i915/i915_reg.h
	+++ sys/dev/drm2/i915/i915_reg.h
	@@ -29,6 +29,7 @@
	#define _I915_REG_H_

	#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
	+#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))

	#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))

	@@ -43,6 +44,14 @@
	*/
	#define INTEL_GMCH_CTRL 0x52
	#define INTEL_GMCH_VGA_DISABLE (1 << 1)
	+#define SNB_GMCH_CTRL 0x50
	+#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
	+#define SNB_GMCH_GGMS_MASK 0x3
	+#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
	+#define SNB_GMCH_GMS_MASK 0x1f
	+#define IVB_GMCH_GMS_SHIFT 4
	+#define IVB_GMCH_GMS_MASK 0xf
	+

	/* PCI config space */

	@@ -108,7 +117,6 @@
	#define GEN6_GRDOM_MEDIA (1 << 2)
	#define GEN6_GRDOM_BLT (1 << 3)

	-/* PPGTT stuff */
	#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) \| (((addr) >> 28) & 0xff0))

	#define GEN6_PDE_VALID (1 << 0)
	@@ -213,6 +221,13 @@
	#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
	#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
	#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
	+/* IVB has funny definitions for which plane to flip. */
	+#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
	+#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
	+#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
	+#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
	+#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
	+#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
	#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
	#define MI_ARB_ENABLE (1<<0)
	#define MI_ARB_DISABLE (0<<0)
	@@ -236,11 +251,18 @@
	*/
	#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
	#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
	-#define MI_INVALIDATE_TLB (1<<18)
	-#define MI_INVALIDATE_BSD (1<<7)
	+#define MI_FLUSH_DW_STORE_INDEX (1<<21)
	+#define MI_INVALIDATE_TLB (1<<18)
	+#define MI_FLUSH_DW_OP_STOREDW (1<<14)
	+#define MI_INVALIDATE_BSD (1<<7)
	+#define MI_FLUSH_DW_USE_GTT (1<<2)
	+#define MI_FLUSH_DW_USE_PPGTT (0<<2)
	#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
	-#define MI_BATCH_NON_SECURE (1)
	-#define MI_BATCH_NON_SECURE_I965 (1<<8)
	+#define MI_BATCH_NON_SECURE (1)
	+/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
	+#define MI_BATCH_NON_SECURE_I965 (1<<8)
	+#define MI_BATCH_PPGTT_HSW (1<<8)
	+#define MI_BATCH_NON_SECURE_HSW (1<<13)
	#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
	#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
	#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
	@@ -298,6 +320,7 @@
	#define DISPLAY_PLANE_B (1<<20)
	#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)\|(0x3<<27)\|(0x2<<24)\|(len-2))
	#define PIPE_CONTROL_CS_STALL (1<<20)
	+#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
	#define PIPE_CONTROL_QW_WRITE (1<<14)
	#define PIPE_CONTROL_DEPTH_STALL (1<<13)
	#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
	@@ -363,6 +386,7 @@
	#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
	#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
	#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
	+#define DPIO_PLL_REFCLK_SEL_MASK 3
	#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
	#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
	#define _DPIO_REFSFR_B 0x8034
	@@ -378,6 +402,9 @@

	#define DPIO_FASTCLK_DISABLE 0x8100

	+#define DPIO_DATA_CHANNEL1 0x8220
	+#define DPIO_DATA_CHANNEL2 0x8420
	+
	/*
	* Fence registers
	*/
	@@ -444,6 +471,7 @@
	#define RING_ACTHD(base) ((base)+0x74)
	#define RING_NOPID(base) ((base)+0x94)
	#define RING_IMR(base) ((base)+0xa8)
	+#define RING_TIMESTAMP(base) ((base)+0x358)
	#define TAIL_ADDR 0x001FFFF8
	#define HEAD_WRAP_COUNT 0xFFE00000
	#define HEAD_WRAP_ONE 0x00200000
	@@ -472,6 +500,11 @@
	#define IPEIR_I965 0x02064
	#define IPEHR_I965 0x02068
	#define INSTDONE_I965 0x0206c
	+#define GEN7_INSTDONE_1 0x0206c
	+#define GEN7_SC_INSTDONE 0x07100
	+#define GEN7_SAMPLER_INSTDONE 0x0e160
	+#define GEN7_ROW_INSTDONE 0x0e164
	+#define I915_NUM_INSTDONE_REG 4
	#define RING_IPEIR(base) ((base)+0x64)
	#define RING_IPEHR(base) ((base)+0x68)
	#define RING_INSTDONE(base) ((base)+0x6c)
	@@ -494,12 +527,17 @@
	#define DMA_FADD_I8XX 0x020d0

	#define ERROR_GEN6 0x040a0
	+#define GEN7_ERR_INT 0x44040
	+#define ERR_INT_MMIO_UNCLAIMED (1<<13)
	+
	+#define DERRMR 0x44050

	/* GM45+ chicken bits -- debug workaround bits that may be required
	* for various sorts of correct behavior. The top 16 bits of each are
	* the enables for writing to the corresponding low bit.
	*/
	#define _3D_CHICKEN 0x02084
	+#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
	#define _3D_CHICKEN2 0x0208c
	/* Disables pipelining of read flushes past the SF-WIZ interface.
	* Required on all Ironlake steppings according to the B-Spec, but the
	@@ -507,11 +545,17 @@
	*/
	# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
	#define _3D_CHICKEN3 0x02090
	-#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5)
	+#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
	+#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)

	#define MI_MODE 0x0209c
	# define VS_TIMER_DISPATCH (1 << 6)
	# define MI_FLUSH_ENABLE (1 << 12)
	+# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
	+
	+#define GEN6_GT_MODE 0x20d0
	+#define GEN6_GT_MODE_HI (1 << 9)
	+#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)

	#define GFX_MODE 0x02520
	#define GFX_MODE_GEN7 0x0229c
	@@ -523,11 +567,15 @@
	#define GFX_PSMI_GRANULARITY (1<<10)
	#define GFX_PPGTT_ENABLE (1<<9)

	+#define VLV_DISPLAY_BASE 0x180000
	+
	#define SCPD0 0x0209c /* 915+ only */
	#define IER 0x020a0
	#define IIR 0x020a4
	#define IMR 0x020a8
	#define ISR 0x020ac
	+#define VLV_GUNIT_CLOCK_GATE 0x182060
	+#define GCFG_DIS (1<<8)
	#define VLV_IIR_RW 0x182084
	#define VLV_IER 0x1820a0
	#define VLV_IIR 0x1820a4
	@@ -642,6 +690,7 @@
	#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */

	#define CACHE_MODE_0 0x02120 /* 915+ only */
	+#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
	#define CM0_IZ_OPT_DISABLE (1<<6)
	#define CM0_ZR_OPT_DISABLE (1<<5)
	#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
	@@ -651,6 +700,8 @@
	#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
	#define BB_ADDR 0x02140 /* 8 bytes */
	#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
	+#define GFX_FLSH_CNTL_GEN6 0x101008
	+#define GFX_FLSH_CNTL_EN (1<<0)
	#define ECOSKPD 0x021d0
	#define ECO_GATING_CX_ONLY (1<<3)
	#define ECO_FLIP_DONE (1<<0)
	@@ -685,6 +736,10 @@
	#define GEN6_BLITTER_FBC_NOTIFY (1<<3)

	#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
	+#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
	+#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
	+#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
	+#define GEN6_BSD_GO_INDICATOR (1 << 4)
	#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
	#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
	#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
	@@ -907,6 +962,7 @@
	#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
	#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
	#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
	+#define DPLL_LOCK_VLV (1<<15)
	#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)

	#define SRX_INDEX 0x3c4
	@@ -1452,6 +1508,10 @@
	#define DDRMPLL1 0X12c20
	#define PEG_BAND_GAP_DATA 0x14d68

	+#define GEN6_GT_THREAD_STATUS_REG 0x13805c
	+#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
	+#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 \| (0x07 << 16))
	+
	#define GEN6_GT_PERF_STATUS 0x145948
	#define GEN6_RP_STATE_LIMITS 0x145994
	#define GEN6_RP_STATE_CAP 0x145998
	@@ -1485,6 +1545,14 @@
	GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
	GEN7_CXT_GT1_SIZE(ctx_reg) + \
	GEN7_CXT_VFSTATE_SIZE(ctx_reg))
	+#define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f)
	+#define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7)
	+#define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff)
	+#define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \
	+ HSW_CXT_RING_SIZE(ctx_reg) + \
	+ HSW_CXT_RENDER_SIZE(ctx_reg) + \
	+ GEN7_CXT_VFSTATE_SIZE(ctx_reg))
	+

	/*
	* Overlay regs
	@@ -1527,23 +1595,46 @@
	#define _VSYNCSHIFT_B 0x61028


	-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
	-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
	-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
	-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
	-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
	-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
	+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
	+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
	+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
	+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
	+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
	+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
	#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
	-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
	+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)

	/* VGA port control */
	#define ADPA 0x61100
	+#define PCH_ADPA 0xe1100
	+#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
	+
	#define ADPA_DAC_ENABLE (1<<31)
	#define ADPA_DAC_DISABLE 0
	#define ADPA_PIPE_SELECT_MASK (1<<30)
	#define ADPA_PIPE_A_SELECT 0
	#define ADPA_PIPE_B_SELECT (1<<30)
	#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
	+/* CPT uses bits 29:30 for pch transcoder select */
	+#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
	+#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
	+#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
	+#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
	+#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
	+#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
	+#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
	+#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
	+#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
	+#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
	+#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
	+#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
	+#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
	+#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
	+#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
	+#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
	+#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
	+#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
	+#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
	#define ADPA_USE_VGA_HVPOLARITY (1<<15)
	#define ADPA_SETS_HVPOLARITY 0
	#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
	@@ -1590,12 +1681,23 @@
	#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)

	#define PORT_HOTPLUG_STAT 0x61114
	+/* HDMI/DP bits are gen4+ */
	#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
	#define DPB_HOTPLUG_INT_STATUS (1 << 29)
	#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
	#define DPC_HOTPLUG_INT_STATUS (1 << 28)
	#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
	#define DPD_HOTPLUG_INT_STATUS (1 << 27)
	+/* HDMI bits are shared with the DP bits */
	+/*
	+#define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29)
	+#define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28)
	+#define HDMID_HOTPLUG_LIVE_STATUS (1 << 27)
	+#define HDMID_HOTPLUG_INT_STATUS (3 << 21)
	+#define HDMIC_HOTPLUG_INT_STATUS (3 << 19)
	+#define HDMIB_HOTPLUG_INT_STATUS (3 << 17)
	+*/
	+/* CRT/TV common between gen3+ */
	#define CRT_HOTPLUG_INT_STATUS (1 << 11)
	#define TV_HOTPLUG_INT_STATUS (1 << 10)
	#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
	@@ -1604,6 +1706,13 @@
	#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
	#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
	#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
	+/* SDVO is different across gen3/4 */
	+#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
	+#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
	+#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
	+#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
	+#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
	+#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)

	/* SDVO port control */
	#define SDVOB 0x61140
	@@ -1728,6 +1837,10 @@

	/* Video Data Island Packet control */
	#define VIDEO_DIP_DATA 0x61178
	+/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
	+ * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
	+ * of the infoframe structure specified by CEA-861. */
	+#define VIDEO_DIP_DATA_SIZE 32
	#define VIDEO_DIP_CTL 0x61170
	/* Pre HSW: */
	#define VIDEO_DIP_ENABLE (1 << 31)
	@@ -1735,19 +1848,25 @@
	#define VIDEO_DIP_PORT_C (2 << 29)
	#define VIDEO_DIP_PORT_D (3 << 29)
	#define VIDEO_DIP_PORT_MASK (3 << 29)
	+#define VIDEO_DIP_ENABLE_GCP (1 << 25)
	#define VIDEO_DIP_ENABLE_AVI (1 << 21)
	#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
	+#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
	#define VIDEO_DIP_ENABLE_SPD (8 << 21)
	-#define VIDEO_DIP_SELECT_MASK (3 << 19)
	#define VIDEO_DIP_SELECT_AVI (0 << 19)
	#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
	#define VIDEO_DIP_SELECT_SPD (3 << 19)
	+#define VIDEO_DIP_SELECT_MASK (3 << 19)
	#define VIDEO_DIP_FREQ_ONCE (0 << 16)
	#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
	#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
	#define VIDEO_DIP_FREQ_MASK (3 << 16)
	/* HSW and later: */
	+#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
	+#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
	#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
	+#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
	+#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
	#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)

	/* Panel power sequencing */
	@@ -1819,18 +1938,35 @@
	#define PFIT_AUTO_RATIOS 0x61238

	/* Backlight control */
	-#define BLC_PWM_CTL 0x61254
	-#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
	#define BLC_PWM_CTL2 0x61250 /* 965+ only */
	-#define BLM_COMBINATION_MODE (1 << 30)
	+#define BLM_PWM_ENABLE (1 << 31)
	+#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
	+#define BLM_PIPE_SELECT (1 << 29)
	+#define BLM_PIPE_SELECT_IVB (3 << 29)
	+#define BLM_PIPE_A (0 << 29)
	+#define BLM_PIPE_B (1 << 29)
	+#define BLM_PIPE_C (2 << 29) /* ivb + */
	+#define BLM_PIPE(pipe) ((pipe) << 29)
	+#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
	+#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
	+#define BLM_PHASE_IN_ENABLE (1 << 25)
	+#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
	+#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
	+#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
	+#define BLM_PHASE_IN_COUNT_SHIFT (8)
	+#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
	+#define BLM_PHASE_IN_INCR_SHIFT (0)
	+#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
	+#define BLC_PWM_CTL 0x61254
	/*
	* This is the most significant 15 bits of the number of backlight cycles in a
	* complete cycle of the modulated backlight control.
	*
	* The actual value is this field multiplied by two.
	*/
	-#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
	-#define BLM_LEGACY_MODE (1 << 16)
	+#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
	+#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
	+#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
	/*
	* This is the number of cycles out of the backlight modulation cycle for which
	* the backlight is on.
	@@ -1840,9 +1976,24 @@
	*/
	#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
	#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
	+#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
	+#define BLM_POLARITY_PNV (1 << 0) /* pnv only */

	#define BLC_HIST_CTL 0x61260

	+/* New registers for PCH-split platforms. Safe where new bits show up, the
	+ * register layout machtes with gen4 BLC_PWM_CTL[12]. */
	+#define BLC_PWM_CPU_CTL2 0x48250
	+#define BLC_PWM_CPU_CTL 0x48254
	+
	+/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
	+ * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
	+#define BLC_PWM_PCH_CTL1 0xc8250
	+#define BLM_PCH_PWM_ENABLE (1 << 31)
	+#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
	+#define BLM_PCH_POLARITY (1 << 29)
	+#define BLC_PWM_PCH_CTL2 0xc8254
	+
	/* TV port control */
	#define TV_CTL 0x68000
	/** Enables the TV encoder */
	@@ -2530,6 +2681,7 @@
	#define PIPECONF_GAMMA (1<<24)
	#define PIPECONF_FORCE_BORDER (1<<25)
	#define PIPECONF_INTERLACE_MASK (7 << 21)
	+#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
	/* Note that pre-gen3 does not support interlaced display directly. Panel
	* fitting must be disabled on pre-ilk for interlaced. */
	#define PIPECONF_PROGRESSIVE (0 << 21)
	@@ -2600,20 +2752,20 @@
	#define PIPE_12BPC (3 << 5)

	#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
	-#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
	+#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
	#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
	#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
	#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
	#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)

	#define VLV_DPFLIPSTAT 0x70028
	-#define PIPEB_LINE_COMPARE_STATUS (1<<29)
	+#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
	#define PIPEB_HLINE_INT_EN (1<<28)
	#define PIPEB_VBLANK_INT_EN (1<<27)
	#define SPRITED_FLIPDONE_INT_EN (1<<26)
	#define SPRITEC_FLIPDONE_INT_EN (1<<25)
	#define PLANEB_FLIPDONE_INT_EN (1<<24)
	-#define PIPEA_LINE_COMPARE_STATUS (1<<21)
	+#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
	#define PIPEA_HLINE_INT_EN (1<<20)
	#define PIPEA_VBLANK_INT_EN (1<<19)
	#define SPRITEB_FLIPDONE_INT_EN (1<<18)
	@@ -2887,12 +3039,19 @@
	#define DISPPLANE_GAMMA_ENABLE (1<<30)
	#define DISPPLANE_GAMMA_DISABLE 0
	#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
	+#define DISPPLANE_YUV422 (0x0<<26)
	#define DISPPLANE_8BPP (0x2<<26)
	-#define DISPPLANE_15_16BPP (0x4<<26)
	-#define DISPPLANE_16BPP (0x5<<26)
	-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
	-#define DISPPLANE_32BPP (0x7<<26)
	-#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
	+#define DISPPLANE_BGRA555 (0x3<<26)
	+#define DISPPLANE_BGRX555 (0x4<<26)
	+#define DISPPLANE_BGRX565 (0x5<<26)
	+#define DISPPLANE_BGRX888 (0x6<<26)
	+#define DISPPLANE_BGRA888 (0x7<<26)
	+#define DISPPLANE_RGBX101010 (0x8<<26)
	+#define DISPPLANE_RGBA101010 (0x9<<26)
	+#define DISPPLANE_BGRX101010 (0xa<<26)
	+#define DISPPLANE_RGBX161616 (0xc<<26)
	+#define DISPPLANE_RGBX888 (0xe<<26)
	+#define DISPPLANE_RGBA888 (0xf<<26)
	#define DISPPLANE_STEREO_ENABLE (1<<25)
	#define DISPPLANE_STEREO_DISABLE 0
	#define DISPPLANE_SEL_PIPE_SHIFT 24
	@@ -2913,6 +3072,8 @@
	#define _DSPASIZE 0x70190
	#define _DSPASURF 0x7019C /* 965+ only */
	#define _DSPATILEOFF 0x701A4 /* 965+ only */
	+#define _DSPAOFFSET 0x701A4 /* HSW */
	+#define _DSPASURFLIVE 0x701AC

	#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
	#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
	@@ -2921,13 +3082,16 @@
	#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
	#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
	#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
	+#define DSPLINOFF(plane) DSPADDR(plane)
	+#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
	+#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)

	/* Display/Sprite base address macros */
	#define DISP_BASEADDR_MASK (0xfffff000)
	#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
	#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
	#define I915_MODIFY_DISPBASE(reg, gfx_addr) \
	- (I915_WRITE(reg, gfx_addr \| I915_LO_DISPBASE(I915_READ(reg))))
	+ (I915_WRITE((reg), (gfx_addr) \| I915_LO_DISPBASE(I915_READ(reg))))

	/* VBIOS flags */
	#define SWF00 0x71410
	@@ -2966,6 +3130,8 @@
	#define _DSPBSIZE 0x71190
	#define _DSPBSURF 0x7119C
	#define _DSPBTILEOFF 0x711A4
	+#define _DSPBOFFSET 0x711A4
	+#define _DSPBSURFLIVE 0x711AC

	/* Sprite A control */
	#define _DVSACNTR 0x72180
	@@ -3031,6 +3197,7 @@
	#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
	#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
	#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
	+#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)

	#define _SPRA_CTL 0x70280
	#define SPRITE_ENABLE (1<<31)
	@@ -3065,6 +3232,8 @@
	#define _SPRA_SURF 0x7029c
	#define _SPRA_KEYMAX 0x702a0
	#define _SPRA_TILEOFF 0x702a4
	+#define _SPRA_OFFSET 0x702a4
	+#define _SPRA_SURFLIVE 0x702ac
	#define _SPRA_SCALE 0x70304
	#define SPRITE_SCALE_ENABLE (1<<31)
	#define SPRITE_FILTER_MASK (3<<29)
	@@ -3085,6 +3254,8 @@
	#define _SPRB_SURF 0x7129c
	#define _SPRB_KEYMAX 0x712a0
	#define _SPRB_TILEOFF 0x712a4
	+#define _SPRB_OFFSET 0x712a4
	+#define _SPRB_SURFLIVE 0x712ac
	#define _SPRB_SCALE 0x71304
	#define _SPRB_GAMC 0x71400

	@@ -3098,8 +3269,10 @@
	#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
	#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
	#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
	+#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
	#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
	#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
	+#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)

	/* VBIOS regs */
	#define VGACNTRL 0x71400
	@@ -3189,20 +3362,22 @@
	#define _PIPEB_LINK_M2 0x61048
	#define _PIPEB_LINK_N2 0x6104c

	-#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
	-#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
	-#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
	-#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
	-#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
	-#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
	-#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
	-#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
	+#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
	+#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
	+#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
	+#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
	+#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
	+#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
	+#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
	+#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)

	/* CPU panel fitter */
	/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
	#define _PFA_CTL_1 0x68080
	#define _PFB_CTL_1 0x68880
	#define PF_ENABLE (1<<31)
	+#define PF_PIPE_SEL_MASK_IVB (3<<29)
	+#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
	#define PF_FILTER_MASK (3<<23)
	#define PF_FILTER_PROGRAMMED (0<<23)
	#define PF_FILTER_MED_3x3 (1<<23)
	@@ -3321,6 +3496,13 @@
	#define ILK_DPFC_DIS1 (1<<8)
	#define ILK_DPFC_DIS2 (1<<9)

	+#define ILK_DSPCLK_GATE_D 0x42020
	+#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
	+#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
	+#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
	+#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
	+#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
	+
	#define IVB_CHICKEN3 0x4200c
	# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
	# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
	@@ -3335,17 +3517,24 @@

	#define GEN7_L3CNTLREG1 0xB01C
	#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
	+#define GEN7_L3AGDIS (1<<19)

	#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
	#define GEN7_WA_L3_CHICKEN_MODE 0x20000000

	+#define GEN7_L3SQCREG4 0xb034
	+#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
	+
	/* WaCatErrorRejectionIssue */
	#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
	#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)

	+#define HSW_FUSE_STRAP 0x42014
	+#define HSW_CDCLK_LIMIT (1 << 24)
	+
	/* PCH */

	-/* south display engine interrupt */
	+/* south display engine interrupt: IBX */
	#define SDE_AUDIO_POWER_D (1 << 27)
	#define SDE_AUDIO_POWER_C (1 << 26)
	#define SDE_AUDIO_POWER_B (1 << 25)
	@@ -3381,15 +3570,44 @@
	#define SDE_TRANSA_CRC_ERR (1 << 1)
	#define SDE_TRANSA_FIFO_UNDER (1 << 0)
	#define SDE_TRANS_MASK (0x3f)
	-/* CPT */
	-#define SDE_CRT_HOTPLUG_CPT (1 << 19)
	+
	+/* south display engine interrupt: CPT/PPT */
	+#define SDE_AUDIO_POWER_D_CPT (1 << 31)
	+#define SDE_AUDIO_POWER_C_CPT (1 << 30)
	+#define SDE_AUDIO_POWER_B_CPT (1 << 29)
	+#define SDE_AUDIO_POWER_SHIFT_CPT 29
	+#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
	+#define SDE_AUXD_CPT (1 << 27)
	+#define SDE_AUXC_CPT (1 << 26)
	+#define SDE_AUXB_CPT (1 << 25)
	+#define SDE_AUX_MASK_CPT (7 << 25)
	#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
	#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
	#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
	+#define SDE_CRT_HOTPLUG_CPT (1 << 19)
	#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT \| \
	SDE_PORTD_HOTPLUG_CPT \| \
	SDE_PORTC_HOTPLUG_CPT \| \
	SDE_PORTB_HOTPLUG_CPT)
	+#define SDE_GMBUS_CPT (1 << 17)
	+#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
	+#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
	+#define SDE_FDI_RXC_CPT (1 << 8)
	+#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
	+#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
	+#define SDE_FDI_RXB_CPT (1 << 4)
	+#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
	+#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
	+#define SDE_FDI_RXA_CPT (1 << 0)
	+#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT \| \
	+ SDE_AUDIO_CP_REQ_B_CPT \| \
	+ SDE_AUDIO_CP_REQ_A_CPT)
	+#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT \| \
	+ SDE_AUDIO_CP_CHG_B_CPT \| \
	+ SDE_AUDIO_CP_CHG_A_CPT)
	+#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT \| \
	+ SDE_FDI_RXB_CPT \| \
	+ SDE_FDI_RXA_CPT)

	#define SDEISR 0xc4000
	#define SDEIMR 0xc4004
	@@ -3654,18 +3872,27 @@
	#define TRANS_6BPC (2<<5)
	#define TRANS_12BPC (3<<5)

	-#define _TRANSA_CHICKEN2 0xf0064
	-#define _TRANSB_CHICKEN2 0xf1064
	-#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
	+#define _TRANSA_CHICKEN1 0xf0060
	+#define _TRANSB_CHICKEN1 0xf1060
	+#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
	+#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
	+#define _TRANSA_CHICKEN2 0xf0064
	+#define _TRANSB_CHICKEN2 0xf1064
	+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
	#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
	+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
	+#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)

	#define SOUTH_CHICKEN1 0xc2000
	#define FDIA_PHASE_SYNC_SHIFT_OVR 19
	#define FDIA_PHASE_SYNC_SHIFT_EN 18
	-#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
	-#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
	+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
	+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
	+#define FDI_BC_BIFURCATION_SELECT (1 << 12)
	#define SOUTH_CHICKEN2 0xc2004
	-#define DPLS_EDP_PPS_FIX_DIS (1<<0)
	+#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
	+#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
	+#define DPLS_EDP_PPS_FIX_DIS (1<<0)

	#define _FDI_RXA_CHICKEN 0xc200c
	#define _FDI_RXB_CHICKEN 0xc2010
	@@ -3675,6 +3902,7 @@

	#define SOUTH_DSPCLK_GATE_D 0xc2020
	#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
	+#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)

	/* CPU: FDI_TX */
	#define _FDI_TXA_CTL 0x60100
	@@ -3726,20 +3954,22 @@
	#define FDI_LINK_TRAIN_AUTO (1<<10)
	#define FDI_SCRAMBLING_ENABLE (0<<7)
	#define FDI_SCRAMBLING_DISABLE (1<<7)
	+
	/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
	#define _FDI_RXA_CTL 0xf000c
	#define _FDI_RXB_CTL 0xf100c
	#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
	#define FDI_RX_ENABLE (1<<31)
	/* train, dp width same as FDI_TX */
	-#define FDI_FS_ERRC_ENABLE (1<<27)
	-#define FDI_FE_ERRC_ENABLE (1<<26)
	+#define FDI_FS_ERRC_ENABLE (1<<27)
	+#define FDI_FE_ERRC_ENABLE (1<<26)
	#define FDI_DP_PORT_WIDTH_X8 (7<<19)
	+#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
	#define FDI_8BPC (0<<16)
	#define FDI_10BPC (1<<16)
	#define FDI_6BPC (2<<16)
	#define FDI_12BPC (3<<16)
	-#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
	+#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
	#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
	#define FDI_RX_PLL_ENABLE (1<<13)
	#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
	@@ -3759,13 +3989,21 @@
	#define FDI_PORT_WIDTH_2X_LPT (1<<19)
	#define FDI_PORT_WIDTH_1X_LPT (0<<19)

	-#define _FDI_RXA_MISC 0xf0010
	-#define _FDI_RXB_MISC 0xf1010
	+#define _FDI_RXA_MISC 0xf0010
	+#define _FDI_RXB_MISC 0xf1010
	+#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
	+#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
	+#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
	+#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
	+#define FDI_RX_TP1_TO_TP2_48 (2<<20)
	+#define FDI_RX_TP1_TO_TP2_64 (3<<20)
	+#define FDI_RX_FDI_DELAY_90 (0x90<<0)
	+#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
	+
	#define _FDI_RXA_TUSIZE1 0xf0030
	#define _FDI_RXA_TUSIZE2 0xf0038
	#define _FDI_RXB_TUSIZE1 0xf1030
	#define _FDI_RXB_TUSIZE2 0xf1038
	-#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
	#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
	#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)

	@@ -3849,6 +4087,19 @@
	#define PCH_LVDS 0xe1180
	#define LVDS_DETECTED (1 << 1)

	+/* vlv has 2 sets of panel control regs. */
	+#define PIPEA_PP_STATUS 0x61200
	+#define PIPEA_PP_CONTROL 0x61204
	+#define PIPEA_PP_ON_DELAYS 0x61208
	+#define PIPEA_PP_OFF_DELAYS 0x6120c
	+#define PIPEA_PP_DIVISOR 0x61210
	+
	+#define PIPEB_PP_STATUS 0x61300
	+#define PIPEB_PP_CONTROL 0x61304
	+#define PIPEB_PP_ON_DELAYS 0x61308
	+#define PIPEB_PP_OFF_DELAYS 0x6130c
	+#define PIPEB_PP_DIVISOR 0x61310
	+
	#define BLC_PWM_CPU_CTL2 0x48250
	#define PWM_ENABLE (1 << 31)
	#define PWM_PIPE_A (0 << 29)
	@@ -3886,6 +4137,11 @@
	#define PANEL_LIGHT_ON_DELAY_SHIFT 0

	#define PCH_PP_OFF_DELAYS 0xc720c
	+#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
	+#define PANEL_POWER_PORT_LVDS (0 << 30)
	+#define PANEL_POWER_PORT_DP_A (1 << 30)
	+#define PANEL_POWER_PORT_DP_C (2 << 30)
	+#define PANEL_POWER_PORT_DP_D (3 << 30)
	#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
	#define PANEL_POWER_DOWN_DELAY_SHIFT 16
	#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
	@@ -3927,11 +4183,13 @@
	#define PORT_TRANS_C_SEL_CPT (2<<29)
	#define PORT_TRANS_SEL_MASK (3<<29)
	#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
	+#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
	+#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)

	#define TRANS_DP_CTL_A 0xe0300
	#define TRANS_DP_CTL_B 0xe1300
	#define TRANS_DP_CTL_C 0xe2300
	-#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
	+#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
	#define TRANS_DP_OUTPUT_ENABLE (1<<31)
	#define TRANS_DP_PORT_SEL_B (0<<29)
	#define TRANS_DP_PORT_SEL_C (1<<29)
	@@ -3986,8 +4244,11 @@
	#define FORCEWAKE 0xA18C
	#define FORCEWAKE_VLV 0x1300b0
	#define FORCEWAKE_ACK_VLV 0x1300b4
	+#define FORCEWAKE_ACK_HSW 0x130044
	#define FORCEWAKE_ACK 0x130090
	#define FORCEWAKE_MT 0xa188 /* multi-threaded */
	+#define FORCEWAKE_KERNEL 0x1
	+#define FORCEWAKE_USER 0x2
	#define FORCEWAKE_MT_ACK 0x130040
	#define ECOBUS 0xa180
	#define FORCEWAKE_MT_ENABLE (1<<5)
	@@ -4006,10 +4267,15 @@
	# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)

	#define GEN6_UCGCTL2 0x9404
	+# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
	+# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
	# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
	# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
	# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)

	+#define GEN7_UCGCTL4 0x940c
	+#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
	+
	#define GEN6_RPNSWREQ 0xA008
	#define GEN6_TURBO_DISABLE (1<<31)
	#define GEN6_FREQUENCY(x) ((x)<<25)
	@@ -4028,7 +4294,9 @@
	#define GEN6_RP_INTERRUPT_LIMITS 0xA014
	#define GEN6_RPSTAT1 0xA01C
	#define GEN6_CAGF_SHIFT 8
	+#define HSW_CAGF_SHIFT 7
	#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
	+#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
	#define GEN6_RP_CONTROL 0xA024
	#define GEN6_RP_MEDIA_TURBO (1<<11)
	#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
	@@ -4041,6 +4309,7 @@
	#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
	#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
	#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
	+#define GEN7_RP_DOWN_IDLE_AVG (0x2<<0)
	#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
	#define GEN6_RP_UP_THRESHOLD 0xA02C
	#define GEN6_RP_DOWN_THRESHOLD 0xA030
	@@ -4080,7 +4349,7 @@
	#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
	#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
	#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
	-#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD \| \
	+#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD \| \
	GEN6_PM_RP_DOWN_THRESHOLD \| \
	GEN6_PM_RP_DOWN_TIMEOUT)

	@@ -4094,6 +4363,10 @@
	#define GEN6_READ_OC_PARAMS 0xc
	#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
	#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
	+#define GEN6_PCODE_WRITE_RC6VIDS 0x4
	+#define GEN6_PCODE_READ_RC6VIDS 0x5
	+#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
	+#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
	#define GEN6_PCODE_DATA 0x138128
	#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8

	@@ -4105,6 +4378,35 @@
	#define GEN6_RC6 3
	#define GEN6_RC7 4

	+#define GEN7_MISCCPCTL (0x9424)
	+#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
	+
	+/* IVYBRIDGE DPF */
	+#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
	+#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
	+#define GEN7_PARITY_ERROR_VALID (1<<13)
	+#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
	+#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
	+#define GEN7_PARITY_ERROR_ROW(reg) \
	+ ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
	+#define GEN7_PARITY_ERROR_BANK(reg) \
	+ ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
	+#define GEN7_PARITY_ERROR_SUBBANK(reg) \
	+ ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
	+#define GEN7_L3CDERRST1_ENABLE (1<<7)
	+
	+#define GEN7_L3LOG_BASE 0xB070
	+#define GEN7_L3LOG_SIZE 0x80
	+
	+#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
	+#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
	+#define GEN7_MAX_PS_THREAD_DEP (8<<12)
	+#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
	+
	+#define GEN7_ROW_CHICKEN2 0xe4f4
	+#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
	+#define DOP_CLOCK_GATING_DISABLE (1<<0)
	+
	#define G4X_AUD_VID_DID 0x62020
	#define INTEL_AUDIO_DEVCL 0x808629FB
	#define INTEL_AUDIO_DEVBLC 0x80862801
	@@ -4118,7 +4420,15 @@
	#define G4X_HDMIW_HDMIEDID 0x6210C

	#define IBX_HDMIW_HDMIEDID_A 0xE2050
	+#define IBX_HDMIW_HDMIEDID_B 0xE2150
	+#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
	+ IBX_HDMIW_HDMIEDID_A, \
	+ IBX_HDMIW_HDMIEDID_B)
	#define IBX_AUD_CNTL_ST_A 0xE20B4
	+#define IBX_AUD_CNTL_ST_B 0xE21B4
	+#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
	+ IBX_AUD_CNTL_ST_A, \
	+ IBX_AUD_CNTL_ST_B)
	#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
	#define IBX_ELD_ADDRESS (0x1f << 5)
	#define IBX_ELD_ACK (1 << 4)
	@@ -4127,7 +4437,15 @@
	#define IBX_CP_READYB (1 << 1)

	#define CPT_HDMIW_HDMIEDID_A 0xE5050
	+#define CPT_HDMIW_HDMIEDID_B 0xE5150
	+#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
	+ CPT_HDMIW_HDMIEDID_A, \
	+ CPT_HDMIW_HDMIEDID_B)
	#define CPT_AUD_CNTL_ST_A 0xE50B4
	+#define CPT_AUD_CNTL_ST_B 0xE51B4
	+#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
	+ CPT_AUD_CNTL_ST_A, \
	+ CPT_AUD_CNTL_ST_B)
	#define CPT_AUD_CNTRL_ST2 0xE50C0

	/* These are the 4 32-bit write offset registers for each stream
	@@ -4137,7 +4455,15 @@
	#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)

	#define IBX_AUD_CONFIG_A 0xe2000
	+#define IBX_AUD_CONFIG_B 0xe2100
	+#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
	+ IBX_AUD_CONFIG_A, \
	+ IBX_AUD_CONFIG_B)
	#define CPT_AUD_CONFIG_A 0xe5000
	+#define CPT_AUD_CONFIG_B 0xe5100
	+#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
	+ CPT_AUD_CONFIG_A, \
	+ CPT_AUD_CONFIG_B)
	#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
	#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
	#define AUD_CONFIG_UPPER_N_SHIFT 20
	@@ -4148,164 +4474,232 @@
	#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
	#define AUD_CONFIG_DISABLE_NCTS (1 << 3)

	+/* HSW Audio */
	+#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
	+#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
	+#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
	+ HSW_AUD_CONFIG_A, \
	+ HSW_AUD_CONFIG_B)
	+
	+#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
	+#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
	+#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
	+ HSW_AUD_MISC_CTRL_A, \
	+ HSW_AUD_MISC_CTRL_B)
	+
	+#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
	+#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
	+#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
	+ HSW_AUD_DIP_ELD_CTRL_ST_A, \
	+ HSW_AUD_DIP_ELD_CTRL_ST_B)
	+
	+/* Audio Digital Converter */
	+#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
	+#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
	+#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
	+ HSW_AUD_DIG_CNVT_1, \
	+ HSW_AUD_DIG_CNVT_2)
	+#define DIP_PORT_SEL_MASK 0x3
	+
	+#define HSW_AUD_EDID_DATA_A 0x65050
	+#define HSW_AUD_EDID_DATA_B 0x65150
	+#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
	+ HSW_AUD_EDID_DATA_A, \
	+ HSW_AUD_EDID_DATA_B)
	+
	+#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
	+#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
	+#define AUDIO_INACTIVE_C (1<<11)
	+#define AUDIO_INACTIVE_B (1<<7)
	+#define AUDIO_INACTIVE_A (1<<3)
	+#define AUDIO_OUTPUT_ENABLE_A (1<<2)
	+#define AUDIO_OUTPUT_ENABLE_B (1<<6)
	+#define AUDIO_OUTPUT_ENABLE_C (1<<10)
	+#define AUDIO_ELD_VALID_A (1<<0)
	+#define AUDIO_ELD_VALID_B (1<<4)
	+#define AUDIO_ELD_VALID_C (1<<8)
	+#define AUDIO_CP_READY_A (1<<1)
	+#define AUDIO_CP_READY_B (1<<5)
	+#define AUDIO_CP_READY_C (1<<9)
	+
	/* HSW Power Wells */
	-#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
	-#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
	-#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
	-#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
	-#define HSW_PWR_WELL_ENABLE (1<<31)
	-#define HSW_PWR_WELL_STATE (1<<30)
	-#define HSW_PWR_WELL_CTL5 0x45410
	+#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
	+#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
	+#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
	+#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
	+#define HSW_PWR_WELL_ENABLE (1<<31)
	+#define HSW_PWR_WELL_STATE (1<<30)
	+#define HSW_PWR_WELL_CTL5 0x45410
	#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
	#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
	-#define HSW_PWR_WELL_FORCE_ON (1<<19)
	-#define HSW_PWR_WELL_CTL6 0x45414
	+#define HSW_PWR_WELL_FORCE_ON (1<<19)
	+#define HSW_PWR_WELL_CTL6 0x45414

	/* Per-pipe DDI Function Control */
	-#define PIPE_DDI_FUNC_CTL_A 0x60400
	-#define PIPE_DDI_FUNC_CTL_B 0x61400
	-#define PIPE_DDI_FUNC_CTL_C 0x62400
	-#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
	-#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
	- PIPE_DDI_FUNC_CTL_A, \
	- PIPE_DDI_FUNC_CTL_B)
	-#define PIPE_DDI_FUNC_ENABLE (1<<31)
	+#define TRANS_DDI_FUNC_CTL_A 0x60400
	+#define TRANS_DDI_FUNC_CTL_B 0x61400
	+#define TRANS_DDI_FUNC_CTL_C 0x62400
	+#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
	+#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
	+ TRANS_DDI_FUNC_CTL_B)
	+#define TRANS_DDI_FUNC_ENABLE (1<<31)
	/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
	-#define PIPE_DDI_PORT_MASK (0xf<<28)
	-#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
	-#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
	-#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
	-#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
	-#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
	-#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
	-#define PIPE_DDI_BPC_8 (0<<20)
	-#define PIPE_DDI_BPC_10 (1<<20)
	-#define PIPE_DDI_BPC_6 (2<<20)
	-#define PIPE_DDI_BPC_12 (3<<20)
	-#define PIPE_DDI_BFI_ENABLE (1<<4)
	-#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
	-#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
	-#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
	+#define TRANS_DDI_PORT_MASK (7<<28)
	+#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
	+#define TRANS_DDI_PORT_NONE (0<<28)
	+#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
	+#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
	+#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
	+#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
	+#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
	+#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
	+#define TRANS_DDI_BPC_MASK (7<<20)
	+#define TRANS_DDI_BPC_8 (0<<20)
	+#define TRANS_DDI_BPC_10 (1<<20)
	+#define TRANS_DDI_BPC_6 (2<<20)
	+#define TRANS_DDI_BPC_12 (3<<20)
	+#define TRANS_DDI_PVSYNC (1<<17)
	+#define TRANS_DDI_PHSYNC (1<<16)
	+#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
	+#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
	+#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
	+#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
	+#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
	+#define TRANS_DDI_BFI_ENABLE (1<<4)
	+#define TRANS_DDI_PORT_WIDTH_X1 (0<<1)
	+#define TRANS_DDI_PORT_WIDTH_X2 (1<<1)
	+#define TRANS_DDI_PORT_WIDTH_X4 (3<<1)

	/* DisplayPort Transport Control */
	#define DP_TP_CTL_A 0x64040
	#define DP_TP_CTL_B 0x64140
	-#define DP_TP_CTL(port) _PORT(port, \
	- DP_TP_CTL_A, \
	- DP_TP_CTL_B)
	-#define DP_TP_CTL_ENABLE (1<<31)
	-#define DP_TP_CTL_MODE_SST (0<<27)
	-#define DP_TP_CTL_MODE_MST (1<<27)
	+#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
	+#define DP_TP_CTL_ENABLE (1<<31)
	+#define DP_TP_CTL_MODE_SST (0<<27)
	+#define DP_TP_CTL_MODE_MST (1<<27)
	#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
	-#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
	+#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
	#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
	#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
	#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
	-#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
	+#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
	+#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
	+#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
	+#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)

	/* DisplayPort Transport Status */
	#define DP_TP_STATUS_A 0x64044
	#define DP_TP_STATUS_B 0x64144
	-#define DP_TP_STATUS(port) _PORT(port, \
	- DP_TP_STATUS_A, \
	- DP_TP_STATUS_B)
	+#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
	+#define DP_TP_STATUS_IDLE_DONE (1<<25)
	#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)

	/* DDI Buffer Control */
	#define DDI_BUF_CTL_A 0x64000
	#define DDI_BUF_CTL_B 0x64100
	-#define DDI_BUF_CTL(port) _PORT(port, \
	- DDI_BUF_CTL_A, \
	- DDI_BUF_CTL_B)
	-#define DDI_BUF_CTL_ENABLE (1<<31)
	+#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
	+#define DDI_BUF_CTL_ENABLE (1<<31)
	#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
	-#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
	+#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
	#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
	-#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
	+#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
	#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
	-#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
	+#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
	#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
	#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
	-#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
	-#define DDI_BUF_EMP_MASK (0xf<<24)
	-#define DDI_BUF_IS_IDLE (1<<7)
	-#define DDI_PORT_WIDTH_X1 (0<<1)
	-#define DDI_PORT_WIDTH_X2 (1<<1)
	-#define DDI_PORT_WIDTH_X4 (3<<1)
	+#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
	+#define DDI_BUF_EMP_MASK (0xf<<24)
	+#define DDI_BUF_PORT_REVERSAL (1<<16)
	+#define DDI_BUF_IS_IDLE (1<<7)
	+#define DDI_A_4_LANES (1<<4)
	+#define DDI_PORT_WIDTH_X1 (0<<1)
	+#define DDI_PORT_WIDTH_X2 (1<<1)
	+#define DDI_PORT_WIDTH_X4 (3<<1)
	#define DDI_INIT_DISPLAY_DETECTED (1<<0)

	/* DDI Buffer Translations */
	#define DDI_BUF_TRANS_A 0x64E00
	#define DDI_BUF_TRANS_B 0x64E60
	-#define DDI_BUF_TRANS(port) _PORT(port, \
	- DDI_BUF_TRANS_A, \
	- DDI_BUF_TRANS_B)
	+#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)

	/* Sideband Interface (SBI) is programmed indirectly, via
	* SBI_ADDR, which contains the register offset; and SBI_DATA,
	* which contains the payload */
	-#define SBI_ADDR 0xC6000
	-#define SBI_DATA 0xC6004
	+#define SBI_ADDR 0xC6000
	+#define SBI_DATA 0xC6004
	#define SBI_CTL_STAT 0xC6008
	+#define SBI_CTL_DEST_ICLK (0x0<<16)
	+#define SBI_CTL_DEST_MPHY (0x1<<16)
	+#define SBI_CTL_OP_IORD (0x2<<8)
	+#define SBI_CTL_OP_IOWR (0x3<<8)
	#define SBI_CTL_OP_CRRD (0x6<<8)
	#define SBI_CTL_OP_CRWR (0x7<<8)
	#define SBI_RESPONSE_FAIL (0x1<<1)
	-#define SBI_RESPONSE_SUCCESS (0x0<<1)
	-#define SBI_BUSY (0x1<<0)
	-#define SBI_READY (0x0<<0)
	+#define SBI_RESPONSE_SUCCESS (0x0<<1)
	+#define SBI_BUSY (0x1<<0)
	+#define SBI_READY (0x0<<0)

	/* SBI offsets */
	-#define SBI_SSCDIVINTPHASE6 0x0600
	+#define SBI_SSCDIVINTPHASE6 0x0600
	#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
	#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
	#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
	#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
	-#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
	+#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
	#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
	-#define SBI_SSCCTL 0x020c
	+#define SBI_SSCCTL 0x020c
	#define SBI_SSCCTL6 0x060C
	-#define SBI_SSCCTL_DISABLE (1<<0)
	+#define SBI_SSCCTL_PATHALT (1<<3)
	+#define SBI_SSCCTL_DISABLE (1<<0)
	#define SBI_SSCAUXDIV6 0x0610
	#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
	-#define SBI_DBUFF0 0x2a00
	+#define SBI_DBUFF0 0x2a00
	+#define SBI_DBUFF0_ENABLE (1<<0)

	/* LPT PIXCLK_GATE */
	-#define PIXCLK_GATE 0xC6020
	-#define PIXCLK_GATE_UNGATE 1<<0
	-#define PIXCLK_GATE_GATE 0<<0
	+#define PIXCLK_GATE 0xC6020
	+#define PIXCLK_GATE_UNGATE (1<<0)
	+#define PIXCLK_GATE_GATE (0<<0)

	/* SPLL */
	-#define SPLL_CTL 0x46020
	+#define SPLL_CTL 0x46020
	#define SPLL_PLL_ENABLE (1<<31)
	-#define SPLL_PLL_SCC (1<<28)
	-#define SPLL_PLL_NON_SCC (2<<28)
	-#define SPLL_PLL_FREQ_810MHz (0<<26)
	-#define SPLL_PLL_FREQ_1350MHz (1<<26)
	+#define SPLL_PLL_SSC (1<<28)
	+#define SPLL_PLL_NON_SSC (2<<28)
	+#define SPLL_PLL_FREQ_810MHz (0<<26)
	+#define SPLL_PLL_FREQ_1350MHz (1<<26)

	/* WRPLL */
	-#define WRPLL_CTL1 0x46040
	-#define WRPLL_CTL2 0x46060
	-#define WRPLL_PLL_ENABLE (1<<31)
	-#define WRPLL_PLL_SELECT_SSC (0x01<<28)
	-#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
	+#define WRPLL_CTL1 0x46040
	+#define WRPLL_CTL2 0x46060
	+#define WRPLL_PLL_ENABLE (1<<31)
	+#define WRPLL_PLL_SELECT_SSC (0x01<<28)
	+#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
	#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
	/* WRPLL divider programming */
	-#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
	-#define WRPLL_DIVIDER_POST(x) ((x)<<8)
	-#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
	+#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
	+#define WRPLL_DIVIDER_POST(x) ((x)<<8)
	+#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)

	/* Port clock selection */
	#define PORT_CLK_SEL_A 0x46100
	#define PORT_CLK_SEL_B 0x46104
	-#define PORT_CLK_SEL(port) _PORT(port, \
	- PORT_CLK_SEL_A, \
	- PORT_CLK_SEL_B)
	+#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
	#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
	#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
	#define PORT_CLK_SEL_LCPLL_810 (2<<29)
	-#define PORT_CLK_SEL_SPLL (3<<29)
	+#define PORT_CLK_SEL_SPLL (3<<29)
	#define PORT_CLK_SEL_WRPLL1 (4<<29)
	#define PORT_CLK_SEL_WRPLL2 (5<<29)
	+#define PORT_CLK_SEL_NONE (7<<29)
	+
	+/* Transcoder clock selection */
	+#define TRANS_CLK_SEL_A 0x46140
	+#define TRANS_CLK_SEL_B 0x46144
	+#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
	+/* For each transcoder, we need to select the corresponding port clock */
	+#define TRANS_CLK_SEL_DISABLED (0x0<<29)
	+#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)

	/* Pipe clock selection */
	#define PIPE_CLK_SEL_A 0x46140
	@@ -4316,29 +4710,46 @@
	/* For each pipe, we need to select the corresponding port clock */
	#define PIPE_CLK_SEL_DISABLED (0x0<<29)
	#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
	+#define _TRANSA_MSA_MISC 0x60410
	+#define _TRANSB_MSA_MISC 0x61410
	+#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
	+ _TRANSB_MSA_MISC)
	+#define TRANS_MSA_SYNC_CLK (1<<0)
	+#define TRANS_MSA_6_BPC (0<<5)
	+#define TRANS_MSA_8_BPC (1<<5)
	+#define TRANS_MSA_10_BPC (2<<5)
	+#define TRANS_MSA_12_BPC (3<<5)
	+#define TRANS_MSA_16_BPC (4<<5)

	/* LCPLL Control */
	-#define LCPLL_CTL 0x130040
	+#define LCPLL_CTL 0x130040
	#define LCPLL_PLL_DISABLE (1<<31)
	#define LCPLL_PLL_LOCK (1<<30)
	-#define LCPLL_CD_CLOCK_DISABLE (1<<25)
	+#define LCPLL_CLK_FREQ_MASK (3<<26)
	+#define LCPLL_CLK_FREQ_450 (0<<26)
	+#define LCPLL_CD_CLOCK_DISABLE (1<<25)
	#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
	+#define LCPLL_CD_SOURCE_FCLK (1<<21)

	/* Pipe WM_LINETIME - watermark line time */
	#define PIPE_WM_LINETIME_A 0x45270
	#define PIPE_WM_LINETIME_B 0x45274
	-#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
	- PIPE_WM_LINETIME_A, \
	- PIPE_WM_LINETIME_A)
	-#define PIPE_WM_LINETIME_MASK (0x1ff)
	-#define PIPE_WM_LINETIME_TIME(x) ((x))
	+#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
	+ PIPE_WM_LINETIME_B)
	+#define PIPE_WM_LINETIME_MASK (0x1ff)
	+#define PIPE_WM_LINETIME_TIME(x) ((x))
	#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
	-#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
	+#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)

	/* SFUSE_STRAP */
	-#define SFUSE_STRAP 0xc2014
	+#define SFUSE_STRAP 0xc2014
	#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
	#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
	#define SFUSE_STRAP_DDID_DETECTED (1<<0)

	+#define WM_DBG 0x45280
	+#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
	+#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
	+#define WM_DBG_DISALLOW_SPRITE (1<<2)
	+
	#endif /* _I915_REG_H_ */
	Index: sys/dev/drm2/i915/intel_ddi.c
	===================================================================
	--- sys/dev/drm2/i915/intel_ddi.c
	+++ sys/dev/drm2/i915/intel_ddi.c
	@@ -146,7 +146,7 @@
	I915_WRITE(SPLL_CTL,
	SPLL_PLL_ENABLE \|
	SPLL_PLL_FREQ_1350MHz \|
	- SPLL_PLL_SCC);
	+ SPLL_PLL_SSC);

	/* Use SPLL to drive the output when in FDI mode */
	I915_WRITE(PORT_CLK_SEL(PORT_E),
	@@ -200,14 +200,14 @@
	DP_TP_CTL_ENHANCED_FRAME_ENABLE \|
	DP_TP_CTL_ENABLE);

	- /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */
	- temp = I915_READ(DDI_FUNC_CTL(pipe));
	- temp &= ~PIPE_DDI_PORT_MASK;
	- temp \|= PIPE_DDI_SELECT_PORT(PORT_E) \|
	- PIPE_DDI_MODE_SELECT_FDI \|
	- PIPE_DDI_FUNC_ENABLE \|
	- PIPE_DDI_PORT_WIDTH_X2;
	- I915_WRITE(DDI_FUNC_CTL(pipe),
	+ /* Enable PIPE_TRANS_DDI_FUNC_CTL for the pipe to work in FDI mode */
	+ temp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
	+ temp &= ~TRANS_DDI_PORT_MASK;
	+ temp \|= TRANS_DDI_SELECT_PORT(PORT_E) \|
	+ TRANS_DDI_MODE_SELECT_FDI \|
	+ TRANS_DDI_FUNC_ENABLE \|
	+ TRANS_DDI_PORT_WIDTH_X2;
	+ I915_WRITE(TRANS_DDI_FUNC_CTL(pipe),
	temp);
	break;
	} else {
	@@ -719,18 +719,18 @@
	pipe_name(intel_crtc->pipe));
	}

	- /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
	- temp = I915_READ(DDI_FUNC_CTL(pipe));
	- temp &= ~PIPE_DDI_PORT_MASK;
	- temp &= ~PIPE_DDI_BPC_12;
	- temp \|= PIPE_DDI_SELECT_PORT(port) \|
	- PIPE_DDI_MODE_SELECT_HDMI \|
	+ /* Enable PIPE_TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
	+ temp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
	+ temp &= ~TRANS_DDI_PORT_MASK;
	+ temp &= ~TRANS_DDI_BPC_12;
	+ temp \|= TRANS_DDI_SELECT_PORT(port) \|
	+ TRANS_DDI_MODE_SELECT_HDMI \|
	((intel_crtc->bpp > 24) ?
	- PIPE_DDI_BPC_12 :
	- PIPE_DDI_BPC_8) \|
	- PIPE_DDI_FUNC_ENABLE;
	+ TRANS_DDI_BPC_12 :
	+ TRANS_DDI_BPC_8) \|
	+ TRANS_DDI_FUNC_ENABLE;

	- I915_WRITE(DDI_FUNC_CTL(pipe), temp);
	+ I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), temp);

	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	Index: sys/dev/drm2/i915/intel_display.c
	===================================================================
	--- sys/dev/drm2/i915/intel_display.c
	+++ sys/dev/drm2/i915/intel_display.c
	@@ -974,9 +974,9 @@

	if (IS_HASWELL(dev_priv->dev)) {
	/* On Haswell, DDI is used instead of FDI_TX_CTL */
	- reg = DDI_FUNC_CTL(pipe);
	+ reg = TRANS_DDI_FUNC_CTL(pipe);
	val = I915_READ(reg);
	- cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
	+ cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
	} else {
	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	@@ -1878,13 +1878,13 @@
	break;
	case 16:
	if (fb->depth == 15)
	- dspcntr \|= DISPPLANE_15_16BPP;
	+ dspcntr \|= DISPPLANE_BGRX555;
	else
	- dspcntr \|= DISPPLANE_16BPP;
	+ dspcntr \|= DISPPLANE_BGRX565;
	break;
	case 24:
	case 32:
	- dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
	+ dspcntr \|= DISPPLANE_BGRX888;
	break;
	default:
	DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
	@@ -1956,14 +1956,14 @@
	return -EINVAL;
	}

	- dspcntr \|= DISPPLANE_16BPP;
	+ dspcntr \|= DISPPLANE_BGRX565;
	break;
	case 24:
	case 32:
	if (fb->depth == 24)
	- dspcntr \|= DISPPLANE_32BPP_NO_ALPHA;
	+ dspcntr \|= DISPPLANE_BGRX888;
	else if (fb->depth == 30)
	- dspcntr \|= DISPPLANE_32BPP_30BIT_NO_ALPHA;
	+ dspcntr \|= DISPPLANE_BGRX101010;
	else {
	DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
	fb->depth);
	Index: sys/dev/drm2/i915/intel_pm.c
	===================================================================
	--- sys/dev/drm2/i915/intel_pm.c
	+++ sys/dev/drm2/i915/intel_pm.c
	@@ -3301,7 +3301,7 @@

	/* Bspec says we need to always set all mask bits. */
	I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) \|
	- _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
	+ _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);

	/*
	* According to the spec the following bits should be

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