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Index: sys/amd64/include/cpufunc.h
===================================================================
--- sys/amd64/include/cpufunc.h
+++ sys/amd64/include/cpufunc.h
@@ -45,6 +45,8 @@
#error this file needs sys/cdefs.h as a prerequisite
#endif
+#include <machine/psl.h>
+
struct region_descriptor;
#define readb(va) (*(volatile uint8_t *) (va))
@@ -836,6 +838,13 @@
write_rflags(rflags);
}
+static __inline int
+interrupts_enabled(void)
+{
+
+ return ((read_rflags() & PSL_I) != 0);
+}
+
static __inline void
stac(void)
{
Index: sys/arm/include/cpufunc.h
===================================================================
--- sys/arm/include/cpufunc.h
+++ sys/arm/include/cpufunc.h
@@ -450,6 +450,16 @@
restore_interrupts(s);
}
+
+static __inline int
+interrupts_enabled(void)
+{
+ register_t ret;
+
+ __asm __volatile("mrs %0, cpsr" : "=&r" (ret));
+
+ return ((ret & __ARM_INTR_BITS) != 0);
+}
#undef __ARM_INTR_BITS
/*
Index: sys/arm64/include/cpufunc.h
===================================================================
--- sys/arm64/include/cpufunc.h
+++ sys/arm64/include/cpufunc.h
@@ -90,6 +90,16 @@
__asm __volatile("msr daifclr, #2");
}
+static __inline int
+interrupts_enabled(void)
+{
+ register_t ret;
+
+ __asm __volatile("mrs %x0, daif" : "=&r" (ret));
+
+ return ((ret & (PSR_I | PSR_F)) != 0);
+}
+
static __inline register_t
get_midr(void)
{
Index: sys/i386/include/cpufunc.h
===================================================================
--- sys/i386/include/cpufunc.h
+++ sys/i386/include/cpufunc.h
@@ -44,6 +44,8 @@
#error this file needs sys/cdefs.h as a prerequisite
#endif
+#include <machine/psl.h>
+
struct region_descriptor;
#define readb(va) (*(volatile uint8_t *) (va))
@@ -691,6 +693,13 @@
write_eflags(eflags);
}
+static __inline int
+interrupts_enabled(void)
+{
+
+ return ((read_eflags() & PSL_I) != 0);
+}
+
#else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
int breakpoint(void);
Index: sys/mips/include/cpufunc.h
===================================================================
--- sys/mips/include/cpufunc.h
+++ sys/mips/include/cpufunc.h
@@ -345,6 +345,13 @@
}
}
+static __inline int
+interrupts_enabled(void)
+{
+
+ return ((mips_rd_status() & MIPS_SR_INT_IE) != 0);
+}
+
static __inline uint32_t
set_intr_mask(uint32_t mask)
{
Index: sys/powerpc/include/cpufunc.h
===================================================================
--- sys/powerpc/include/cpufunc.h
+++ sys/powerpc/include/cpufunc.h
@@ -202,6 +202,13 @@
mtmsr(msr);
}
+static __inline int
+interrupts_enabled(void)
+{
+
+ return ((mfmsr() & PSL_EE) != 0);
+}
+
static __inline struct pcpu *
get_pcpu(void)
{
Index: sys/riscv/include/cpufunc.h
===================================================================
--- sys/riscv/include/cpufunc.h
+++ sys/riscv/include/cpufunc.h
@@ -81,6 +81,20 @@
);
}
+static __inline int
+interrupts_enabled(void)
+{
+
+ register_t ret;
+
+ __asm __volatile(
+ "csrr %0, sstatus"
+ : "=&r" (ret)
+ );
+
+ return ((ret & SSTATUS_SIE) != 0);
+}
+
#define cpu_nullop() riscv_nullop()
#define cpufunc_nullop() riscv_nullop()
#define cpu_setttb(a) riscv_setttb(a)
Index: sys/sparc64/include/cpufunc.h
===================================================================
--- sys/sparc64/include/cpufunc.h
+++ sys/sparc64/include/cpufunc.h
@@ -223,6 +223,13 @@
}
#define intr_restore(s) wrpr(pstate, (s), 0)
+static __inline int
+interrupts_enabled(void)
+{
+
+ return ((rdpr(pstate) & PSTATE_IE) != 0);
+}
+
/*
* In some places, it is required that the store is directly followed by a
* membar #Sync. Don't trust the compiler to not insert instructions in

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