D50209.id54425.diff
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D50209.id54425.diff
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	diff --git a/sys/arm/arm/generic_timer.c b/sys/arm/arm/generic_timer.c
	--- a/sys/arm/arm/generic_timer.c
	+++ b/sys/arm/arm/generic_timer.c
	@@ -289,20 +289,22 @@
	}

	#ifdef __aarch64__
	-static int
	-cntpct_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
	- uint32_t esr)
	+static bool
	+cntpct_handler(uint64_t esr, struct trapframe *frame)
	{
	uint64_t val;
	int reg;

	- if ((insn & MRS_MASK) != MRS_VALUE)
	- return (0);
	+ if (ESR_ELx_EXCEPTION(esr) != EXCP_MSR)
	+ return (false);

	- if (MRS_SPECIAL(insn) != MRS_SPECIAL(CNTPCT_EL0))
	- return (0);
	+ if ((esr & ISS_MSR_DIR) == 0)
	+ return (false);
	+
	+ if ((esr & ISS_MSR_REG_MASK) != CNTPCT_EL0_ISS)
	+ return (false);

	- reg = MRS_REGISTER(insn);
	+ reg = ISS_MSR_Rt(esr);
	val = READ_SPECIALREG(cntvct_el0);
	if (reg < nitems(frame->tf_x)) {
	frame->tf_x[reg] = val;
	@@ -316,7 +318,7 @@
	*/
	frame->tf_elr += INSN_SIZE;

	- return (1);
	+ return (true);
	}
	#endif

	@@ -332,7 +334,7 @@
	#ifdef __aarch64__
	if (TUNABLE_INT_FETCH("hw.emulate_phys_counter", &emulate) &&
	emulate != 0) {
	- install_undef_handler(cntpct_handler);
	+ install_sys_handler(cntpct_handler);
	}
	#endif
	}
	diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
	--- a/sys/arm64/include/armreg.h
	+++ b/sys/arm64/include/armreg.h
	@@ -278,6 +278,7 @@

	/* CNTPCT_EL0 - Counter-timer Physical Count register */
	#define CNTPCT_EL0 MRS_REG(CNTPCT_EL0)
	+#define CNTPCT_EL0_ISS ISS_MSR_REG(CNTPCT_EL0)
	#define CNTPCT_EL0_op0 3
	#define CNTPCT_EL0_op1 3
	#define CNTPCT_EL0_CRn 14