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diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c
--- a/sys/x86/cpufreq/hwpstate_amd.c
+++ b/sys/x86/cpufreq/hwpstate_amd.c
@@ -429,10 +429,9 @@
}
static int
-sysctl_epp_handler(SYSCTL_HANDLER_ARGS)
+sysctl_cppc_request_field_handler(SYSCTL_HANDLER_ARGS)
{
- const u_int max_epp =
- BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, (uint64_t)-1);
+ const u_int max = BITS_VALUE(arg2, (uint64_t)-1);
const device_t dev = arg1;
struct hwpstate_softc *const sc = device_get_softc(dev);
u_int val;
@@ -441,17 +440,16 @@
/* Sysctl knob does not exist if PSTATE_CPPC is not set. */
check_cppc_enabled(sc, __func__);
- val = BITS_VALUE(AMD_CPPC_REQUEST_EPP_BITS, sc->cppc.request);
+ val = BITS_VALUE(arg2, sc->cppc.request);
error = sysctl_handle_int(oidp, &val, 0, req);
if (error != 0 || req->newptr == NULL)
return (error);
- if (val > max_epp)
+ if (val > max)
return (EINVAL);
- error = set_cppc_request(dev,
- BITS_WITH_VALUE(AMD_CPPC_REQUEST_EPP_BITS, val),
- BITS_WITH_VALUE(AMD_CPPC_REQUEST_EPP_BITS, -1));
+ error = set_cppc_request(dev, BITS_WITH_VALUE(arg2, val),
+ BITS_WITH_VALUE(arg2, -1));
return (error);
}
@@ -921,10 +919,39 @@
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
- "epp", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, dev, 0,
- sysctl_epp_handler, "IU",
+ "epp", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
+ dev, AMD_CPPC_REQUEST_EPP_BITS,
+ sysctl_cppc_request_field_handler, "IU",
"Efficiency/Performance Preference "
"(range from 0, most performant, through 255, most efficient)");
+
+ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+ SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
+ "min_perf", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
+ dev, AMD_CPPC_REQUEST_MIN_PERF_BITS,
+ sysctl_cppc_request_field_handler, "IU",
+ "Minimum allowed performance level (from 0 to 255, "
+ "must be smaller than 'max_perf', "
+ "effective range limited by CPU capabilities)");
+
+ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+ SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
+ "max_perf", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
+ dev, AMD_CPPC_REQUEST_MAX_PERF_BITS,
+ sysctl_cppc_request_field_handler, "IU",
+ "Maximum allowed performance level (from 0 to 255, "
+ "must be greater than 'min_perf', "
+ "effective range limited by CPU capabilities)");
+
+ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+ SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
+ "desired_perf", CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
+ dev, AMD_CPPC_REQUEST_DES_PERF_BITS,
+ sysctl_cppc_request_field_handler, "IU",
+ "Desired performance (from 0 to 255, "
+ "0 means autonomous mode enabled, "
+ "otherwise value must be between 'min_perf' "
+ "and 'max_perf' inclusive)");
}
return (cpufreq_register(dev));
}

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