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D48187.id151913.diff
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diff --git a/sys/amd64/vmm/x86.c b/sys/amd64/vmm/x86.c
--- a/sys/amd64/vmm/x86.c
+++ b/sys/amd64/vmm/x86.c
@@ -150,8 +150,6 @@
* pkg_id_shift and other OSes may rely on it.
*/
width = MIN(0xF, log2(threads * cores));
- if (width < 0x4)
- width = 0;
logical_cpus = MIN(0xFF, threads * cores - 1);
regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus;
}
@@ -256,7 +254,7 @@
func = 3; /* unified cache */
break;
default:
- logical_cpus = 0;
+ logical_cpus = sockets * threads * cores;
level = 0;
func = 0;
break;
@@ -266,7 +264,14 @@
regs[0] = (logical_cpus << 14) | (1 << 8) |
(level << 5) | func;
regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;
+
+ /*
+ * ecx: Number of cache ways for non-fully
+ * associative cache, minus 1. Reported value
+ * of zero means there is one way.
+ */
regs[2] = 0;
+
regs[3] = 0;
break;
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D48187.id151913.diff (946 B)
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D48187: bhyve: fix CPUID L3 Cache Size reporting for AMD/SVM
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