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Index: sys/arm64/cavium/thunder_pcie_pem.h
===================================================================
--- sys/arm64/cavium/thunder_pcie_pem.h
+++ sys/arm64/cavium/thunder_pcie_pem.h
@@ -48,6 +48,9 @@
uint32_t sli;
uint32_t sli_group;
uint64_t sli_window_base;
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ int pci_domain;
+#endif
};
#endif
Index: sys/arm64/cavium/thunder_pcie_pem.c
===================================================================
--- sys/arm64/cavium/thunder_pcie_pem.c
+++ sys/arm64/cavium/thunder_pcie_pem.c
@@ -313,6 +313,11 @@
struct rman *rm;
sc = device_get_softc(dev);
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ if (type == PCI_RES_BUS)
+ return (pci_domain_adjust_bus(sc->pci_domain, child, res,
+ start, end));
+#endif
rm = thunder_pem_rman(sc, type);
if (rm == NULL)
@@ -619,6 +624,11 @@
struct resource *res;
device_t parent_dev;
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ if (type == PCI_RES_BUS)
+ return (pci_domain_alloc_bus(sc->pci_domain, child, rid, start,
+ end, count, flags));
+#endif
rm = thunder_pem_rman(sc, type);
if (rm == NULL) {
/* Find parent device. On ThunderX we know an exact path. */
@@ -675,7 +685,13 @@
struct resource *res)
{
device_t parent_dev;
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ struct thunder_pem_softc *sc = device_get_softc(dev);
+ if (type == PCI_RES_BUS)
+ return (pci_domain_release_bus(sc->pci_domain, child, rid,
+ res));
+#endif
/* Find parent device. On ThunderX we know an exact path. */
parent_dev = device_get_parent(device_get_parent(dev));
@@ -773,6 +789,10 @@
if (thunder_pem_identify(dev) != 0)
goto fail;
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ sc->pci_domain = pci_alloc_domain();
+#endif
+
/* Initialize rman and allocate regions */
sc->mem_rman.rm_type = RMAN_ARRAY;
sc->mem_rman.rm_descr = "PEM PCIe Memory";
Index: sys/dev/pci/pci_host_generic.h
===================================================================
--- sys/dev/pci/pci_host_generic.h
+++ sys/dev/pci/pci_host_generic.h
@@ -61,6 +61,9 @@
#ifdef FDT
struct ofw_bus_iinfo pci_iinfo;
#endif
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ int pci_domain;
+#endif
};
extern devclass_t generic_pcie_devclass;
Index: sys/dev/pci/pci_host_generic.c
===================================================================
--- sys/dev/pci/pci_host_generic.c
+++ sys/dev/pci/pci_host_generic.c
@@ -188,6 +188,10 @@
return (ENXIO);
}
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ sc->pci_domain = pci_alloc_domain();
+#endif
+
sc->bst = rman_get_bustag(sc->res);
sc->bsh = rman_get_bushandle(sc->res);
@@ -501,7 +505,15 @@
generic_pcie_release_resource(device_t dev, device_t child, int type,
int rid, struct resource *res)
{
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ struct generic_pcie_softc *sc;
+ if (type == PCI_RES_BUS) {
+ sc = device_get_softc(dev);
+ return (pci_domain_release_bus(sc->pci_domain, child, rid,
+ res));
+ }
+#endif
/* For PCIe devices that do not have FDT nodes, use PCIB method */
if ((int)ofw_bus_get_node(child) <= 0) {
return (generic_pcie_release_resource_pcie(dev,
@@ -517,7 +529,15 @@
pci_host_generic_alloc_resource(device_t dev, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ struct generic_pcie_softc *sc;
+ if (type == PCI_RES_BUS) {
+ sc = device_get_softc(dev);
+ return (pci_domain_alloc_bus(sc->pci_domain, child, rid,
+ start, end, count, flags));
+ }
+#endif
/* For PCIe devices that do not have FDT nodes, use PCIB method */
if ((int)ofw_bus_get_node(child) <= 0)
return (generic_pcie_alloc_resource_pcie(dev, child, type, rid,
@@ -579,6 +599,11 @@
struct rman *rm;
sc = device_get_softc(dev);
+#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+ if (type == PCI_RES_BUS)
+ return (pci_domain_adjust_bus(sc->pci_domain, child, res,
+ start, end));
+#endif
rm = generic_pcie_rman(sc, type);
if (rm != NULL)
Index: sys/dev/pci/pci_subr.c
===================================================================
--- sys/dev/pci/pci_subr.c
+++ sys/dev/pci/pci_subr.c
@@ -292,6 +292,20 @@
};
static TAILQ_HEAD(, pci_domain) domains = TAILQ_HEAD_INITIALIZER(domains);
+static int pci_next_domain;
+
+/*
+ * Allocate a domain to be used by pci_find_domain. This is used on platforms
+ * where the domain is not profided by the firmware, e.g. on ACPI or FDT.
+ * If any drivers use the value returned from this then all drivers must use
+ * this function to allocate domain IDs. This is a requirement on FDT.
+ */
+int
+pci_alloc_domain(void)
+{
+
+ return (atomic_fetchadd_int(&pci_next_domain, 1));
+}
/*
* Each PCI domain maintains its own resource manager for PCI bus
Index: sys/dev/pci/pcib_private.h
===================================================================
--- sys/dev/pci/pcib_private.h
+++ sys/dev/pci/pcib_private.h
@@ -149,6 +149,7 @@
int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
int slot, int func, uint8_t *busnum);
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
+int pci_alloc_domain(void);
struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
int pci_domain_adjust_bus(int domain, device_t dev,

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